Post on 23-Apr-2018
transcript
BRIAN ZIMMER
• Email: bmzimmer@eecs.berkeley.edu• Website: http://eecs.berkeley.edu/~bmzimmer/• Discussion Sections: Thursdays, 5pm-6pm, 320 Soda Hall• Office Hours: Tuesdays, 1pm-2pm, 550 Cory Hall (if
undergrad, just knock on the door)• Questions?: Ask on piazza.com, only email me if you are
sure nobody else would be interested in the answer…• I will respond just as fast as if were an email…
Thursday, September 1, 2011
LOGISTICS
• Has everyone successfully setup everything?
• Piazza
• Github• SSH
• NoMachine (NX)
• Lab #1 is out, due in < 2 weeks
Thursday, September 1, 2011
MACHINE ASSIGNMENTS
• NoMachine has a limit of two users, so you will be assigned to share a machine with someone
• When projects start, each group will have their own machine
Thursday, September 1, 2011
REMEMBER!
• NEVER post materials online
• Tools
• Documents• Technology files
• Methodology Scripts
• Which also means google won’t help much if you’re stuck…
Thursday, September 1, 2011
HOW? THREE LABS + PROJECT
• Lab 1: GCD: VLSI’s Hello World• 8/29 to 9/12 (two weeks)
• Lab 2: Write and synthesize a Two-Stage Processor• 9/12 to 9/26 (two weeks)
• Lab 3: ASIC Implementation of a RISC-V v2 Core with On-Chip Caches • 9/26 to 10/17 (three weeks)
• Project (groups of two)• Given a processor as a baseline• Explore micro-architectural variations to improve performance or
energy efficiency
Thursday, September 1, 2011
PROCESS
• Synopsys 90nm Educational Library• Can use without an NDA (not a real process)• Whole source: ~/cs250/stdcells/vendor• 9 metal layers• Standard cells, SRAM• IO Pads• Also includes need files for custom design• Easy physical design• Tutorial coming soon…
Thursday, September 1, 2011
LAB LOGISTICS
• You will turn in by pushing to github repos
• Your report should be put in the repo as well
• Labs are 25% of your grade
• Each student gets a total of four late days
Thursday, September 1, 2011
TIPS
• Be efficient: • Learn bash/vim well• Learn how to debug• Learn how to script
• Document• If it took you more than 5 minutes to figure out, write it down
• Draw it first• Will save time in the long run
• Do the tutorials• Start early• Asking questions also saves time, so start early enough that you have time to
ask
Thursday, September 1, 2011
FINDING HELP
• Optional Book: Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, by Erik Brunvand• Not just about VLSI tools…will give a broader perspective
• Download the manuals!• ~cs250/manuals/
• Piazza• Beware of googling…• Chisel will have nothing, most tools under NDAs
Thursday, September 1, 2011
OTHER TOOLS• Instructional• Ack: Search for text recursively. To install:• mkdir bin; curl http://betterthangrep.com/ack-standalone > ~/bin/ack && chmod 0755 !#:3
• To .bash_profile, add the line “export PATH=~/bin:$PATH”
• Bash/Vim:• My settings: https://github.com/brianzimmer/dotfiles Take what you want…but make
sure you read through every file to put your own name/preferences in and understand what every line does
• Evernote• Great way to document (take a screenshot, paste in code, etc)• In this class, there will be many one-line tricks/code snippets/etc that should
be recorded for future reference
• OS X• Quicksilver• Command-{• Size-up• iTerm
Thursday, September 1, 2011
TOOL FLOW OVERVIEW
• vcs-sim-rtl: Does the RTL work as expected?
• dc-syn: Synthesis: transform RTL to standard cells
• vcs-sim-gl-syn: Do the standard cells work as expected?
• icc-par : Place & Route: layout and connect standard cells
• vcs-sim-gl-par : Does the layout work as expected?
• pt-pwr: Analyze the final design (power)
Thursday, September 1, 2011
STANDARD CELL BASED DESIGN - SYNTHESIS
• ~cs250/stdcells/synopsys-90nm/vendor/SAED_EDK90nm/Digital_Standard_Cell_Library/doc/databook
Thursday, September 1, 2011
FUTURE DISCUSSIONS
• Bring your laptop!
• Please keep coming…these are meant to save you time in the long run
• I’m open to recommendations regarding what material to cover…email me if you would really like to see anything in particular covered
Thursday, September 1, 2011
IF TIME: LAB 1 DISCUSSIONGreatest Common Divisor
• Euclidean Algorithm
• START (A, B)
• if (A < B)
• SWAP (A, B)
• else if (B != 0)
• SUBTRACT (A-B, B)
• else
• DONE gcd=A
START (32, 48)A<B SWAP (48, 32)B!=0 SUBTRACT (16, 32)A<B SWAP (32, 16)B!=0 SUBTRACT (16, 16)B!=0 SUBTRACT (0, 16)A<B SWAP (16, 0)B=0 DONE GCD=16
Thursday, September 1, 2011
SO DESIGN IT!
• Split into datapath and control
• Figure out how many states you need and how to transition between states
• Figure out how what control signals your control needs to generate for your datapath
Thursday, September 1, 2011
PARTIAL ANSWER…Tick-tock!
B
A_lt_B B_zero
zero? lt
A
sub
A_mux_sel
A_en
B_mux_sel
B_en
operands_val
operands_rdy
result_val
result_rdy
operands_A
operands_B
result
WAIT
CALC
DONE
Waiting for new input operands
Swapping and subtracting
Waiting for consumer to take the result
reset
Thursday, September 1, 2011