Post on 06-Feb-2018
transcript
Outline Introduction Design toolchain Basic Elements Demo - FFT calculation Summary
Xilinx FPGA design using Simulink with HardwareCo-Simulation
Miko laj Chwalisz(chwalisz@tkn.tu-berlin.de)
Technische Universitat BerlinTelecommunication Networks Group (TKN)
April 28, 2011
TKNTelecommunication
Networks Group
Outline Introduction Design toolchain Basic Elements Demo - FFT calculation Summary
Outline
1 Introduction
2 Design toolchain
3 Basic Elements
4 Demo - FFT calculation
5 Summary
2 / 17
Outline Introduction Design toolchain Basic Elements Demo - FFT calculation Summary
Simulink based FPGA design model
Simulink
Environment for multidomain simulation and Model-Based Designfor dynamic and embedded systems.
Xilinx System Generator
High-level tool for designing high-performance DSP systems usingFPGAs.
Replace HDL language with Simulink blocks
Xilinx Blockset contains many functions
Possibility to use HDL modules as black boxes
Ease of simulation and testbench
Compilation to bitstream, HDL, hardware co-simulation
3 / 17
Outline Introduction Design toolchain Basic Elements Demo - FFT calculation Summary
Hardware co-simulation
Incorporate hardware intoSimulink design
Speed up simulation withhardware in the loop
Automatic data exchange
Supports Xilinx FPGA chipswith JTAG programming
4 / 17
Outline Introduction Design toolchain Basic Elements Demo - FFT calculation Summary
Toolchain
Required software
Matlab
7.4.0.287(R2007a)
Matlab Simulink
6.6(R2007a)
ISE Design Suite
v10.1.03
EDK
v10.1.03
System Generator
10.1.3.1386
Sensitive to version changes
One System Generatorsupports only two Matlabversions
Xilinx ISE v10.1 is the lastone supporting Virtex IIchips
Additional software: MentorModelsim
5 / 17
Outline Introduction Design toolchain Basic Elements Demo - FFT calculation Summary
Toolchain
Required software
Matlab 7.4.0.287(R2007a)
Matlab Simulink 6.6(R2007a)
ISE Design Suitev10.1.03
EDK v10.1.03
System Generator10.1.3.1386
Sensitive to version changes
One System Generatorsupports only two Matlabversions
Xilinx ISE v10.1 is the lastone supporting Virtex IIchips
Additional software: MentorModelsim
5 / 17
Outline Introduction Design toolchain Basic Elements Demo - FFT calculation Summary
Outline
1 Introduction
2 Design toolchain
3 Basic Elements
4 Demo - FFT calculation
5 Summary
6 / 17
Outline Introduction Design toolchain Basic Elements Demo - FFT calculation Summary
Simple example
System Generator
Input/Output Gateway
Xilinx blocks
Any Simulink blocks
Gateways are Top-leveloutput in compilation results
Between gateways there areonly Xilinx blocks
Outside gateways can be allother blocks
7 / 17
Outline Introduction Design toolchain Basic Elements Demo - FFT calculation Summary
System Generator
Most important block
Must be at Top-level inevery Simulink model
Allows compilation of thedesign
8 / 17
Outline Introduction Design toolchain Basic Elements Demo - FFT calculation Summary
System Generator compilation targets
HDL Netlist
VHDLVerilog
Bitstream
Hardware co-simulationJTAG
FPGAprogrammingData exchange
Ethernet
Data exchangePoint-to-pointNetwork based
9 / 17
Outline Introduction Design toolchain Basic Elements Demo - FFT calculation Summary
Gateways
Name is transferredto the generated IP
Fixed binary pointarithmetic
Important to setOutput data type
number of bitsbinary point
10 / 17
Outline Introduction Design toolchain Basic Elements Demo - FFT calculation Summary
Basic elements
11 / 17
Outline Introduction Design toolchain Basic Elements Demo - FFT calculation Summary
Memory library
12 / 17
Outline Introduction Design toolchain Basic Elements Demo - FFT calculation Summary
Outline
1 Introduction
2 Design toolchain
3 Basic Elements
4 Demo - FFT calculation
5 Summary
13 / 17
Outline Introduction Design toolchain Basic Elements Demo - FFT calculation Summary
Simulink model
Signal generated in Simulink. Sum of 2 sine waves and noise
512point FFT
Delay block on done line
14 / 17
Outline Introduction Design toolchain Basic Elements Demo - FFT calculation Summary
Hardware-Software Co-Simulation
Simulink subsystem with Xilinx blocksCompiled Co-Simulation block
Automatic JTAG connectionFPGA configuration at simulation start
15 / 17
Outline Introduction Design toolchain Basic Elements Demo - FFT calculation Summary
Demo results
Calculated FFT
Done,synchronizationpulse
Original signal
16 / 17
Outline Introduction Design toolchain Basic Elements Demo - FFT calculation Summary
Summary
Simulink as FPGA design tool
Easy to use
No need of HDL knowledge
Multiple ready blocks
Hardware-Software Co-Simulation
Xilinx System Generator brings hardware into simulation
Problems
Sensitive to version changes
Complicated and long toolchain
17 / 17
Outline Introduction Design toolchain Basic Elements Demo - FFT calculation Summary
Xilinx FPGA design using Simulink with HardwareCo-Simulation
Miko laj Chwalisz(chwalisz@tkn.tu-berlin.de)
Technische Universitat BerlinTelecommunication Networks Group (TKN)
April 28, 2011
TKNTelecommunication
Networks Group
18 / 17