Design of Low-Voltage MOSFET-Only\u0026gt;tex\u0026lt;$SigmaDelta$\u0026gt;/tex\u0026lt;Modulators...

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96 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004

Design of Low-Voltage MOSFET-Only ��Modulators in Standard Digital CMOS TechnologyThomas Tille, Member, IEEE, Jens Sauerbrey, Manfred Mauthe, and Doris Schmitt-Landsiedel, Member, IEEE

Abstract—A design strategy of low-voltage high-linearityMOSFET-only �� modulators in standard digital CMOStechnology is presented. The modulators use substrate-biasedMOSFETs in the depletion region as capacitors, linearized bydifferent compensation techniques. This work shows the design,simulation and measured results of a number of MOSFET-only�� modulators using different implementations of so calledcompensated depletion-mode MOS capacitors. The modulatorsare designed for the demands of speech band applications. Theperformance of the modulators proves the capability of compen-sated depletion-mode MOS capacitors to fulfill analog circuitrequirements at low supply voltages with reduced processingefforts.

Index Terms—Analog-to-digital converters, CMOS analogintegrated circuits, depletion-mode, low-voltage, MOS capacitor,MOSCAP, MOSFET-only, �� modulators, switched-capacitor(SC) circuits.

I. INTRODUCTION

TO integrate the analog part of a mainly digital applicationon a single-chip with a standard digital CMOS process,

capacitors without the requirement of extra process layers aredesired. These capacitors should have a large capacitance perunit area and a high linearity. The combination of these prop-erties is given neither by standard interlayer capacitors nor byMOS capacitors. MOS capacitors using the gate-to-bulk capac-itance of a standard MOSFET feature a high capacitance perunit area but a strong voltage dependence. The strong voltagedependence caused by different charge distributions in the ac-cumulation, inversion, and depletion regions can be reduced bya series or parallel compensation technique achieving a high-lin-earity capacitor.

Series compensation and parallel compensation of MOScapacitors biased in the strong inversion or accumulationregion are described in [1]–[4]. In these works, a switchedhigh bias voltage is required to keep the MOS capacitors instrong inversion or accumulation. However, the required bias

Manuscript received January 15, 2003; revised September 26, 2003. Thispaper was recommended by Guest Editors A. Rodríguez-Vázquez, F. Mediero,and O. Feely.

T. Tille was with the Institute of Technical Electronics, Technical Univer-sity of Munich, D-80333 Munich, Germany. He is now with the ElectronicsDevelopment Department, BMW Group, D-80788 Munich, Germany (e-mail:Thomas.Tille@bmw.de).

J. Sauerbrey is with Corporate Research, CPR FEC, Infineon TechnologiesAG, D-81730 Munich, Germany (e-mail: Jens.Sauerbrey@infineon.com).

M. Mauthe is with Corporate Logic, CL DAT, Infineon Technologies AG,D-81609 Munich, Germany (e-mail: Manfred.Mauthe@infineon.com).

D. Schmitt-Landsiedel is with the Institute of Technical Electronics,Technical University of Munich, D-80333 Munich, Germany (e-mail:dsl@ei.tum.de).

Digital Object Identifier 10.1109/TCSI.2003.821296

Fig. 1. Principle diagram of a p-channel depletion-mode MOS capacitor.

voltage is too high for low-voltage applications and the need ofa switched bias restricts the use to switched-capacitor (SC) cir-cuits. Furthermore, the supply voltage limit in state-of-the-artCMOS processes is opposed to an operation in strong inversionor accumulation.

The use of series or parallel compensated MOS capacitorsoperated in the depletion region [5], [6] yields significantadvantages: the compensated structure is usable at low supplyvoltages, works without voltage-boosting techniques, and isnot limited to SC circuits. A substrate biasing produces adepletion region broadening of these depletion-mode MOScapacitors, which leads to an extension of the linear voltagerange of the total resulting capacitance. In Section II, ananalytical description of the compensation effect of series com-pensated depletion-mode MOS capacitors (SCDM-MOSCAPs)and parallel compensated depletion-mode MOS capacitors(PCDMS-MOSCAPs) are given, respectively. Furthermore,several circuit implementations are described and measuredcapacitance–voltage ( ) characteristics of SCDM- andPCDM-MOSCAPs realized in standard 0.25- m n-well digitalCMOS technology are discussed.

In Section III, a number of fully differential MOSFET-onlySC modulators using different compensated deple-tion-mode MOS capacitors are described. The propertiesof these modulators in particular concerning nonidealitiesof the capacitors are analyzed. The implementation of theMOSFET-only modulators in standard 0.25- m n-welldigital CMOS technology is described as well as simulatedand experimental results are presented. To evaluate the per-formance of these modulators, simulated and measured dataare compared with data of a reference modulator realizedwith the same architecture and on the same substrate but withstandard interlayer capacitors.

II. COMPENSATED DEPLETION-MODE MOS CAPACITORS

A. Characterization of Depletion-Mode

Fig. 1 shows the principle diagram of a p-channel deple-tion-mode MOS capacitor. To extend the usable voltage rangeof a depletion-mode MOS capacitor, a bias voltage isnecessary at the pn junction between shorted drain/source

TILLE et al.: DESIGN OF LOW-VOLTAGE MOSFET-ONLY MODULATORS 97

Fig. 2. Cross section of a p-channel depletion-mode MOS capacitor instandard digital n-well CMOS technology.

Fig. 3. Measured depletion region broadening of a p-channel MOS capacitorcaused by substrate biasing (0.25-�m CMOS, t = 5 nm, W = 40 �m, andL = 10 �m).

nodes and the bulk node of the MOSFET [5]. The usablecapacitance is available between nodes and . To realizea floating capacitor in standard n-well CMOS technology,a p-channel MOSFET embedded in a separate n-well waschosen. For this configuration, the shorted drain/source nodesrequire a negative potential related to the bulk node .

Fig. 2 depicts a cross section of a p-channel depletion-modeMOS capacitor in standard digital CMOS technology.

The substrate bias voltage causes a depletion regionbroadening. This effect is shown in the measured CV curvesof Fig. 3 for a MOS capacitor with different substrate biasvoltages. The depletion region broadening is caused by a shiftof the threshold voltage relative to the bulk potential. Theresulting gate-to-bulk voltage for is thesum of the substrate bias voltage and the shifted thresholdvoltage

The reason for the threshold voltage shift is thebody-effect. The value is the threshold voltage at a substratebias voltage of zero. Therefore, the threshold voltage shift de-pends on the body-effect coefficient , the substrate bias voltage

, and the bulk Fermi potential [7] as follows:

The body-effect coefficient depends on the substrate dopingconcentration , the gate-oxide thickness , and the gate

Fig. 4. Principle diagram of a p-channel SCDM-MOSCAP.

Fig. 5. Cross section of a p-channel SCDM-MOSCAP in standard digitaln-well CMOS technology.

area and determines the dependence of the threshold voltageon the substrate bias as

with (3)

The characteristics in the depletion region are givenby the gate-oxide capacitance in series with the depletioncapacitance so that the gate-to-bulk capacitancebecomes

Here is the thickness of the depletion layer, given by

From (5) follows the gate-to-bulk capacitance in depletion

where is the flatband voltage.Fig. 3 shows measured characteristics of depletion region

broadenings of a p-channel depletion-mode MOS capacitor instandard 0.25- m CMOS technology at different substrate biasvoltages from V to V related to analogground.

The resulting functions within the extended depletionregion of a MOS capacitor are the fundamental characteristicsfor compensated depletion-mode MOS capacitors.

B. Series Compensated Depletion-Mode MOS Capacitors

One promising way to reduce the nonlinearity of adepletion-mode MOS capacitor is the use of a series com-pensation technique [5]. Fig. 4 shows the principle diagramof a series compensated depletion-mode MOS capacitor(SCDM-MOSCAP). The series compensation is obtainedby connecting the gate nodes of two depletion-mode MOScapacitors and , and the usable capacitance is availablebetween the bulk nodes and . Fig. 5 depicts a cross sectionof the series compensation structure with two equally sizedp-channel MOS capacitors in separate n-wells.

The drain and source contacts of each of the p-channelMOSFETs and are shorted. The dc voltages and

are the substrate bias voltages between the drain/sourceand bulk nodes and , respectively. For this configuration,the shorted drain/source nodes require a negative potentialrelated to the bulk nodes. If MOS capacitors of equal area areused, the substrate bias voltages and should be ofthe same value for symmetry of the nonlinearity compensationeffect.

For the following theoretical description, it is assumed thatthe MOS capacitors and are equal and gate node isnot charged. Hence, the potential at node is in the middlebetween the potential of nodes , and , respectively. Then, thetotal resulting capacitance of a SCDM-MOSCAP, whichis the series capacitance of both capacitances and ,can be determined by

where and are the gate-to-bulk capacitancesof the MOS capacitors and with the correspondinggate-to-bulk voltages and .

Using (6), the total resulting capacitance per unit area of aseries compensated MOS capacitor in depletion is

The compensation effect of a p-channel SCDM-MOSCAPbased on (6) and (8) is illustrated in Fig. 6.

In Fig. 6, the composition of the total capacitanceout of the two nonlinear partial capacitances andis depicted for a representative operating point. The condition

is satisfied.

To describe the linearity of a MOS capacitor, we define thenonlinear residual voltage dependence (RVD) [6]. The param-eter RVD is the percentage difference between themaximum of the function in a specific voltage interval

relative to the minimum capacitance

RVD (9)

Fig. 6. Visualization of the theoretical compensation effect of a p-channelSCDM-MOSCAP and representative operating point.

Fig. 7. Test circuit for CV measurement of an SCDM-MOSCAP.

To model RVD , (8) is decomposed in a constantpart and a voltage-dependent correction termRVD

RVD (10)

Using (3), (8), and (10), the nonlinear residual voltage depen-dence RVD is given by (11), shown at the bottom ofthe page.

Measured characteristics of a p-channel SCDM-MOSCAP are obtained from a test circuit according to Fig. 7.The operation levels of the test circuit potentials are depictedin Fig. 8.

and are the potentials of the shorteddrain/source nodes of the MOS capacitors and ,respectively. The potential is the sum of the sinusoidaltest signal amplitude , the offset voltage , and thenegative substrate bias voltage . The potential isthe analog ground potential GNDA minus the substrate bias

Fig. 8. Signal operation levels of the test circuit.

Fig. 9. Measured CV characteristics of an SCDM-MOSCAP at differentsubstrate bias voltages (0.25 �m-CMOS, t = 5 nm, W = W = 20 �m,and L = L = 20 �m).

voltage . GNDA is relative to the ground potential. The common-mode voltage level is given by

via voltage divider .Fig. 9 shows a plot of an SCDM-MOSCAP realized in

standard 0.25- m n-well CMOS technology. It can be seen thata large constant capacitance range is obtained already for smallsubstrate bias voltages , e.g., a voltage range of 1.5 V isachieved with a of only 0.5 V. This demonstrates the us-ability of the presented capacitors in circuits with low supplyvoltages.

Hence, for the considered standard 0.25- m digital CMOStechnology with an oxide thickness of 5 nm, the capacitance perunit area is approximately 0.4 fF m .

The nonlinear residual voltage dependence RVDof an SCDM-MOSCAP in a specific voltage interval of

0.5 V at a substrate bias voltage of 0.5 Vis less than 0.1%. The measured residual voltage dependence isshown in Fig. 10.

Fig. 9 also shows that the linearization with different substratebias voltages results in approximately equal specific capacitancevalues with different usable voltage ranges. This is an agreementwith the analytical result of (8). This permits a modification ofthe circuit diagram shown in Fig. 4 into an arrangement withoutfloating dc voltage sources (Fig. 11).

In the circuit implementation of Fig. 11 the shorted drainand source nodes of both MOSFETs and are connectedto each other and then this node is biased negative relative toGNDA. Note that the bias voltage must not become larger than

Fig. 10. Measured residual voltage dependence of an SCDM-MOSCAPwith a substrate bias voltage of V = V = �0.5 V (0.25 �m-CMOS,t =5 nm, W = W = 20 �m, and L = L = 20 �m).

Fig. 11. SCDM-MOSCAP with fixed substrate bias and high-resistanceelement.

the bulk voltages because otherwise the pn junctions betweendrain/source and n-well of the MOSFETs and turn on.The best way to prevent this is to connect the shorted drain andsource nodes to which also simplifies the realization. Torealize a high-resistance element on gate node to prevent agate charging, it is possible to use, e.g. an n-channel MOSFET

, operated in the subthreshold region. Its resistance valuemay vary in a wide range but must be high enough not to deteri-orate the modulator performance. To avoid significant parasiticcapacitances, the area of the MOSFET should be small rel-ative to the areas of the MOSFETs and .

Fig. 12 shows the measured residual voltage dependence ofan SCDM-MOSCAP with fixed substrate bias and high-resis-tance element according to Fig. 11 realized in standard 0.25- mn-well CMOS technology.

The nonlinear residual voltage dependence RVDin a specific voltage interval of 0.5 V with fixed sub-strate bias is again less than 0.1%.

C. Parallel Compensated Depletion-Mode MOS Capacitors

Another way to reduce the nonlinearity of a depletion-modeMOS capacitor is the use of a parallel compensation technique[6]. Fig. 13 shows the principle diagram of a parallel com-pensated depletion-mode MOS capacitor (PCDM-MOSCAP).The parallel compensation is obtained by connecting twodepletion-mode MOS capacitors in antiparallel.

The substrate bias voltages and between shorteddrain/source nodes and the bulk node realize the depletion re-gion broadening of the depletion-mode MOS capacitors and

Fig. 12. Measured residual voltage dependence of an SCDM-MOSCAP withfixed substrate biasV = V and high-resistance element (0.25-�m CMOS,t = 5 nm, W = W = 20 �m, and L = L = 20 �m).

Fig. 13. Principle diagram of a p-channel PCDM-MOSCAP.

Fig. 14. Cross section of a p-channel PCDM-MOSCAP in standard digitaln-well CMOS technology.

, respectively. The total resulting capacitance of the PCDM-MOSCAP is available between the nodes and . Fig. 14depicts a cross section of the parallel compensation structurewith two equally sized p-channel MOS capacitors in separaten-wells.

The compensation effect of a PCDM-MOSCAP is basedon the sum of the nonlinear voltage dependent capacitances

and of the MOS capacitors and, respectively. The total resulting capacitance of a

PCDM-MOSCAP can be determined by

Fig. 15. Visualization of the theoretical compensation effect of a p-channelPCDM-MOSCAP.

Fig. 16. Test circuit for CV measurement of a PCDM-MOSCAP.

Using (6), the total resulting capacitance per unit area of aPCDM-MOSCAP is

with .The compensation effect of a p-channel PCDM-MOSCAP

based on (6) and (13) is illustrated in Fig. 15.By separating (13) in a constant part and a

voltage dependent correction term RVDwe can determine the nonlinear residual voltage depen-dence RVD of a PCDM-MOSCAP in analogy toSection II-B

RVD (14)

Using (3), (13) and (14), the nonlinear residual voltage de-pendence RVD is expressed by (15), shown at thebottom of the following page.

Measured characteristics of a PCDM-MOSCAP are ob-tained from a test circuit according to Fig. 16. The signal oper-ation levels of the test circuit are depicted in Fig. 17.

Fig. 17. Signal operation levels of the test circuit.

Fig. 18. Measured CV plot of a PCDM-MOSCAP with different substratebias voltages (0.25-�m CMOS, t = 5 nm, W = W = 20 �m, and L =

L = 20 �m).

and are the potentials of the shorteddrain/source nodes of the MOS capacitors and ,respectively. The potential is the sum of the test signalamplitude , the offset voltage and the negative substratebias voltage . The potential is the GNDA potentialminus the substrate bias voltage .

Fig. 18 shows the plot of a PCDM-MOSCAP realizedin standard 0.25- m n-well CMOS technology at different sub-strate bias voltages .

Hence, for the considered technology with an oxide thick-ness of 5 nm the capacitance per unit area is approximately

fF m . This is four times larger than the capacitance ofan SCDM-MOSCAP in the same technology.

The nonlinear residual voltage dependence RVDin a specific voltage interval of V at a substratebias voltage of V is less than 6%. Thecorresponding characteristic is shown in Fig. 19.

Fig. 18 also shows that the linearization with different floatingsubstrate bias voltages results in approximately equal specific

Fig. 19. Measured residual voltage dependence of a PCDM-MOSCAP with asubstrate bias voltage of V = V = �0:5 V (0.25-�m CMOS, t =

5 nm, W = W = 20 �m, and L = L = 20 �m).

Fig. 20. PCDM-MOSCAP with fixed substrate bias.

capacitance values with different usable voltage ranges. Thispermits a modification of the circuit shown in Fig. 13 intoan arrangement without floating dc voltage sources. Fig. 20shows the circuit implementation with fixed substrate bias

. The shorted drain and source nodesof both MOSFETs and are connected to each otherand then this node is biased negative relative to GNDA. Thisnegative bias potential is , preventing the pn junctionsbetween drain/source and n-well of the MOSFETs andfrom being switched on.

Fig. 21 shows the measured RVD of a realized PCDM-MOSCAP with fixed substrate bias according to Fig. 20.

The nonlinear residual voltage dependence RVDof a PCDM-MOSCAP in a specific voltage interval of

0.5 V with fixed substrate bias is less than6%.

In comparison to a standard poly1-metal1 interlayer capacitorin 0.25- m digital CMOS technology with a capacitance perunit area of 0.1 fF m an SCDM-MOSCAP realized in the

Fig. 21. Measured residual voltage dependence of a PCDM-MOSCAP withfixed substrate bias V = V (0.25-�m CMOS, t = 5 nm,W =W =

20 �m, and L = L = 20 �m).

Fig. 22. Second-order single-loop��modulator architecture with coefficientvalues of a = 1=5, a = 5=8, b = 1=5, and b = 1=4.

same technology has a four times higher capacitance. A PCDM-MOSCAP has an even 16 times higher specific capacitance thanthe standard interlayer capacitor.

III. MOSFET-ONLY MODULATORS

A. Modulator Architecture

Different MOSFET-only modulators are realized usingcompensated depletion-mode MOS capacitors. A conventionalsecond-order single-loop modulator architecture waschosen for these applications. The modulator architecture isshown in Fig. 22.

The coefficients of this architecture are realized by compen-sated depletion-mode MOS capacitors.

B. SC Realization

Fig. 23 shows the circuit diagram of the implemented second-order single-loop MOSFET-only modulators in a fully dif-ferential SC design.

C. Nonlinear Capacitor Effects in SC Modulators

To characterize the influence of capacitor nonidealities in SCmodulators, the dependence of the modulator signal-to-

noise-plus-distortion ratio (SNDR) on the nonlinear RVD ofthe MOS capacitors is relevant. Therefore, a simple simula-tion model to reproduce and vary the residual voltage depen-dence of a compensated depletion-mode MOS capacitor wasused (Fig. 24). This model was used for SPICE circuit simu-lations of modulators, where the remaining modulator elements

are idealized blocks to point out the influence of only the ca-pacitor nonlinearities to the modulator behavior. All other cir-cuit simulations (cf. -indicated values in Table II) are done withstandard BSIM3v3 transistor models (incl. compensated deple-tion-mode MOS capacitors).

To build a variable admittance between the terminalsand , a SPICE variable admittance block (YX) [8] , a ref-erence capacitor , and a lookup table (LUT) is used. TheLUT contains measured voltage-dependent capacitance valuesof a compensated depletion-mode MOS capacitor. The simula-tion model makes it possible to vary the residual voltage depen-dence based on a realistic characteristic by multiplying itwith a specific factor. The dependence of the modulator SNDRon the capacitor residual voltage dependence is investigated fora modulator circuit according to Fig. 23 with use of the simula-tion model in Fig. 24 for all capacitors – .

The level of the third-order harmonic component of the mod-ulator output spectrum is affected by the value of the residualvoltage dependence of the used capacitors. Fig. 25 shows thiscorrelation for exaggerated nonlinear residual voltage depen-dencies of the MOS capacitors at a constant input level of 6 dBreferred to the reference voltage at an oversampling ratio (OSR)of 64. Here, for all capacitors of the modulator the same non-linear residual voltage dependence is used.

Fig. 26 illustrates the dependence of the amplitude of thethird-order harmonic component on the RVD. In this case,e.g., for an RVD V of 1%, the amplitude of thethird-order harmonic component increases by about 4 dB. If theresidual voltage dependence RVD V is less than0.5%, no significant SNDR loss of the modulator at an OSR of64 is noticeable. In the case of using SCDM-MOSCAPs whichhave a residual voltage dependence RVD V ofless than 0.1%, the third-order harmonic component is wellbelow the thermal noise and no SNDR loss is to be expected.

At higher oversampling ratios, the dependence of the mod-ulator SNDR on the capacitors’ RVD increases. Fig. 27 de-picts this influence for oversampling ratios of 16–256 at non-linear residual voltage dependencies RVD V of0%–20% at constant modulator input amplitudes of 6 dB.

To evaluate the dependence of the modulator SNDR on theresidual voltage dependence of the depletion-mode MOS ca-pacitors in different locations of the circuit, a simulation wasperformed with exaggerated RVDs. Fig. 28 illustrates this de-pendence for each capacitor in the second-order fully differen-tial modulator structure (Fig. 23) at an OSR of 64. Withthe exception of the indicated capacitors all modulator elementsare idealized. Fig. 28 shows the relatively large influence of theswitching capacitors of the first integrator stage and onthe modulator SNDR with an increasing RVD. The dependenceof the SNDR on the RVD of all other capacitors is very small.

If the RVD in a specific voltage interval of Vof the first switching capacitors is less than approximately 0.5%and that of all others is less than approximately 5%, no seriousSNDR limitation occurs.

D. Building Blocks

Standard single-stage fully differential folded-cascodeoperational amplifiers and are used to create the

Fig. 23. Principle diagram of an SC �� modulator using depletion-mode MOS capacitors.

Fig. 24. Simple simulation model to reproduce and vary capacitornonlinearity.

Fig. 25. Simulated output spectra (OSR = 64) with different exaggeratednonlinear residual voltage dependencies RVD(V = �0.5 V) of the MOScapacitors.

SC integrators. The amplifiers are optimized regarding toslew-rate, gain, gain-bandwidth-product and dynamic range.The comparator is a fully-differential latch with pull-up andcross transistors. The switches consist of complementaryn-channel and p-channel MOSFETs with minimum channellength of 0.25 m. The ON-resistance of the switches

Fig. 26. Dependence of the amplitude of the third-order harmonic componenton the nonlinear residual voltage dependence RVD(V = �0:5V) at OSR =64 and f = f =OSR=8.

Fig. 27. Dependence of the peak SNDR on the OSR for different nonlinearresidual voltage dependences RVD(V = �0:5 V).

Fig. 28. Dependence of the peak SNDR on the OSR at different nonlinearresidual voltage dependences RVD(V = �0:5 V).

Fig. 29. Four-phase clocking scheme.

is less than k at V. To minimize the seriesresistance in the signal path the time constantis much smaller than . That guarantees a complete chargeand discharge operation of the SC branches. The circuits areconventionally clocked with a four-phase clocking schemeaccording to Fig. 29.

In Fig. 29, and are the nonoverlapping clock phasesand and are delayed by relative to and . Theclock generator is realized in static CMOS logic controlled byan external master clock.

The reference voltages for the 1-b D/A conversionare V and V (relative to

). Hence, the 0-dB level of the modulatorinput corresponds to a - sinusoidal signal.

The capacitor values are chosen in consideration of thethermal noise. Therefore, the minimum size of the samplingcapacitors and are defined. Hence, the size of thesecapacitors is determined as fF. The capac-itors in the integrator feedback loops have a size of 1 pF. Allother capacitor values result from the coefficient ratio of themodulator architecture (Fig. 22) scheduled in Table I.

TABLE ICAPACITOR VALUES

Fig. 30. Fully differential MOSFET-only SC �� modulator using SCDM-MOSCAPs only.

Fig. 31. Chip microphotograph of a manufactured MOSFET-only ��modulator using SCDM-MOSCAPs only.

E. MOSFET-Only Implementation WithSCDM-MOSCAPs Only

Fig. 30 shows the simplified circuit of the first implementa-tion of a MOSFET-only modulator in a fully differential SCdesign using SCDM-MOSCAPs.

To obtain an optimum linearity all capacitors are realized con-sistently by SCDM-MOSCAPs according to the circuit diagramshown in Fig. 11.

All MOSFET-only modulators are designed and imple-mented in standard 0.25- m digital n-well CMOS technologywith an oxide thickness of 5 nm and without extra layers for ca-pacitors. One poly and three metal layers are used.

The core area of the MOSFET-only modulator version withSCDM-MOSCAPs only is approximately mm . A chip mi-crophotograph is shown in Fig. 31.

In order to illustrate the SNDR of the realized MOSFET-onlymodulator, the output spectrum of a 65 536-samples bit-

stream (Blackman windowed) is captured. The input is a low-distortion differential sinusoidal signal with a frequency of2 kHz balanced to the analog ground. Fig. 32 shows the outputspectrum of the modulator with a bandwidth of 8 kHz and anOSR of 64 at a sampling frequency of 1.024 MHz.

With an input level of 12 dB, the third-order harmonic com-ponent is below the noise floor as can be seen in the basebandillustration (Fig. 33).

Fig. 32. Measured output spectrum (full spectrum) of a MOSFET-only ��modulator with SCDM-MOSCAPs only (OSR = 64, f = 1:024 MHz,f = 2 kHz).

Fig. 33. Baseband of the measured output spectrum of a MOSFET-only�� modulator using SCDM-MOSCAPs only (0.25-�m CMOS, OSR = 64,f = 1:024 MHz, f = 2 kHz).

The achieved signal-to-noise ration (SNR) and SNDR versusinput signal amplitude are shown in Fig. 34. There, the ampli-tude of the input signal is stepped down from 2 to 80 dB. Apeak SNDR of 72 dB at a 12-dB input level and a peak SNRof 77 dB at a 6-dB input level (corresponding with the theo-retical value) are achieved.

To demonstrate the high linearity of series compensated de-pletion-mode MOS capacitors with a higher oversampling ratio,Fig. 34 also illustrates the SNDR and SNR of the modulator at anOSR of 128. The input is a low-distortion differential sinusoidalsignal with a frequency of 1 kHz and the sampling frequency is1.024 MHz, so that we have a bandwidth of 4 kHz. We achievea peak SNDR of 80 dB at an input level of 10 dB and a peakSNR of 85 dB at an input level of 6 dB.

A reference modulator with standard poly1-metal1capacitors fF m , implemented on the samechip, has the same performance at OSR of 64 and 128 asthe MOSFET-only modulator with SCDM-MOSCAPs. Thatproves the high linearity of SCDM-MOSCAPs and fulfills theprediction of the assumption in Section III-C that no significantSNDR loss will be expected.

Fig. 34. Measured SNDR and SNR versus input level of a MOSFET-only��modulator using SCDM-MOSCAPs only, at oversampling ratios of 64 and 128.

Fig. 35. Fully differential MOSFET-only SC �� modulator using PCDM-MOSCAPs only.

Fig. 36. Chip microphotograph of a manufactured MOSFET-only ��

modulator using PCDM-MOSCAPs only.

All investigated MOSFET-only modulators operate withsupply voltages ranging from 1.8 to 2.5 V and consume approx-imately 1 mW at 1.8-V power supply.

F. MOSFET-Only Implementation With PCDM-MOSCAPsOnly

A second implementation uses PCDM-MOSCAPs ex-clusively (Fig. 35). The large capacitance per unit area ofPCDM-MOSCAPs provides the highest area efficiency of themodulator.

The core area of the manufactured circuit shown in Fig. 36has a size of approximately mm .

Fig. 37 shows the baseband of the modulator output spectrumwith a bandwidth of 8 kHz and an OSR of 64 at a 1.024-MHz

Fig. 37. Baseband of the measured output spectrum of a MOSFET-only�� modulator using PCDM-MOSCAPs only (0.25-�m CMOS, OSR = 64,f = 1:024 MHz, f = 2 kHz).

Fig. 38. Measured SNDR and SNR versus input level of a MOSFET-only��modulator using PCDM-MOSCAPs only, at oversampling ratios of 64 and 128.

sampling frequency and at an input frequency of 2 kHz. As canbe seen, at an input level of 20 dB, the third-order harmoniccomponent is below the noise floor.

The achieved SNR and SNDR versus input signal amplitudeare shown in Fig. 38. A peak SNDR of 66 dB at a 20-dBinput level and a peak SNR of 76 dB at a 6-dB input level(corresponding with the theoretical value) are achieved.

Additionally, Fig. 38 includes the SNR and SNDR of themodulator at an OSR of 128 at an input frequency of 1 kHzand a sampling frequency of 1.024 MHz (bandwidth 4 kHz).We achieve a peak SNDR of 72 dB at an input level of 20 dBand a peak SNR of 84 dB at an input level of 6 dB.

G. Hybrid MOSFET-Only Implementation With SCDM-and PCDM-MOSCAPs

To combine the advantages of SCDM- and PCDM-MOSCAPs, in Fig. 39 the sampling-capacitors of the first inte-grator stage are realized by high-linearity SCDM-MOSCAPsand all other capacitors by area-efficient PCDM-MOSCAPs[5]. The reason for this combination is that nonlinearity ofthe sampling-capacitor of the first integrator stage has a much

Fig. 39. Fully differential MOSFET-only SC �� modulator using SCDM-and PCDM-MOSCAPs.

Fig. 40. Chip microphotograph of a MOSFET-only �� modulator usingSCDM- and PCDM-MOSCAPs.

Fig. 41. Baseband of the measured output spectrum of a MOSFET-only ��modulator using SCDM- and PCDM-MOSCAPs (0.25-�m CMOS, OSR = 64,f = 1:024 MHz, f = 2 kHz).

Fig. 42. Measured SNDR and SNR versus input level of a MOSFET-only��modulator using SCDM- and PCDM-MOSCAPs at oversampling ratios of 64and 128.

TABLE IIMEASURED MODULATOR PERFORMANCE

Fig. 43. Chip microphotographs of different MOSFET-only�� modulators (�� ,�� , and�� ) by comparison to a reference��modulator (�� )using standard interlayer capacitors (technology: standard 0.25-�m CMOS).

larger influence on the modulator SNDR than that of all othercapacitors according to Fig. 28.

The manufactured circuit has a core area of approximatelymm . A chip microphotograph is depicted in Fig. 40.

Fig. 41 shows the baseband of the modulator output spectrumwith a bandwidth of 8 kHz and an OSR of 64 at a 1.024-MHzsampling frequency and at an input frequency of 2 kHz. Withan input level of 12 dB, the third-order harmonic componentis below the noise floor.

The achieved SNR and SNDR versus input signal amplitudeare shown in Fig. 42. A peak SNDR of 71 dB at a 12-dBinput level and a peak SNR of 77 dB at a 6-dB input level areobtained. Additionally, Fig. 42 includes the SNR and SDNR ofthe modulator at an OSR of 128 at an input frequency of 1 kHzand a sampling frequency of 1.024 MHz (bandwidth 4 kHz). Weachieve a peak SNDR of 78 dB at an input level of 10 dB anda peak SNR of 85 dB at an input level of 6 dB.

H. Comparison of MOSFET-Only Modulators With aReference Modulator

Measured and simulated data of all investigatedMOSFET-only modulators compared to data of a

reference modulator using standard poly1-metal1 inter-layer capacitors are summarized in Table II.

Fig. 43 shows a comparison of the core areas of themodulators.

The area consumption of MOSFET-only modulatorsusing different compensated depletion-mode MOS capacitorsin comparison to a reference modulator withstandard poly1-metal1 capacitors is illustrated in Fig. 44 (atOSR ) and Fig. 45 (at OSR ). All modulatorshave the same architecture, coefficients, and capacitor values,respectively.

The MOSFET-only modulator using SCDM-MOSCAPsonly has an area reduction of 43% compared to the ref-erence modulator design with standard poly1-metal1 ca-pacitors. Thereby, no noticeable decrease of SNDR occurs. TheMOSFET-only modulator using PCDM-MOSCAPs only

achieves an area reduction of 68% at a loss on SNDRof 7 dB at OSR and 8 dB at OSR , respectively.Advantageously, the implementation needs no high-re-sistance element to prevent a gate charging. The hybrid ver-sion of the MOSFET-only modulator using SCDM- andPCDM-MOSCAPs has an area reduction of 57% com-pared to the reference modulator and an area reduction

Fig. 44. Measured peak SNR and peak SNDR at OSR = 64 versus modulatorarea.

Fig. 45. Measured peak SNR and peak SNDR at OSR = 128 versusmodulator area.

of 25% compared to the design . The loss of SNDR is2 dB at OSR and OSR , respectively.

All investigated MOSFET-only modulators feature nosignificant loss on SNR compared to the values of the referencemodulator.

IV. CONCLUSION

The design of low-voltage MOSFET-only modulatorsusing different implementations of compensated deple-tion-mode MOS capacitors was presented. Generally, we usedepletion-mode MOS capacitors, where a depletion regionbroadening causes an extension of the usable voltage range.We distinguish between series and parallel compensateddepletion-mode MOS capacitors. Series compensated deple-tion-mode MOS capacitors achieve high linearity at moderatecapacitance per unit area. Parallel compensated depletion-modeMOS capacitors have a high specific capacitance and mediumlinearity. Both capacitor types need no voltage-boosting, noswitched bias and no extra process layers for their operation.

Therefore, no limitation exists for decreasing supply voltagesin future technologies.

Low-voltage MOSFET-only modulators using compen-sated depletion-mode MOS capacitors were described, exem-plarily, for the demands of speech band applications. The im-pact of compensated depletion-mode MOS capacitors used inthese modulators was analyzed with respect to the dependenceof the SNDR on the RVD and capacitor location. This permitsa specific use of compensated depletion-mode MOS capaci-tors in MOSFET-only modulators. Three implementationprinciples are discussed: using SCDM-MOSCAPs only, usingPCDM-MOSCAPs only, and a hybrid design using SCDM- andPCDM-MOSCAPs. All modulators achieve a high peak SNRand SNDR, working at low supply voltages and low area con-sumption. The measured performance of these modulators wascompared to that of a reference modulator using standard inter-layer capacitors.

The design strategy given in this work shows the possibilityand advantages on realizing modulators using compen-sated depletion-mode MOS capacitors. This approach makes itpossible to realize high-accuracy low-voltage analog circuits instandard digital CMOS technology.

REFERENCES

[1] H. Yoshizawa and G. C. Temes, “High-linearity switched-capacitor cir-cuits in digital CMOS technology,” in Proc. IEEE Int. Symp. Circuitsand Systems, Seattle, WA, 1995, pp. 1029–1032.

[2] H. Yoshizawa, Y. Huang, P. F. Ferguson Jr., and G. C. Temes,“MOSFET-only switched-capacitor circuits in digital CMOS tech-nology,” IEEE J. Solid-State Circuits, vol. 34, pp. 734–747, June 1999.

[3] H. Yoshizawa, G. C. Temes, P. Ferguson Jr., and F. Krumenacher, “Noveldesign techniques for high-linearity MOSFET-only switched-capacitorcircuits,” in IEEE Symp. VLSI Circuits, 1996, pp. 152–153.

[4] R. Kainer, “Circuit Arrangement for Reducing the Voltage Dependenceof a MOS Capacitor,” Eur. Patent EP 0720238, Mar. 7, 1996.

[5] T. Tille, J. Sauerbrey, and D. Schmitt-Landsiedel, “A 1.8-VMOSFET-only �� modulator using substrate biased depletion-modeMOS capacitors in series compensation,” IEEE J. Solid-State Circuits,vol. 36, pp. 1041–1047, July 2001.

[6] , “A low-voltage MOSFET-only �� modulator for speech bandapplications using depletion-mode MOS capacitors in combined seriesand parallel compensation,” in Proc. IEEE Int. Symp. Circuits and Sys-tems, vol. 1, Sydney, Australia, May 2001, pp. I376–I379.

[7] N. Arora, MOSFET Models for VLSI Circuit Simulation. New York:Springer-Verlag, 1993.

[8] OrCAD Pspice A/D. User’s Guide, OrCAD Inc., 1998.

Thomas Tille (M’01) was born in Berlin, Germany,in 1971. He received the Dipl.-Ing. degree inelectrical engineering from the Technical Universityof Berlin, Berlin, Germany, in 1995 and the Dr.-Ing.degree in electrical engineering from the TechnicalUniversity of Munich, Munich, Germany, in 2001.

In 1997, he joined the Institute of Technical Elec-tronics at the Technical University of Munich as a Re-search and Teaching Assistant and worked in a coop-erative program with the Research and DevelopmentDepartment of Siemens AG and the Corporate Re-

search Centre of Infineon Technologies AG. There he was engaged in analogCMOS circuit design for low-voltage AD converters. Since 2002, he has beenwith the Electronics Development Department, BMW Group, Munich, wherehe is managing projects in the field of automotive electronics and sensor sys-tems. His research interests are in the area of analog integrated CMOS circuits,sensor technology, and physics of semiconductor devices.

Jens Sauerbrey was born in Arnstadt, Germany,in 1966. He received the Dipl.-Ing. degree inelectrical engineering from the Technical Universityof Ilmenau, Ilmenau, Germany, and the Dr. Ing.degree in electical enginnering from theTechnicalUniversity of Munich, Munich, Germany in 1994,and 2003, respectively.

He joined the Research and Development Labo-ratories at Siemens AG, Munich, Germany, wherehe was involved in circuit design for data converters.Since 1999, he has been with the Corporate Research

Center of Infineon Technologies AG, Munich, where he concentrates on analogcircuit design for very-low-supply voltages.

Manfred Mauthe was born in Reutlingen, Germany,in 1948. He received the Dipl.-Ing. degree in elec-trical engineering from the Technical University ofStuttgart, Stuttgart, Germany, in 1974.

He joined the Corporate Research Group ofSiemens AG, Munich, Germany, in 1974, where heworked in the area of CCDs. Later, he was engagedin analog CMOS circuit design for hearing aids andsensor interface circuits. In 1999, he joined InfineonTechnologies AG, Munich, where he was engagedin developing �� analog-to-digital converters and

high-speed CMOS circuits. From 2000 to 2002, he was with the RF CMOSGroup of the Wireless Solutions Department of Infineon Technologies AG,Munich. Currently, he is with the Corporate Logic Department and is involvedin the design of high-speed macros. His field of interest is the design of analogintegrated CMOS circuits.

Doris Schmitt-Landsiedel (M’80) received theDipl.-Ing. degree in electrical engineering fromthe Technical University of Karlsruhe, Karlsruhe,Germany, the diploma in physics from the Universityof Freiburg, Freiburg, Germany, and the Dr. rer. nat.degree from the Technical University of Munich,Munich, Germany.

Following some research projects on semicon-ductor lasers and nonlinear optics, she joined theCorporate Research and Development Departmentof Siemens AG, Munich, in 1981. There she worked

on scaling properties of MOS devices and on the design of high-speed logicand SRAM circuits. Since 1989, she has been section manager of a group ofprojects in future generation memory design, analog and digital CMOS andBICMOS circuits, and design-based yield analysis. Since 1996, she has been aProfessor of Electrical Engineering and Director of the Institute for TechnicalElectronics at the Technical University of Munich. Her research interests arein mixed signal and low-power circuit design, failure analysis, design formanufacturability, and sensors on silicon.

Design of Low-Voltage MOSFET-Only\u0026gt;tex\u0026lt;$SigmaDelta$\u0026gt;/tex\u0026lt;Modulators...

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