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© 2003 Xilinx, Inc. All Rights Reserved
Reading Reports
Xilinx:
This module was completely redone. Please translate entire module
Some pages are the same. They are noted in the module
Xilinx:
This module was completely redone. Please translate entire module
Some pages are the same. They are noted in the module
FPGA Design Flow Workshop
Reading Reports 6 - 2 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Objectives
After completing this module, you will be able to:• Determine whether a design met your area goals• Determine whether a design met your performance goals
Xilinx:
all new bullets
Xilinx:
all new bullets
Reading Reports 6 - 3 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Outline
• Introduction• Area Goals• Performance Goals• Summary
Reading Reports 6 - 4 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Introduction
• After you have implemented your design, how can you tell whether the implementation was successful?
• First and foremost, how do you define a successful design?
• Answer: A successful design means the design...– Fits into the device– Achieves performance goals
Reading Reports 6 - 5 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Outline
• Introduction• Area Goals• Performance Goals• Summary
Reading Reports 6 - 6 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Area Goals
• How do we know if the design fits into the device?
• How do we know if there is room in the device for more logic? If there is, exactly how much space is available?
• If the design fits into the device, was it able to route completely?
Reading Reports 6 - 7 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Area Goals
• How do we know if the design fits into the device?– Information can be found in the Map Report or the Place & Route Report
• How do we know if there is room in the device for more logic? If there is, exactly how much space is available?
– Information can be found in the Map Report or the Place & Route Report
• If the design fits into the device, was it able to route completely?– Information can be found in the Place & Route Report
Reading Reports 6 - 8 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Map Report
• Map Report contents– Command line options for the map program– Design summary
• List of how many device resources are used– Errors and warnings– Removed logic summary
• List of logic that was removed due to sourceless or loadless nets– IOB properties
• Indicates whether an I/O flip-flop is used• List of attributes on each I/O pin
Xilinx:
Same as v4 slide 6-10
Removed last bullet about Post-map Static Timing Report
Xilinx:
Same as v4 slide 6-10
Removed last bullet about Post-map Static Timing Report
Reading Reports 6 - 9 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Map Report
• Map Report– <design>.mrp
• It is useful to review this report before proceeding to Place & Route
– Especially for large or high-speed designs
– Ensure device has enough resources
Reading Reports 6 - 10 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Map Report Questions
Open the Map Report from the Tool Flow lab
• How many slices were used?
• How many IOBs were used?
• Were there any errors, warnings, or informational messages?
Xilinx:
Same as v4 slide 6-11
Xilinx:
Same as v4 slide 6-11
Reading Reports 6 - 11 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Answers
• How many slices were used (Number of occupied Slices)?– Virtex-II
• 162 (VHDL)• 75 (Verilog)
– Spartan-3• 164 (VHDL)• 75 (Verilog)
• How many IOBs were used?– 17 (same for all versions)
• Were there any errors, warnings, or informational messages?– Three informational messages (same for all versions)
Reading Reports 6 - 12 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Place & Route Report
• Place & Route Report contents – Command line options for the PAR program– Errors and warnings– Device utilization summary
• Similar to the Design Summary from the Map Report– Unrouted nets– Timing summary
• Statistics on average routing delays• Performance versus constraints if the design contains timing constraints
Xilinx:
same as v4 slide 6-17
Xilinx:
same as v4 slide 6-17
Reading Reports 6 - 13 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Place & Route Report
• Place & Route Report– <design>.par
Reading Reports 6 - 14 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Place & Route Report Questions
Open the Place & Route Report from the Tool Flow lab
• Does the Device Utilization Summary agree with the Map Report?
• Are there any unrouted signals?
Reading Reports 6 - 15 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Answers
• Does the Device Utilization Summary agree with the Map Report?– Yes
• Are there any unrouted signals?– No
Reading Reports 6 - 16 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Outline
• Introduction• Area Goals• Performance Goals• Summary
Reading Reports 6 - 17 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
CommunicatingPerformance Goals
• Where would you look to find reasonable values for your timing constraints?
• Answer: Post-Map Static Timing Report
Reading Reports 6 - 18 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Post-Map Static Timing Report
• The Post-Map Static Timing Report indicates whether your constraints are reasonable
– Contains actual block delays and 0.1 ns net delays• What is reasonable? Use the 60/40 rule:
– If less than 60 percent of the timing budget is used for logic delays, the Place & Route tools should be able to meet the constraint easily
– Between 60 to 80 percent, software run time will increase– Greater than 80 percent, the tools may have trouble meeting your goals
Xilinx:
similar to v4 slide 6-30
Note: values in sub-bullets are
changed
Xilinx:
similar to v4 slide 6-30
Note: values in sub-bullets are
changed
Reading Reports 6 - 19 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Handling Unreasonable Constraints
• Re-evaluate the constraints: Is the design over-constrained?– Yes: Consider using advanced constraints– No: Redesign logic or pipeline to reduce the number of logic levels in long
paths
Xilinx:
same as v4 slide 6-31
Xilinx:
same as v4 slide 6-31
Reading Reports 6 - 20 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Timing Reports
• Post-Map Static Timing Report created during Map process
– <design>.twx– Not created by default– Double-click the process to
create this report– Double-click on the report to
view it in the Timing Analyzer
Reading Reports 6 - 21 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Timing Reports
• Timing Report contents (for designs with constraints)– Command line options for the trce program– Timing Constraints section
• Summary of each timing constraint (if you have any)• Details on paths that fail to meet constraints
– Data sheet section• Setup/hold, clock to pad, timing between clock domains, and pad-to-pad delay
information• Organized in easy-to-read table format
– Timing Summary section• Number of errors and Timing Score
Xilinx:
same as v4 slide 6-28
Xilinx:
same as v4 slide 6-28
Reading Reports 6 - 22 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Timing Reports
• Timing Reports can be viewed using the Timing Analyzer– Creating custom reports with the Timing Analyzer is covered in the
Designing for Performance course• Note: Timing Reports can be created for designs without constraints
– Xilinx, however, recommends using timing constraints to meet performance goals
Xilinx:
same as v4 slide 6-29
Xilinx:
same as v4 slide 6-29
Reading Reports 6 - 23 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Evaluating Performance Goals
• Now that you have entered constraints, how do you know if the constraints were met?
• Answer: Place & Route Report or Post-Place & Route Static Timing Report
Reading Reports 6 - 24 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Post-Place & Route Timing Report
• Post-Place & Route Static Timing Report
– <design>.twx– Created by default
Reading Reports 6 - 25 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Post-Place & Route Static Timing Report
• The Post-Place & Route Static Timing Report indicates whether your constraints were actually met
– Contains actual block delays and actual net delays calculated from Place & Route
– Used for static timing analysis after Place & Route
Xilinx:
same as v4 slide 6-32
Xilinx:
same as v4 slide 6-32
Reading Reports 6 - 26 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Timing Report Question
Open the Post-Place & Route Static Timing Report from the Tool Flow lab
• What is the minimum clock period for this design (clock to setup value for wr_clk_in)?
Reading Reports 6 - 27 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Answer
• What is the minimum clock period for this design (clock to setup value for wr_clk_in)?
– Virtex-II• 22.084 ns (VHDL)• 8.025 ns (Verilog)
– Spartan-3• 26.786 ns (VHDL)• 10.988 ns (Verilog)
• Notice there are no timing constraints in the design; otherwise, they would have been reported
Reading Reports 6 - 28 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Pinout Information
• Where can I get pinout information to start the board layout?
• Answer: Pad Report
Reading Reports 6 - 29 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Pad Report
• Plain text Pad Report– <design>_pad.txt– Viewed in the Project Navigator
window– Sorted by pin number only
• Pad Report– <design>.pad, <design>_pad.csv– This report must be viewed in a
spreadsheet tool• Delimiters: | (.pad) or comma (.csv)
– Allows data sorting by various fields• Pin number, signal name, I/O
standard, data flow direction, etc
Reading Reports 6 - 30 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Pad Report Questions
Open the Pad Report from the Tool Flow lab.
• What pin location was assigned to “reset”?
• What is on pin H8?
Reading Reports 6 - 31 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Answers
• What pin location was assigned to “reset”?– Virtex-II
• D9 (VHDL)• C12 (Verilog)
– Spartan-3• P16 (VHDL)• P11 (Verilog)
• What is on pin H8?– GND
Reading Reports 6 - 32 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Outline
• Introduction• Area Goals• Performance Goals• Summary
Reading Reports 6 - 34 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Review Questions
• How do you determine whether your timing constraints are reasonable? (Hint: which report do you review?)
• To estimate the amount of available resources you have left, do you need to fully implement your design? Why or why not?
Reading Reports 6 - 35 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Answers
• How do you determine whether your timing constraints are reasonable? (Hint: which report do you review?)
– Use the Post-Map Static Timing Report– You must double-click the Generate Post-Map Static Timing process to
create this report (it is not created by default)• This process is underneath the Map process
• To estimate the amount of available resources you have left, do you need to fully implement your design? Why or why not?
– No. You have to implement through the Translate and Map processes because the Design Summary in the Map Report shows you the available resources left in the device
Reading Reports 6 - 36 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only
Summary
• A successful implementation means that your design meets your area and performance objectives
• The Map and PAR Report provides resource utilization and availability
• The Post-Map Static Timing Report gives you information to create reasonable timing constraints
• The Post-Place & Route Static Timing Report informs you whether your timing constraints were met