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© Ministère de l'éducation nationale, de l'enseignement supérieur et de la recherche SEPTEMBRE 2005

4 6DUT GEII - Informatique des Systèmes Industriels

UEU E 2 3 Matière I n f o r m a t i q u e I n d u s t r i e l l e Volume horaire 1 2 C 2 0 T D 2 8 T PRéférence I I 2 ModuleA r c h i t e c t u r e d e s s y s t è m e sà p r o c e s s e u r s Positionnement S 2

Objectifs : $ Maîtriser l’implémentation des concepts de la programmation structurée et démystifier le langage de haut niveau (exemple : traduction C / Assembleur), $ Comprendre l’architecture d’un système à processeur, $ Comprendre les mécanismes d'interruption.

Compétences minimales : $ tre capable d’écrire un programme langage de haut niveau pour une cible à microprocesseur ou microcontrôleur, $ Savoir interfacer un périphérique, savoir gérer des entrées – sorties, $ tre capable d’évaluer les contraintes de temps dans le cas d’une application simple.

Pré-Requis : $ Module II1 Algorithmique, Programmation $ Module ENSL1 électronique numérique, synthèse logique

Contenu : $ Terminologie : micro-ordinateur, microprocesseur, micro-contrôleur, $ Organisation matérielle d’un micro-contrôleur. Étude de l’espace d’adressage sur un exemple de composant, types de mémoires et leur rôle dans l’architecture, $ Modèle de programmation d’un processeur, jeu d’instructions, exemples de sources en langage assembleur, $ La pile et ses utilisations, $ Analyse du code assembleur généré par un compilateur, $ Interfaces d’entrées-sorties parallèle et série, $ Utilisations des ‘timers’, $ Fonctionnement en régime d’interruption, procédures de traitement d’interruption.

Modalités de mise en œuvre : $ Utiliser un environnement de développement en langage évolué, $ Écrire des applications sur cible à processeur, mettant en œuvre des périphériques d'entrée/sortie, programmée en langage évolué pouvant inclure des fonctions simples en assembleur (utilisation des instructions de traitement des bits, si elles existent), $ Faire comprendre la part matérielle et la part logicielle dans le traitement des interruptions, $ S’appuyer sur des exemples de programmes de traitement du signal (mise en œuvre de convertisseurs analogique-numérique et numérique-analogique ), de dialogue via des interfaces série.

Prolongements : $ Par modules complémentaires MC-II3, MC-II2.

Mots-clés : $ Microcontrôleur, périphériques, architecture, variables, mémoires, registres, ports, interruptions.

3. Parts Location Diagram

Place Plan - Component Side

User Manual

7

MC9S12DP512 Device Guide V01.25

23

Figure 1-1 MC9S12DP512 Block Diagram

512K Byte Flash EEPROM

14K Byte RAM

Enhanced Capture

RESET

EXTALXTAL

VDD1,2VSS1,2

SCI0

4K Byte EEPROM

BKGD

R/W

MODB

XIRQ

NOACC/XCLKS

SystemIntegration

Module(SIM)

VDDR

CPU12

Periodic InterruptCOP WatchdogClock Monitor

Single-wire Background

Breakpoints

PLLVSSPLL

XFCVDDPLL

Multiplexed Address/Data Bus

VDDAVSSA

VRHVRLATD0

MultiplexedWide Bus

Multiplexed

VDDXVSSX

Internal Logic 2.5V

Narrow Bus

PPAGE

VDDPLLVSSPLL

PLL 2.5V

IRQ

LSTRBECLKMODA

PA4

PA3

PA2

PA1

PA0

PA7

PA6

PA5

TEST

AD

DR

12A

DD

R11

AD

DR

10A

DD

R9

AD

DR

8

AD

DR

15A

DD

R14

AD

DR

13D

ATA

12D

ATA

11D

ATA

10D

ATA

9D

ATA

8

DAT

A15

DAT

A14

DAT

A13

PB

4P

B3

PB

2P

B1

PB

0

PB

7P

B6

PB

5A

DD

R4

AD

DR

3A

DD

R2

AD

DR

1A

DD

R0

AD

DR

7A

DD

R6

AD

DR

5D

ATA

4D

ATA

3D

ATA

2D

ATA

1D

ATA

0

DAT

A7

DAT

A6

DAT

A5

DAT

A4

DAT

A3

DAT

A2

DAT

A1

DAT

A0

DAT

A7

DAT

A6

DAT

A5

PE3PE4PE5PE6PE7

PE0PE1PE2

AN02

AN06

AN00

AN07

AN01

AN03AN04AN05

PAD03PAD04PAD05PAD06PAD07

PAD00PAD01PAD02

IOC2

IOC6

IOC0

IOC7

IOC1

IOC3IOC4IOC5

PT3PT4PT5PT6PT7

PT0PT1PT2

VRHVRL

VDDAVSSA

VRHVRLATD1

AN10

AN14

AN08

AN15

AN09

AN11AN12AN13

PAD11PAD12PAD13PAD14PAD15

PAD08PAD09PAD10

VDDAVSSA

RXDTXD

MISOMOSI

PS3PS4PS5

PS0PS1PS2SCI1

RXDTXD

PP3PP4PP5PP6PP7

PP0PP1PP2

PIX2

PIX0PIX1

PIX3

ECS

PK3

PK7

PK0PK1

XADDR17

ECS

XADDR14XADDR15XADDR16

SCKSS

PS6PS7

SPI0

IICSDASCL

PJ6PJ7

CAN0RXCANTXCAN

PM1PM0

CAN1RXCANTXCAN

PM2PM3

CAN2RXCANTXCAN

PM4PM5

CAN3RXCANTXCAN

PM6PM7

KWH2

KWH6

KWH0

KWH7

KWH1

KWH3KWH4KWH5

PH3PH4PH5PH6PH7

PH0PH1PH2

KWJ0KWJ1

PJ0PJ1

I/O Driver 5V

VDDAVSSA

A/D Converter 5V &

DDRA DDRB

PTA PTB

DD

RE

PT

E

AD

1

AD

0

PT

K

DD

RK

PT

T

DD

RT

PT

P

DD

RP

PT

S

DD

RS

PT

M

DD

RM

PT

H

DD

RH

PT

J

DD

RJ

PK2

BDLC RXBTXB

Clock andResetGenerationModule

Voltage RegulatorVSSR

Debug Module

VDD1,2VSS1,2

VREGEN

VDDRVSSR

Voltage Regulator 5V & I/O

CAN4RXCANTXCAN

MISOMOSISCK

SS

SPI2

MISOMOSISCK

SS

SPI1

PIX4PIX5

PK4PK5

XADDR18XADDR19

Voltage Regulator Reference

KWP2

KWP6

KWP0

KWP7

KWP1

KWP3KWP4KWP5

KWJ6KWJ7

Timer

(J1850)

Mod

ule

to P

ort R

outin

g

PWM2

PWM6

PWM0

PWM7

PWM1

PWM3PWM4PWM5

PWM


24

1.5 Device Memory Map

Table 1-1 and Figure 1-2 show the device memory map of the MC9S12DP512 after reset. Note that afterreset the bottom 1k of the EEPROM ($0000 - $03FF) are hidden by the register space

Table 1-1 Device Memory Map

Address Module Size(Bytes)

$0000 - $000F HCS12 Multiplexed External Bus Interface 16

$0010 - $0014 HCS12 Module Mapping Control 5

$0015 - $0016 HCS12 Interrupt 2

$0017 - $0019 Reserved 3

$001A - $001B Device ID register (PARTID) 2

$001C - $001D HCS12 Module Mapping Control 2

$001E HCS12 Multiplexed External Bus Interface 1

$001F HCS12 Interrupt 1

$0020 - $0027 Reserved 8

$0028 - $002F HCS12 Breakpoint 8

$0030 - $0031 HCS12 Module Mapping Control 2

$0032 - $0033 HCS12 Multiplexed External Bus Interface 2

$0034 - $003F Clock and Reset Generator (PLL, RTI, COP) 12

$0040 - $007F Enhanced Capture Timer 16-bit 8 channels 64

$0080 - $009F Analog to Digital Converter 10-bit 8 channels (ATD0) 32

$00A0 - $00C7 Pulse Width Modulator 8-bit 8 channels (PWM) 40

$00C8 - $00CF Serial Communications Interface 0 (SCI0) 8

$00D0 - $00D7 Serial Communications Interface 0 (SCI1) 8

$00D8 - $00DF Serial Peripheral Interface (SPI0) 8

$00E0 - $00E7 Inter IC Bus 8

$00E8 - $00EF Byte Data Link Controller (BDLC) 8

$00F0 - $00F7 Serial Peripheral Interface (SPI1) 8

$00F8 - $00FF Serial Peripheral Interface (SPI2) 8

$0100- $010F Flash Control Register 16

$0110 - $011B EEPROM Control Register 12

$011C - $011F Reserved 4

$0120 - $013F Analog to Digital Converter 10-bit 8 channels (ATD1) 32

$0140 - $017F Motorola Scalable Can (CAN0) 64

$0180 - $01BF Motorola Scalable Can (CAN1) 64

$01C0 - $01FF Motorola Scalable Can (CAN2) 64

$0200 - $023F Motorola Scalable Can (CAN3) 64

$0240 - $027F Port Integration Module (PIM) 64

$0280 - $02BF Motorola Scalable Can (CAN4) 64

$02C0 - $03FF Reserved 320

$0000 - $0FFF EEPROM array 4096

$0800 - $3FFF RAM array 14336

$4000 - $7FFFFixed Flash EEPROM arrayincl. 1K, 2K, 4K or 8K Protected Sector at start

16384


25

$8000 - $BFFF Flash EEPROM Page Window 16384

$C000 - $FFFFFixed Flash EEPROM arrayincl. 2K, 4K, 8K or 16K Protected Sector at endand 256 bytes of Vector Space at $FF80 - $FFFF

16384

Table 1-1 Device Memory Map

Address Module Size(Bytes)


26

Figure 1-2 MC9S12DP512 Memory Map

* Assuming that a ‘0’ was driven onto port K bit 7 during MCU is reset into normal expanded wide or narrow mode.

$0400

$0000

$0800

$4000

$8000

$C000

$FF00VECTORS

$FFFF

EXTERN

EXPANDED*

VECTORS

NORMALSINGLE CHIP

VECTORS

SPECIALSINGLE CHIP

REGISTERS(Mappable to any 2k Blockwithin the first 32K)

$0000

$03FF

$0000

$0FFF

4K Bytes EEPROM(Mappable to any 4K Block)

14K Bytes RAM(Mappable to any 16Kand alignable to top orbottom)

$4000

$7FFF

16K Fixed FlashPage $3E = 62(This is dependant on thestate of the ROMHM bit)

$8000

$BFFF

16K Page Window32 x 16K Flash EEPROMpages

$C000

$FFFF

16K Fixed FlashPage $3F = 63

$FF00

$FFFF

BDM(if active)

$0800

$3FFF

Reference Manual S12CPUV2

34 Addressing Modes MOTOROLA

Addressing Modes

Table 3-1. M68HC12 Addressing Mode Summary

Addressing Mode Source Format Abbreviation Description

InherentINST

(no externallysupplied operands)

INH Operands (if any) are in CPU registers

ImmediateINST #opr8i

orINST #opr16i

IMMOperand is included in instruction stream

8- or 16-bit size implied by context

Direct INST opr8a DIROperand is the lower 8 bits of an address

in the range $0000–$00FF

Extended INST opr16a EXT Operand is a 16-bit address

RelativeINST rel8

orINST rel16

RELAn 8-bit or 16-bit relative offset from the current pc

is supplied in the instruction

Indexed(5-bit offset)

INST oprx5,xysp IDX5-bit signed constant offset

from X, Y, SP, or PC

Indexed(pre-decrement)

INST oprx3,–xys IDX Auto pre-decrement x, y, or sp by 1 ~ 8

Indexed(pre-increment)

INST oprx3,+xys IDX Auto pre-increment x, y, or sp by 1 ~ 8

Indexed(post-decrement)

INST oprx3,xys– IDX Auto post-decrement x, y, or sp by 1 ~ 8

Indexed(post-increment)

INST oprx3,xys+ IDX Auto post-increment x, y, or sp by 1 ~ 8

Indexed(accumulator offset)

INST abd,xysp IDXIndexed with 8-bit (A or B) or 16-bit (D)

accumulator offset from X, Y, SP, or PC


INST oprx9,xysp IDX19-bit signed constant offset from X, Y, SP, or PC

(lower 8 bits of offset in one extension byte)


INST oprx16,xysp IDX216-bit constant offset from X, Y, SP, or PC

(16-bit offset in two extension bytes)

Indexed-Indirect(16-bit offset)

INST [oprx16,xysp] [IDX2]Pointer to operand is found at...

16-bit constant offset from X, Y, SP, or PC(16-bit offset in two extension bytes)

Indexed-Indirect(D accumulator offset)

INST [D,xysp] [D,IDX]Pointer to operand is found at...

X, Y, SP, or PC plus the value in D


73

Section 5 Resets and Interrupts

5.1 Overview

Consult the Exception Processing section of the CPU12 Reference Manual for information on resets andinterrupts.

5.2 Vectors

5.2.1 Vector Table

Table 5-1 lists interrupt sources and vectors in default order of priority.

Table 5-1 Interrupt Vector Locations

Vector Address Interrupt Source CCRMask Local Enable HPRIO Value

to Elevate$FFFE, $FFFF Reset None None –

$FFFC, $FFFD Clock Monitor fail reset None PLLCTL (CME, SCME) –

$FFFA, $FFFB COP failure reset None COP rate select –

$FFF8, $FFF9 Unimplemented instruction trap None None –

$FFF6, $FFF7 SWI None None –

$FFF4, $FFF5 XIRQ X-Bit None –

$FFF2, $FFF3 IRQ I-Bit IRQCR (IRQEN) $F2

$FFF0, $FFF1 Real Time Interrupt I-Bit CRGINT (RTIE) $F0

$FFEE, $FFEF Enhanced Capture Timer channel 0 I-Bit TIE (C0I) $EE

$FFEC, $FFED Enhanced Capture Timer channel 1 I-Bit TIE (C1I) $EC

$FFEA, $FFEB Enhanced Capture Timer channel 2 I-Bit TIE (C2I) $EA

$FFE8, $FFE9 Enhanced Capture Timer channel 3 I-Bit TIE (C3I) $E8





$FFDE, $FFDF Enhanced Capture Timer overflow I-Bit TSRC2 (TOI) $DE

$FFDC, $FFDD Pulse accumulator A overflow I-Bit PACTL (PAOVI) $DC

$FFDA, $FFDB Pulse accumulator input edge I-Bit PACTL (PAI) $DA

$FFD8, $FFD9 SPI0 I-Bit SPICR1 (SPIE, SPTIE) $D8

$FFD6, $FFD7 SCI0 I-BitSCICR2

(TIE, TCIE, RIE, ILIE)$D6

$FFD4, $FFD5 SCI1 I-BitSCICR2

(TIE, TCIE, RIE, ILIE)$D4

$FFD2, $FFD3 ATD0 I-Bit ATDCTL2 (ASCIE) $D2

$FFD0, $FFD1 ATD1 I-Bit ATDCTL2 (ASCIE) $D0

$FFCE, $FFCF Port J I-BitPIEJ

(PIEJ7, PIEJ6, PIEJ1, PIEJ0)$CE

$FFCC, $FFCD Port H I-Bit PIEH (PIEH7-0) $CC


74

5.3 Effects of Reset

When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to therespective module Block Guides for register reset states.

5.3.1 I/O pins

Refer to the HCS12 Multiplexed External Bus Interface (MEBI) Block Guide for mode dependent pinconfiguration of port A, B, E and K out of reset.

Refer to the PIM Block Guide for reset configurations of all peripheral module ports.

$FFCA, $FFCB Modulus Down Counter underflow I-Bit MCCTL (MCZI) $CA

$FFC8, $FFC9 Pulse Accumulator B Overflow I-Bit PBCTL (PBOVI) $C8

$FFC6, $FFC7 CRG PLL lock I-Bit CRGINT (LOCKIE) $C6

$FFC4, $FFC5 CRG Self Clock Mode I-Bit CRGINT (SCMIE) $C4

$FFC2, $FFC3 BDLC I-Bit DLCBCR1 (IE) $C2

$FFC0, $FFC1 IIC Bus I-Bit IBCR (IBIE) $C0

$FFBE, $FFBF SPI1 I-Bit SPICR1 (SPIE, SPTIE) $BE

$FFBC, $FFBD SPI2 I-Bit SPICR1 (SPIE, SPTIE) $BC

$FFBA, $FFBB EEPROM I-Bit ECNFG (CCIE, CBEIE) $BA

$FFB8, $FFB9 FLASH I-Bit FCNFG (CCIE, CBEIE) $B8

$FFB6, $FFB7 CAN0 wake-up I-Bit CANRIER (WUPIE) $B6

$FFB4, $FFB5 CAN0 errors I-Bit CANRIER (CSCIE, OVRIE) $B4

$FFB2, $FFB3 CAN0 receive I-Bit CANRIER (RXFIE) $B2

$FFB0, $FFB1 CAN0 transmit I-Bit CANTIER (TXEIE2-TXEIE0) $B0

$FFAE, $FFAF CAN1 wake-up I-Bit CANRIER (WUPIE) $AE

$FFAC, $FFAD CAN1 errors I-Bit CANRIER (CSCIE, OVRIE) $AC

$FFAA, $FFAB CAN1 receive I-Bit CANRIER (RXFIE) $AA

$FFA8, $FFA9 CAN1 transmit I-Bit CANTIER (TXEIE2-TXEIE0) $A8

$FFA6, $FFA7 CAN2 wake-up I-Bit CANRIER (WUPIE) $A6

$FFA4, $FFA5 CAN2 errors I-Bit CANRIER (CSCIE, OVRIE) $A4

$FFA2, $FFA3 CAN2 receive I-Bit CANRIER (RXFIE) $A2

$FFA0, $FFA1 CAN2 transmit I-Bit CANTIER (TXEIE2-TXEIE0) $A0

$FF9E, $FF9F CAN3 wake-up I-Bit CANRIER (WUPIE) $9E

$FF9C, $FF9D CAN3 errors I-Bit CANRIER (CSCIE, OVRIE) $9C

$FF9A, $FF9B CAN3 receive I-Bit CANRIER (RXFIE) $9A

$FF98, $FF99 CAN3 transmit I-Bit CANTIER (TXEIE2-TXEIE0) $98

$FF96, $FF97 CAN4 wake-up I-Bit CANRIER (WUPIE) $96

$FF94, $FF95 CAN4 errors I-Bit CANRIER (CSCIE, OVRIE) $94

$FF92, $FF93 CAN4 receive I-Bit CANRIER (RXFIE) $92

$FF90, $FF91 CAN4 transmit I-Bit CANTIER (TXEIE2-TXEIE0) $90

$FF8E, $FF8F Port P Interrupt I-Bit PIEP (PIEP7-0) $8E

$FF8C, $FF8D PWM Emergency Shutdown I-Bit PWMSDN (PWMIE) $8C

$FF80 to$FF8B

Reserved

Alphabetical List of Commands file:///f:/Temp/DOCS_TP_II2/Doc_NoIce_8/cmdlist.htm

1 sur 5 11/01/2006 00:21

NoIce Alphabetical List of CommandsA B C D E F G H I J K L M N O P Q R S T U V W X Y Z ;

For more details on the operation and parameter format of each command, click on the commandname hot-link.

In each command:

curly brackets {} denote optional parameters."addr" denotes an address or address expression"size" denotes a size or size expression"value" denotes an expression

ASSEMBLE {addr} Assemble into memoryASM {addr} Assemble into memoryAUTOGEN value Abbreviation of AUTOGENERATEAUTOGENERATE value Turn automatic symbol generation on and offB {addr} Abbreviation of BREAKPOINTBREAK Same as HALTBREAKPOINT {addr} Insert, delete, or display breakpointsBRK value Begin (value=1) or end (value=0) serial line breakCALL {addr} Call a subroutineCALLSKIP name skipsize Define a subroutine called with post-bytesCAP file Abbreviation of CAPTURECAPTURE file Capture disassembly, dump, and target output to fileCASE value Turn symbol case sensitivity on and offCHECK addr size Abbreviation of CHECKSUMCHECKSUM addr size Compute byte checksum on regionCLEARLINEINGO {Y} Delete all source line informationCLEARSYMBOLS {Y} Delete all symbolsCOPY addr1 size addr2 Copy memory from addr1 to addr2D {addr} {size} Abbreviation of DUMPDEF name value {%type} Abbreviation of DEFINEDEFB name value {%type} Abbreviation of DEFBASEDEFBASE name value {%type} Define base symbol "name". Optional data type override

DEFINE name value {%type} Define global symbol "name". Optional data type override

DEFREG name address size Define pseudo-register "name".DEFSCOPED name value {%type} Define scoped symbol "name". Optional data type override


2 sur 5 11/01/2006 00:21

DEFS name value {%type} Abbreviation of DEFSCOPEDDEFTYPE name offset %type Define data type "name"

DEFT name offset %type Abbreviation of DEFTYPEDELAY time Set delay for command playbackDTR value Set serial line DTR active (value=1) or inactive (value=0)DUMP {addr} {size} Dump block of memory at addr in hex and ASCIIE {addr} {val} {%type} Abbreviation of EDITECHO {text string} Echo "text string" to data windowEDIT {addr} {%type} {val.} Examine/change memory. Optional data type override

ENDENUM {name} End definition of enumeration "name"ENDFILE {addr} Define the end of the current file scope for symbol definitionENDFUNCTION {addr} Define the end of the current function scope for symbol definitionENDF {address} Abbreviation of ENDFUNCTIONENDS size {name} Abbreviation of ENDSTRUCT ENDSTRUCT size {name} Declare the end of the current data structure definitionENUM offset {name} {%type} Begin definition of enumeration "name"

ENUMVAL value name Define "name" as a member of the current enumerationEX1 {tail} Run the extension EX1EX2 {tail} Run the extension EX2F {text string} Abbreviation of FINDFIND {text string} Find the string in the view fileFILE file {offset} Define the current file for source debugFILL addr size value Fill memory block at addr with valueFRAMEPOINTER str Set name of IEEE 695 frame pointerFUNC name {addr} Abbreviation of FUNCTIONFUNCTION name {addr} Define a function for scoped symbol definitionG {addr} Abbreviation of GOGO {addr} Begin execution at addr or at PCHALT Interrupt target executionI addr Abbreviation of ININ addr Read byte from portINTSIZE n Set size of IEEE 695 integerISTEP Step one machine instructionL file {offset} {B} Abbreviation of LOADLARGEPOINTERSIZE n Set size of IEEE 695 large pointer


3 sur 5 11/01/2006 00:21

LASTFILELOADED{filename}

Delete breakpoints, watches, symbols, and line information if thefilename or its modification time have changed from the last invocation of this command.

LINE linum View the specified source lineLINE linum addr Define address of source lineLEADINGDIGIT n Set requirement for leading digit on hex numbersLOAD file {offset} {B} Load Intel, Motorola/Freescale, Tektronix or other fileLONGSIZE n Set size of IEEE 695 long integerM {addr} Same as MEMMEM {addr} Show/edit the block of memory at addr in hex or ASCIIMODE val Set source mode (0,1,2)N Abbreviation of NEXTNEXT Step over subroutineNOFILES Delete file and line number informationO addr val Abbreviation of OUTOPEN file Open file via LOAD, PLAY, or VIEWOUT addr val Write byte to portPLAY file Execute commands from "file"POINTERSIZE n Set size of default pointerQ Abbreviation of QUITQUIT Exit to DOSR {reg val} Abbreviation of REGISTERRADIX val Set radix for formatted input and output. "Val" must be 10 or 16REC file Abbreviation of RECORDRECORD file Record commands to fileREGISTER {reg val} Change registerREM {string} Remark (comment) for command filesRESET Reset target hardwareRTS value Set serial line RTS active (value=1) or inactive (value=0)S {addr} Abbreviation of SOURCES2FORMAT format Set the format of Motorola/Freescale S2 addresses

SAVE file addr size Save a block of memory as an Intel or Motorola/Freescale hex file, or as a binary file

SCOPE name Set current scope for scoped symbol definition and useSET name value Same as DEFINESFUNC name {addr} Abbreviation of STATICFUNCTIONSHORTSIZE n Set size of IEEE 695 short integerSMALLPOINTERSIZE n Set size of IEEE 695 small pointerSOURCE {addr} Show source code at beginning at addrST Abbreviation of STEP


4 sur 5 11/01/2006 00:21

STATETEXT n text Set text for target state nSTATICFUNCTION name {addr} Define a static function for scoped symbol definition

STEP Step into subroutinesSTOP Stop recording commands to fileSTRUCT offset {name} Begin definition of a data structureSYM expr Abbreviation of SYMBOLSYMBOL expr Show symbol with value "expr"TIME {comment} Show elapsed time since last TIME commandU {addr} Abbreviation of UNASMUNASM {addr} Disassemble beginning at addrV {file} Abbreviation of VIEWVAL expr Abbreviation of VALUEVALUE expr Show value of "expr"VER Abbreviation of VERSIONVERSION Show host and target versionsVIEW {file} View fileW addr {len} {%type} Abbreviation of WATCHWAIT time Wait for "time" millisecondsWAITFORSTOP {time} Wait up to "time" seconds for the target to stop runningWATCH addr {len} {%type} Watch data at "addr"

; {string} Remark (comment) for command files

The following commands may also be invoked by pressing the indicated function key.F1 HelpF2 Dump next blockF3 Find nextF4 View fileF5 GoF6 List breakpointsF7 Step into (traditional NoICE key)F8 Step over (traditional NoICE key)F9 Step one instructionF10 Step over (same as DevStudio)F11 Step into (same as DevStudio)

Pressing Alt and a function key will attempt to invoke the command files ALTF1.NOI throughALTF12.NOI, respectively.

NoICE (tm) Debugger, Copyright © 2005 by John Hartman

IUT GEII Rouen Freescale 9S12 Instruction Set Page 1 / 2

ABA Add accumulator B to accumulator A

ABX Add accumulator B to index register X

ABY Add accumulator B to index register Y

ADCA Add with carry to accumulator A ADCB Add with carry to accumulator B

ADDA Add without carry to accumulator A

ADDB Add without carry to accumulator B

ADDD Add without carry to accumulator D

ANDA Logical and with accumulator A ANDB Logical and with accumulator B ANDCC Logical and CCR with mask ASL Arithmetic shift left memory

ASLA Arithmetic shift left accumulator A

ASLB Arithmetic shift left accumulator B

ASLD Arithmetic shift left accumulator D

ASR Arithmetic shift right memory

ASRA Arithmetic shift right accumulator A

ASRB Arithmetic shift right accumulator B

BCC Branch if carry clear BCLR Clear bit(s) in memory BCS Branch if carry set BEQ Branch if equal BGE Branch if greater than or equal BGND Enter background debug mode BGT Branch if greater than BHI Branch if higher

BHS Branch if higher or same BITA Bit test accumulator A BITB Bit test accumulator B BLE Branch if less than or equal BLO Branch if lower BLS Branch if lower or same BLT Branch if less than BMI Branch if minus BNE Branch if not equal BPL Branch if plus BRA Branch always

BRCLR Branch if bit clear BRN Branch never

BRSET Branch if bits set BSET Set bit(s) in memory BSR Branch to subroutine BVC Branch if overflow cleared BVS Branch if overflow set

CALL call subroutine in extended memory

CBA Compare accumulator A and B CLC Clear carry bit CLI Clear interrupt bit CLR Clear memory CLRA Clear accumulator A CLRB Clear accumulator B

CLV Clear two’s complement overflow bit

CMPA Compare accumulator A CMPB Compare accumulator B COM One’s complement on memory

COMA One’s complement on accumulator A

COMB One’s complement on accumulator B

CPD Compare accumulator D CPS Compare register SP CPX Compare index register X CPY Compare index register Y DAA Decimal adjust accumulator A

DBEQ Decrement counter and branch if equal to zero

DBNE Decrement counter and branch if not equal to zero

DEC Decrement memory location DECA Decrement accumulator A DECB Decrement accumulator B DES Decrement register SP DEX Decrement index register X DEY Decrement index register Y EDIV Division 32-bits/16 bits (unsigned) EDIVS Division 32-bits/16 bits (signed) EMACS Multiply and accumulate signed

EMAXD Maximum of 2 unsigned integer in accumulator D

EMAXM Maximum of 2 unsigned integer in memory

EMIND Minimum of 2 unsigned integer in accumulator D

EMINM Minimum of 2 unsigned integer in memory

EMUL 16-bit * 16-bit multiplication (unsigned)

EMULS 16-bit * 16-bit multiplication (signed)

EORA Exclusive or with accumulator A EORB Exclusive or with accumulator B ETBL Table Lookup and Interpolate EXG Exchange register contents FDIV 16-bit / 16-bits fractional divide IBEQ Increment and branch if equal to

zero

IBNE Increment and branch if not equal to zero

IDIV 16-bit / 16-bit integer division (unsigned)

IDIVS 16-bit / 16-bit integer division (signed)

INC Increment memory location INCA Increment accumulator A INCB Increment accumulator B INS Increment register SP INX Increment index register X INY Increment index register Y JMP Jump JSR Jump to subroutine LBCC Long branch if carry clear LBCS Long branch if carry Set LBEQ Long branch if equal

LBGE Long branch if greater than or equal

LBGT Long branch if greater than LBHI Long branch if higher LBHS Long branch if higher or same LBLE Long branch if Less Than or equal LBLO Long branch if lower LBLS Long branch if lower or same LBLT Long branch if less than LBMI Long branch if Minus LBNE Long branch if not equal LBPL Long branch if plus LBRA Long branch always LBRN Long branch never LBVC Long branch if overflow clear LBVS Long branch if overflow set LDAA Load accumulator A

IUT GEII Rouen Freescale 9S12 Instruction Set Page 2 / 2

LDAB Load accumulator B LDD Load accumulator D LDS Load register SP LDX Load index register X LDY Load index register Y LEAS Load SP with effective address LEAX Load X with effective address LEAY Load Y with effective address LSL Logical shift left in memory LSLA Logical shift left accumulator A LSLB Logical shift left accumulator B LSLD Logical shift left accumulator D LSR Logical shift left in memory LSRA Logical shift right accumulator A LSRB Logical shift right accumulator B LSRD Logical shift right accumulator D

MAXA Get maximum of 2 unsigned byte in accumulator A

MAXM Get maximum of 2 unsigned byte in memory

MEM Membership function

MINA Get minimum of 2 unsigned byte in accumulator A

MINM Get minimum of 2 unsigned byte in memory

MOVB Memory to memory byte move MOVW Memory to memory word move MUL 8*8-bit unsigned multiplication NEG Negate memory (2’s complement)

NEGA Negate accumulator A (2’s complement)

NEGB Negate accumulator B (2’s complement)

NOP No operation ORAA Inclusive or with accumulator A

ORAB Inclusive or with accumulator B ORCC Inclusive or CCR with mask PSHA Push accumulator A PSHB Push accumulator B PSHC Push register CCR PSHD Push accumulator D PSHX Push index register X PSHY Push index register Y PULA Pop accumulator A PULB Pop accumulator B PULC Pop register CCR PULD Pop accumulator D PULX Pop index register X PULY Pop index register Y REV Rule Evaluation for 8-bits values REVW Rule Evaluation for 16-bits values ROL Rotate memory left ROLA Rotate left accumulator A ROLB Rotate left accumulator B ROR Rotate right memory RORA Rotate right accumulator A RORB Rotate right accumulator B RTC Return from call RTI Return from interrupt RTS Return from subroutine SBA Subtract accumulators

SBCA Subtract with carry from accumulator A

SBCB Subtract with carry from accumulator B

SEC Set carry bit SEI Set interrupt bit

SEV Set two’s complement overflow bit

SEX Sign extend into 16-bit register

STAA Store accumulator A STAB Store accumulator B STD Store accumulator D STOP Stop processing STS Store register SP STX Store index register X STY Store index register Y

SUBA Subtract without carry from accumulator A

SUBB Subtract without carry from accumulator B

SUBD Subtract without carry from accumulator D

SWI Software interrupt

TAB Transfer accumulator A to accumulator B

TAP Transfer accumulator A to CCR

TBA Transfer accumulator B to accumulator A

TBEQ Test counter and branch if equal to zero

TBL 8-Bit Table Lookup and Interpolate

TBNE Test counter and branch if not equal to zero

TFR Transfer register to register TPA Transfer CCR to accumulator A TRAP Software interrupt TST Test memory TSTA Test accumulator A TSTB Test accumulator B TSX Transfer SP to index register X TSY Transfer SP to index register Y TXS Transfer index register X to SP TYS Transfer index register Y to SP WAI Wait for Interrupt

WAV Weighted Average Calculation

XGDX Exchange accumulator D with index register X

XGDY Exchange accumulator D with index register Y

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˘ ˇ · 2009-01-29 · (if active) $0800 $3FFF Reference Manual S12CPUV2 34 Addressing Modes...

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