© 2009 IBM Corporation Verification of embedded system specifications using collaborative...

© 2009 IBM Corporation

Verification of embedded system specificationsusing collaborative simulation of SysML and Simulink models

Ryo Kawahara*, Hiroaki Nakamura*, Dolev Dotan**, Andrei Kirshin**, Takashi Sakairi*, Shinichi Hirose*, Kohichi Ono*, Hiroshi Ishikawa* *Tokyo Research Laboratory, IBM Research**Haifa Research Laboratory, IBM Research

Haifa Research Lab – Model Driven Engineering Technologies Group


AbstractThe authors propose an extension of SysML

which enables description of continuous-time behavior.

The authors also develop its execution tool integrated on Eclipse-based platform by exploiting co-simulation of SysML and MATLAB / Simulink.

To demonstrate the effectiveness of the tool and the extension to SysML in verifying specifications of an embedded system, we create a sample model and analyze its execution results by checking constraints under a test case.



Introduction In the development of an embedded system, it is

important to verify that the specification of the system satisfies the requirements at an early stage

– One approach to achieve this is to model and simulate the system during the analysis

– Systems Modeling Language (SysML) is an extension of UML for embedded systems to include heterogeneous elements such as software, electronics, or mechanics



SubjectEmbedded systems often include control systems

– A control system is usually a hybrid system, the mixture of continuous-time and discrete behavior

– Continuous-time behavior in UML / SysML has not been defined

– Simulation of control system is usually done in a specialized tools, such as the MathWorks MATLAB / Simulink

– A UML / SysML behavior is not associated with time

Integration of the continuous-time behavior into the systems model is desired



Background: SysML SysML is an extension of UML2 for systems engineering

Requirements–Requirement diagram

Behaviors–Activity diagram

–State machine diagram

Structures–Block definition diagram

=> class diagram

–Internal block diagram

=> composite structure diagram

Parametrics–Parametric diagram

=> internal block diagram



Background: SimulinkSimulink uses Block diagram

– Block diagram describes the flow of signal between blocks, which process the signal

– This example calculates:

t

dftf0 In1Out1 )(2)(



ApproachUse SysML for a system architecture descriptionUse specific languages for each domain

– Simulink for continuous-time behavior in a control system

Time duration assignment to SysML actionVerify specification by collaborative simulation

– Run multiple simulation in parallel with time synchronization

– Independent time management module



Extended Modeling for Simulation in SysML

Time assignment to action

Continuous data exchange between blocks

Specifying Simulink model as a block behavior

MARTE <<GaStep>> stereotype, or sleep() method in action code

SysML flow ports with connectors in internal block diagram

<<externalModel>> stereotype to specify model file



SysML Execution and Debugging Debugging of behavioral UML models by emulation, supporting:

- Class, Composite Structure Diagrams- State Machines, Activities- Java as Action Language

Extensible to support UML profiles (in this case SysML)

Debugging UI – Model Debugging Perspective (next slide) Diagram animation

Debugging modes: Traditional Debugging

- Start “main”- Run to breakpoint- Stepping

Interactive debugging(model “exerciser”)

- Manually create objects- Invoke operations- Send signals

Current State

Execution Pending

Running Transition

Breakpoint



Model Debugging Perspective

DebugVariables

Console

Diagram Animation

Signals

Event Pools

Instances

Breakpoints

I/OSnippet

Watch

Sleeping



Sleeping ViewShows the queue of sleeping behaviors and behavior elements.

Wakeup time

Current virtual time



Time ManagementData is exchanged and the next Simulink step is

executed at:– End of timed SysML behavioral step (<<GaStep>> or sleep())

– Periodic data exchange event

SysML 　　　　　

object


object

MATLAB / Simulink 　　

Timed schedulerUML execution engine

Time management module

Demands of time

Add periodic data exchange events into the list consists of the discrete events

Time demands to scheduler

MATLAB / Simulink command execution

…Simulation start / stop


object

400

Time

Periodic data exchange events

Discrete events

0 100 200 300

Action1Action2

Action3



Co-simulation with SimulinkAll the Simulink models are referred from a

single temporary Simulink model– Only one Simulink process is used

Simulation data is sent or received through Input/Output S-Functions

Model reference1

Input S-Function

Model reference2

OutputS-Function

Temporary generated Simulink model

Model 1 Model 2

Simulink models which are assigned to SysML behaviors

Data from SysML Data to SysML



Overview of Sample model: Humidifier

Requirements– The humidifier starts vapor emission within 5 minutes since the

power on signal

– The humidifier ends cool down within 10 minutes since the power off signal

– The humidifier keeps the room humidity at a constant level specified by the user automatically

Heater

Reservoir

Circulator fan

Pan

Basic mechanism– The water is boiled by the heater

– Vapor is emitted to the environment by circulator fan



Structure of HumidifierSystem

Simulink model assigned block

State machine assigned block

Block definition diagram

Internal block diagram of HumidifierSystem Flow ports for

continuous I/O

Standard ports for discrete signals

Simulink model assigned blockState machine

assigned block



Behavior of Control blockState machine

diagramSignal from

user interface

Change event that monitors values from

a Simulink blocks



Simulink model for VaporGenerationPlant

heating subsystem

radiation subsystem

evaporation subsystem



Test context

Simulink model assigned block

Block definition diagram

Internal block diagram of TestContext

Flow ports for continuous I/O to

consist a closed loop

Definition of test environment

Test target



Cooling down taking too long time

Test case and resultsTime(s) Command

0 Test start

10 Power on

2000 Power off

3600 Test end

Automatic humidity control



Parametric and time constraint evaluation

Parametric diagramSequence diagram with time constraint

using MARTE profile

Constraint block:Humidity should be kept

near target value

Timed constraint:Cool down should be

finished within 10 minutes



ConclusionWe have developed a verification tool based on

co-simulation of Simulink and SysML

We have extended the modeling capability of SysML to be able to reference Simulink models and specify timed behavior

These extensions enable one to test specifications of a system which includes continuous-time behavior in a closed control loop




Overview of the verification tool

Block2Integer b = 1 Block3

Integer c = 2

Integer eval

eval = f(bb, cc)bb cc

eval

Eval > 80

eval

Virtual time scheduler

Time-aware UML execution engine

Simulink

p q

{h,i}

p q

<x,y,z>

{j,k} l m {n,o}

{a,b,c}|{d,e,(f|g}}

Parametric constraint evaluator Time constraint evaluator

Binary tree for fast eval.

TPTP-basedtest driver

Timed test cases Timed discrete behavior Continuous behavior

Parametric constraints(OMG SysML)

Time constraints(OMG MARTE profile)



Simulink model for Room block

saturation_vapor_pressure subsystem

relative_humidity subsystem



State machine diagram of HeaterControl block



Related works

Reichmann et al. (2004),Telelogic Rhapsody®

C. Nytsch-Geusen (2007),

A. Pop et al., (2007),

T. A. Johnson et al., (2008)

Hooman et al. (2004)

Our approach

Coupling method

Conversion to source code

Conversion to Modelica

Co-simulation of Simulink and Rose® RT

Co-simulation

Simulation time management

By independent module (Rhapsody)

By Modelica By Simulink By independent module

Studies on coupling of UML/SysML and continuous-time simulation (e.g., Simulink)



Related worksSource code level linkage of UML and Simulink

– Reichmann et al., 2004. Telelogic Rhapsody®

Co-simulation of Simulink and UML model on IBM Rational Rose® RealTime

– J. Hooman, N. Mulyar and L. Posta, 2004

Conversion of UML/SysML to Modelica language– C. Nytsch-Geusen, 2007. A. Pop et al., 2007. T. A. Johnson et

al., 2008

– Modelica is a new language to model continuous-time system

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