© 2010 Altera Corporation—Public

Modeling and SimulatingWireless Systems Using MATLAB® and Simulink®

2010 Technology Roadshow

© 2010 Altera Corporation—Public

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Agenda

Introduction Challenges of wireless system modeling and simulation Introduction to MATLAB, Simulink, and blocksets

Models and demonstrations System-level wireless system model RF receiver front-end design Fixed-point design HDL co-simulation

Next steps FPGA implementation

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© 2010 Altera Corporation—Public

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Design Flow Challenges Result in High Verification Costs

Design and Implementation

Research & System Level Design

RequirementsRequirements Algorithms

Integration and Test

Analog Hardware

EmbeddedSoftware

Digital Hardware

VHDL, Verilog SPICEC/C++

Gap #1:Algorithm development is not connected to the design flow.

Gap #2:Multiple tools are used for design and implementation.

Impact:Errors are found too late;

product is delayed.

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© 2010 Altera Corporation—Public

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

System Design Requires Multi-Domain Expertise and Collaboration Signal modeling in three

domains: Time domain Frequency domain Spatial domain

System modeling in three domains: Digital baseband Analog/mixed-signal Radio frequency

Advanced Multifunction RF Concept (AMRFC) Test-Bed Block Diagram (radar-www.nrl.navy.mil)

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© 2010 Altera Corporation—Public

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Requirements

Solution: Multi-domain Modeling and Simulation Unify algorithm research, design, & testing

1. Model the system and requirements in the same industry-standard environment.

2. Model different subsystem domains in one integrated environment.

3. Re-use this model as a testbench throughout the design process

4. Verify implementation details using system testbench and co-simulation with your chosen design tools.

5. Leverage the environment all the way to integration and test.

Design

Analog/RF Models

Environment Models

Algorithms

Digital Models

Timing and Control Logic

Integration and TestTest

Environments

C, C++ VHDL, Verilog

EmbeddedSoftware

Prototype

SPICE

DigitalHardware

AnalogHardware

Implementation

Gen

erat

e

Gen

erat

e

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© 2010 Altera Corporation—Public

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Simulink Key Features Hierarchical, component-based modeling MATLAB® integration Extensive library of predefined blocks Application-specific libraries available Open application program interface (API)

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© 2010 Altera Corporation—Public

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Key Features – Signal Processing Blockset

Waveform coding Matched filter detectors Adaptive beamforming or

detection (STAP) DOA, target detection Beamforming Tracking N-dimensional signals

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Key Features – Communications Blockset

Modulation Sequence generators RF impairments Channel models

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© 2010 Altera Corporation—Public

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Key Features – RF Blockset Complex baseband-equivalent

modeling

Physical blocks account for reflections

Cascaded receiver chains: gain, noise figure, IP3 modeling

Verify RF behavior at system level

Amplifiers, filters, mixers, etc.

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© 2010 Altera Corporation—Public

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Demonstrations

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Example:Digital Down Converter for Radar System

Diplex

DUCPulsetrain/

compress

LO

Mixer FormatPre-filter

Beamweight

IFFT

RF

FormatSpatial

estimate

CorrelateTrack/predict

Threshold

Decisionmaking

Post-processingPost-processingPre-processingPre-processing

Beamweight

process

FPGA implementation

Hig

h-s

pe

ed

s

eri

al

Hig

h-s

pe

ed

s

eri

al

Front endFront end

Hig

h-s

pe

ed

s

eri

al

Hig

h-s

pe

ed

s

eri

al

Example design focusExample design focus

Pre-detect

Beamweight

process

DDC FFT

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© 2010 Altera Corporation—Public

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ADC

Traditional Digital Downconversion

Complex NCO

M:1 Decimating Low Pass FIR

M:1 Decimating Low Pass FIR

I Baseband Data

Q Baseband Data

XReal IF Data

exp ( j θkn + PhsAdj)

Baseband Fc = Carrier

Signal

Frequency, F Baseband Carrier

Signal

Frequency, F

Real IF SignalComplex

Baseband Signal

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© 2010 Altera Corporation—Public

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Polyphase Digital Downconversion350 MSPS

1:2

Demux

exp ( j ωcarrier+0+PhsAdj)

exp ( j ωcarrier+π+PhsAdj)NCO

NCO

X

X

8:1 Decimating FIR 8:1 Decimating FIR

8:1 Decimating FIR 8:1 Decimating FIR

1:2

Demux

exp ( j ωcarrier+π/4+PhsAdj)

exp ( j ωcarrier+5π/4+PhsAdj)NCO

NCO

X

X

8:1 Decimating FIR 8:1 Decimating FIR

8:1 Decimating FIR 8:1 Decimating FIR

1:2

Demux

exp ( j ωcarrier+π/2+PhsAdj)

exp ( j ωcarrier + 3π/2 + PhsAdj)NCO

NCO

X

X

8:1 Decimating FIR 8:1 Decimating FIR

8:1 Decimating FIR 8:1 Decimating FIR

1:2

Demux

exp ( j ωcarrier+3π/4+PhsAdj)

exp ( j ωcarrier+7π/4+PhsAdj)NCO

NCO

X

X

8:1 Decimating FIR 8:1 Decimating FIR

8:1 Decimating FIR 8:1 Decimating FIR

baseband I data

baseband Q data

ADC

2.8 GSPS

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© 2010 Altera Corporation—Public

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ADC

Aliased Polyphase Digital Downconversion

Real IF Data

Baseband Fc = Carrier

SignalFS/2

K=2 for second Nyquist zone

FS

Real IF Signal Spinner selects Nyquist Zone to downconvert

Low Pass FIRФ1

exp ( j 1k 2π/8)X

Low Pass FIRФ2

exp ( j 2k 2π/8)X

Low Pass FIRФ3

exp ( j 3k 2π/8)X

Low Pass FIRФ4

exp ( j 4k 2π/8)X

Low Pass FIRФ5

exp ( j 5k 2π/8)X

Low Pass FIRФ6

exp ( j 6k 2π/8)X

Low Pass FIRФ7

exp ( j 7k 2π/8)X

baseband I data

baseband Q data

Low Pass FIRФ0

exp ( j 0k 2π/8)X

+ X

350 MSPS

Optional Complex NCO

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© 2010 Altera Corporation—Public

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

What We Used Simulink Embedded MATLAB RF Blockset Signal Processing

Blockset Fixed-Point Tool EDA Simulator Links Masked subsystems

and libraries

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© 2010 Altera Corporation—Public

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Key Take-Aways

Integrated tool for collaboration among multiple engineering teams: System engineers Signal processing engineers Antenna designers RF engineers HDL programmers

Environment to explore design tradeoffs: Fixed-point processing RF receiver architecture Beam-forming configurations

Continuous verification flow from system-level specifications to implementation-level component designs

MATLAB® and Simulink® provide:

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© 2010 Altera Corporation—Public

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

Next steps: FPGA implementation

The original Simulink floating-point model and the elaborated fixed-point models are re-used as a system level verification test bench

Verification “deltas” resulting from device-specific behavior are evaluated using system level metrics (BER, Pd, etc.)

Altera® Advanced DSP Builder blocks enable system level verification by maintaining the connection between high level model and FPGA hardware

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© 2010 Altera Corporation—Public

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S.

For More Information about MATLAB Products or Services, Please Contact:

Mainland, ChinaNon-military Industry and Education Users: The MathWorks ChinaWebsite: www.mathworks.cnTel: 86-10-5982-7000Military Industry Users: HiRain TechnologiesWebsite: www.hirain.comTel: 86-10-6484-0606

Hong Kong/ MacauWorld Express Computer Systems Ltd.Tel: 852-2893-3262

Taiwan TeraSoft Inc. Website: www.terasoft.com.twTel: 886-2-2788-9300

US Headquarters： The MathWorks, Inc

Website: www.mathworks.com Tel: 10-508-647-7000

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© 2010 Altera Corporation—Public

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