© 2013 IBM Corporation

Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation

Erez Bilgory Alex Goryachev Ronny Morad Tali Rabetti

IBM Research – Haifa

June 2013

2

Background: System-level simulation

Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation

Pre-silicon, system-level RTL simulation:

– Many cores (possibly multithreaded)

– Many I/O devices, bridges, HW accelerators, message-passing components

– All components run in parallel

– Only RTL, no real SW in the simulated system

Processor Core#1

Processor Core#N

HW accelerator

unit

I/O BFM#2

I/O BFM#1

Memory

Message passing

unit

System bus

I/O bus

Processor Core#2

…

IO bridgeMemory controller

3

Background: Test generator

Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation

Concrete test cases (including instruction

stream for each processor core)

Abstract test case

(High level test description)

System-leveltest generator

4

Background: Test generator

Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation

System-leveltest generator

Memory Read

IO rd

Memory write

Send message to core 2

IO Wr

Memory write

Memory write

Send message to core 1

IO Rd

Memory read

Core 1 Core 2

Mix 10 instructions of types:

50%:

25%:

25%:

Memory access

IO Rd/Wr

Send message

Abstract test case Concrete test cases

5

Background: Message passing component

Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation

Message Passing Unit

FIFO 0

FIFO 1

FIFO 4

FIFO 2

FIFO 3

FIFO 0

FIFO 1

FIFO 4

FIFO 2

FIFO 3

connection Table

E0

E1

E2

(1) Write

data

(2) Initiate message

transmission

(3) Read data

Processor Core#1

Processor Core#2

Processor Core#3

Input Output

Processor Core#4

6

Background: Message passing component

Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation

Message Passing Unit

FIFO 0

FIFO 1

FIFO 4

FIFO 2

FIFO 3

FIFO 0

FIFO 1

FIFO 4

FIFO 2

FIFO 3

connection Table

E0

E1

E2

(1) Write

data

(2) Initiate message

transmission

Reconfigure entry

(3) Read data

Processor Core#1

Processor Core#2

Processor Core#3

Input Output

Processor Core#4

7

Mix 10 instructions of types:

34%:

33%:

33%:

Random

Use entry

Reconfigure entry

The reconfiguration challenge: Shared connection table entry reconfiguration

Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation

Random

Reconfigure E1

Random

Reconfigure E2

Use E1

Use E1

Random

Use E2

Reconfigure E1

Random

Core 1 Core 2

Random

Runtime

Actual runtime of each operation is unknown before simulation, and

can change from simulation to simulation

Random

Reconfigure E1

Random

Reconfigure E2

Use E1

Use E1

Random

Use E2

Reconfigure E1

Core 1 Core 2

8

The reconfiguration challenge

Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation

Core 1 Core 2

Random

Reconfigure E1

Random

Reconfigure E2

Use E1

Use E1

Random

Use E2

Reconfigure E1

Random

The arrowed operations need

to be synced

9

The reconfiguration challenge

Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation

Core 1 Core 2

Random

Reconfigure E1

Random

Reconfigure E2

Use E1

Use E1

Random

Use E2

Reconfigure E1

Random

Signal

Signal

Signal

Poll

Poll

Poll

Signal

Poll

Poll: Wait until a known value is written to a semaphore

address before operation

Signal: Write a known value to a semaphore address after

operation

10

The reconfiguration challenge

Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation

Is this scenario correct?

Does it have the needed synchronization operations?

Does it have deadlocks?

Lose the test generator’s power!

Only one test scenario

Core 1 Core 2

Use entry 1

Signal semaphore 1

Random instructions

Poll semaphore 1

Use entry 1

Poll semaphore 2

Use entry 2

Poll semaphore 3

Reconfigure entry 3

Signal semaphore 3

Use entry 2

Random instructions

Poll semaphore 1

Reconfigure entry 1

Signal semaphore 1

Reconfigure entry 2

Signal semaphore 2

Use entry 3

Signal semaphore 3

Random instructions

Poll semaphore 3

Use entry 3

Directed test, complete with needed

synchronization operation

11

Our solution: Automatic synchronization

Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation

Test generator tracker

Transactions: thread, entry, use/Reconfigure

Semaphore address and value to poll, if needed

Addition

The output of the tracker is a set of synchronization operations needed to preserve the intended ordering of specific transactions with respect to each other

Other transactions remain unordered

Template

Test cases

random

Reconfigure E1

random

Reconfigure E2

Use E1

Use E1

random

Use E2

Reconfigure E1

random

Core 1 Core 2

12

Our solution: Results

Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation

Template before

Core 1 Core 2Use entry 1

Signal semaphore 1

Random instructions

Poll semaphore 1

Use entry 1

Poll semaphore 2

Use entry 2

Poll semaphore 3

Reconfigure entry 3

Signal semaphore 3

Use entry 2

Random instructions

Poll semaphore 1

Reconfigure entry 1

Signal semaphore 1

Reconfigure entry 2

Signal semaphore 2

Use entry 3

Signal semaphore 3

Random instructions

Poll semaphore 3

Use entry 3

BEFORE: Directed test, with synchronization

operation

AFTER: Totally random test, now

possible

Mix 10 instructions of types:

34%:

33%:

33%:

Random

Use entry

Reconfigure entry

13

Summary

Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation

Existing state-of-the-art constraint random test generator for system-level testing

New hardware requires entry reconfiguration as part of the verification

We implemented automatic barrier insertion that eliminates the need for complex directed tests

The new mechanism allows random generation of tests that use and reconfigure shared entries, with minimal intrusiveness

In the future, the same solution may be applicable for other reconfiguration challenges

© 2013 IBM Corporation

For more information, contact: Erez Bilgory (erezbi@il.ibm.com) Alex Goryachev (gory@il.ibm.com)

Ronny Morad (morad@il.ibm.com)

Tali Rabetti (talis@il.ibm.com)

IBM Research – Haifa

Enabling easy creation of HW reconfiguration scenarios for system level pre-silicon simulation

Thank You!