We present an operation scheme for a dc-dc converter consist-ing of a class-E inverter and a class-E rectifier to always achievezero-voltage zero-dv/dt switching at a wide range of input andoutput voltages. To cope with the high sensitivity due to loadvariations, previous approaches either forgo the zero-dv/dt turn-on switching conditions or required additional components andtopological changes. Instead, the proposed strategy modulates theduty cycles and switching frequencies depending on the inputand output voltages to always achieve zero-dv/dt turn-on switch-ing, and thus minimizes switching losses while preserving thestructural simplicity of the converter. Experiments demonstratethe prototype converter maintaining the desired soft switchingcondition under 80-to-200 V input voltage and 5-to-20 V outputvoltage variations. In an additional prototype we implementeda similar design with synchronous rectification that achieves apeak efficiency of 92.3 % at 80 V input voltage, 12 V outputvoltage, and 26.9 W output power.
I. INTRODUCTION
High frequency power conversion enables system size andweight reductions, new applications [1], [2], and new ways tobuild power converters [3]. Among many resonant convertertopologies that eliminate switching loss for high frequencyoperation, class-E [4]–[6] is a popular choice for its circuitsimplicity, ease of design, tuning, and because it only need asimple ground-referenced gate drive. Just as many other typesof resonant converters, conventional class-E converters operateefficiency only on a narrow range of input and output voltages.This paper presents an operation scheme to overcome thislimitation by changing the transistor duty cycle and switchingfrequency.
The main disadvantage of the class-E converter is its sen-sitivity to variations on the input and output conditions [7].When the inverter is designed to operate at 50 % duty cycle,[8] reports 5 % inverter efficiency drop by a twofold increaseor decrease in the load resistance. Drain voltage waveformsin [8]–[10] show severe switching losses introduced by loadvariations in a class-E amplifier. This high sensitivity isproblematic when the circuit is to be used for applicationsthat demand flexible input and output conditions, such as auniversal mobile battery charger in which the input voltageshould typically range from 85 Vac to 265 Vac, and the outputvoltage from 5 Vdc to 20 Vdc.
The design outlined in [10] overcomes this problem bytuning the converter such that the zero crossing of the voltage
across the switch always occurs at a constant timing. Thistuning method guarantees zero-voltage switching under vary-ing input and output voltage conditions provided that the gatedrive signal has an accurate and precise duty cycle as wellas fast rise time. Because this strategy forgoes the zero-dv/dtduring the turn-on transition, a slight deviation in the switchingtiming may lead to significant switching loss, especially athigh frequency. Using a resistance compression network [9] isanother effective strategy to tackle the sensitivity issue in theseconverters. The impedance network consisting of inductorsand capacitors significantly reduces the range of the loadvariations when seen from the input of the network. Althoughthis method adds several passive components to the systemand requires two identical loads, this solution is generallyapplicable beyond class-E to other topologies to deal with theload variation problem.
This paper presents a new method to deal with the sensitivityof a class-E converter to the input and output conditions. Fora dc-dc converter consisting of a class-E inverter and a class-E rectifier [11], we use different duty cycles and frequenciesdepending on the input and output voltages to always achievezero-voltage zero-dv/dt switching. This strategy adds noadditional components on the power stage, although at theexpense of potentially more complicated design of the gatedrive unit. Since the proposed method only handles input andoutput voltage conditions, a proper control strategy such ason-off control [12], [13] is necessary to maintain the desiredoutput current level.
The remainder of this paper is organized as follows. Sec-tion II explains how to calculate the duty cycle and fre-quency values for the desired soft switching. We perform theanalysis on an example converter to illustrate the calculationsteps. Section III shows the experimental verification andachievements. We build a converter and test it to validatethe theoretical analysis, identify sources of power loss, andimprove the efficiency by synchronous rectification. We alsobriefly introduce a new way to design a class-E converterwith a loosely-coupled transformer [12]–[16], and describe itsbenefit. Section IV concludes the paper.
Fig. 1. The class-E dc-dc converter that is the subject of our study.Instead of large (ideally infinite) choke inductance [4], [11], a finite dc-feed inductance [5] is used in both the inverter and the rectifier. (a) A dc-dcconverter consisting of a class-E inverter and a class-E rectifier [11]. A seriesLC filter lies between them. (b) The class-E inverter under the assumptionthat only sinusoidal ac current with Is half peak-to-peak amplitude flows intothe LC filter branch and the rectifier. (c) The class-E rectifier [5], [11] underthe assumption that it is driven by a sinusoidal input current with Is halfpeak-to-peak amplitude.
II. DUTY CYCLE AND FREQUENCY CALCULATIONS
A. Calculation Steps
The dc-dc converter that is the subject of our study consistsof a class-E inverter and a class-E rectifier [11], both of whichhave finite dc-feed inductance [5]. Fig. 1a is the schematic ofthe circuit. Analyses throughout this section are based onfollowing assumptions: First, Q and D are ideal switches.They have zero forward voltage drop, zero on-resistance, aswell as zero turn-on and -off time. Their junction capacitancesare absorbed to the parallel capacitance Cinv and Crect,and their nonlinearity is negligibly small. Second, all passiveelements are ideal. Especially, series resistances of inductorLinv , Ls, and Lrect are negligibly small. Lastly, the currentflowing through Ls-Cs branch is sinusoidal.
We explain how to determine the switching frequency ω,inverter duty cycle dinv and the rectifier duty cycle drect thatachieve zero-voltage and zero-dv/dt switching for a givenconverter design. By a given converter design we mean thefollowing values are given: the input dc voltage Vin; theinverter-side resonant inductance Linv and capacitance Cinv;the filter inductance Ls and capacitance Cs; the rectifier-side resonant inductance Lrect and capacitance Crect; and theoutput dc voltage Vout.
Assuming that a sinusoidal ac current flows between the in-verter and the rectifier, we can divide the circuit of Fig. 1a into
TABLE ICOMPONENT VALUES OF THE EXAMPLE CONVERTER WITH VARIABLE
two parts: an inverter driving a load impedance Rload+jXload
with a sinusoidal load current of Is half-peak-to-peak ampli-tude [Fig. 1b]; and a rectifier presenting an input impedanceRrect+jXrect and being driven by a sinusoidal current sourcewith Is half-peak-to-peak amplitude [Fig. 1c] [11].
Fig. 2 are general solution maps of dinv , drect, Rrect,Rload, Xrect, and Xload for zero-voltage zero-dv/dt switching(derivation details are in Appendix A; Python code thatcalculates and plots the solution map is in Appendix B; basicideas of the derivation are from [17]–[20]). Because a class-E inverter operation is time-reversal of a class-E rectifieroperation [21], [22], the solution map for Xload equals to thatfor Xrect times negative one [Fig. 2b]. Those solution mapsgive specific values of six parameters mentioned above as afunction of Is and ω, all of which are scaled by a simplefunction of resonant inductance, resonant capacitance, and dcvoltages, as shown on the plot titles and axes labels of Fig. 2.The reason for choosing Is and ω as variables is that onlythose two parameters are shared by both the inverter [Fig. 1b]and the rectifier [Fig. 1c].
When a converter design is given, we calculate scalingfactors and turn general solution maps into specific solutionmaps that show necessary impedance and duty cycles for theinverter and the rectifier. Once we obtain specific solutionmaps for the given converter, we find the point (Is, ω) thatmakes Rload(Is, ω) equal to Rrect(Is, ω) and Xload(Is, ω)equal to Xrect(Is, ω) + ωLs − 1/ωCs. This is to match theimpedance the inverter needs to drive and the one presentedby the load branch, which is the LC filter connected in serieswith the rectifier. The found (Is, ω) is the point that achieveszero-voltage and zero-dv/dt switching for both the inverterand the rectifier. Then, we find dinv and drect that correspondto the (Is, ω) point on the specific solution maps derived fromFig. 2c.
Fig. 3 is used to find the rectifier output current. Similarto what we have explained for Fig. 2, we convert the plot tothe specific solution map by multiplying appropriate scalingfactors to horizontal and vertical axes, then read the outputcurrent value that corresponds to the found (Is, ω) point.
B. Calculation Example
In order to illustrate the calculation procedure outlinedabove, consider an example converter in structure of Fig. 1awith component values given in Table I. Fig. 4 illustrates thesteps for finding duty cycles and the frequency, which wedescribe in detail below.
First, obtain specific solution maps of Rload and Rrect as afunction of Is and ω. In order to do that, in Fig. 2a, scale the
10-2 10-1 100 101 102 103 104 105 106 107
Is√Lrect/Crect /Vout for the rectifier
Is√Linv/Cinv /Vin for the inverter
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
ω√ L r
ectC
rect
for t
he re
ctifi
erω√ L i
nvCinv
for t
he in
verte
r
Rrect/√Lrect/Crect for the rectifier
Rload/√Linv/Cinv for the inverter
10−9
10−7
10−5
10−3
10−1
101
103
(a)
10-2 10-1 100 101 102 103 104 105 106 107
Is√Lrect/Crect /Vout for the rectifier
Is√Linv/Cinv /Vin for the inverter
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
ω√ L r
ectC
rect
for t
he re
ctifi
erω√ L i
nvCinv
for t
he in
verte
r
Xrect/√Lrect/Crect for the rectifier
−Xload/√Linv/Cinv for the inverter
−10−11
−10−9
−10−7
−10−5
−10−3
−10−1
−101
−103
10−6
10−4
10−2
100
102
104
(b)
10-2 10-1 100 101 102 103 104 105 106 107
Is√Lrect/Crect /Vout for the rectifier
Is√Linv/Cinv /Vin for the inverter
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
ω√ L r
ectC
rect
for t
he re
ctifi
erω√ L i
nvCinv
for t
he in
verte
r
drect for the rectifierdinv for the inverter
0.00
0.15
0.30
0.45
0.60
0.75
0.90
1.05
(c)
Fig. 2. General solution maps of equivalent impedance and duty cycles forzero-voltage, zero-dv/dt switching. For the rectifier, solution maps describethe equivalent input impedance of the rectifier. For the inverter, these mapsdescribe the load impedance that the inverter needs to drive. (a) The equivalentresistance. (b) The equivalent reactance. (c) The switch duty cycle.
10-2 10-1 100 101 102 103 104 105 106 107
Is√Lrect/Crect /Vout for the rectifier
Is√Linv/Cinv /Vin for the inverter
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
ω√ L r
ectC
rect
for t
he re
ctifi
erω√ L i
nvCinv
for t
he in
verte
r
Iout√Lrect/Crect /Vout for the rectifier
Iin√Linv/Cinv /Vin for the inverter
10−5
10−3
10−1
101
103
105
107
109
Fig. 3. General solution map of the dc-dc converter output current. This plotis used to predict the output current of the dc-dc converter at the desiredoperating point (Is, ω).
horizontal axis by Vin/√Linv/Cinv = 2.24 A, the vertical
axis by 1/√LinvCinv = 2.24 × 107 rad/s, and multiply the
general solution map by√Linv/Cinv = 44.7 Ω to obtain
Fig. 4a, the specific solution map of Rload. Similarly for Rrect,scale Fig. 2a horizontally by Vout/
√Lrect/Crect = 1.58 A,
vertically by 1/√LrectCrect = 3.16× 107 rad/s, and multiply
the solution map by√Lrect/Crect = 31.6 Ω to obtain Fig. 4b.
Second, subtract Fig. 4b from Fig. 4a. The result is plottedin Fig. 4c. The curve on which Rload − Rrect equals to 0 isthe set of (Is, ω) that matches the resistance needed by theinverter and the resistance presented by the rectifier.
Third, obtain specific solution maps of Xload and Xrect
from Fig. 2b in a similar fashion as for Rload and Rrect.Results are shown in Fig. 4d and 4e. Note that the sign ofXload is the opposite of Fig. 2b.
Fourth, add (ωLs−1/ωCs) to Fig. 4e, and subtract it fromFig. 4d. The set of (Is, ω) that satisfies Xload−(Xrect+ωLs−1/ωCs) = 0 are points that equalize the reactance needed bythe inverter with that presented by the load branch.
Fifth, find the point that matches both the resistance andthe reactance between the inverter and the load branch asshown in Fig. 4g. In this example, Is of 3.856 A and ω of2π(4.903 MHz) is such a point.
Sixth, find the duty cycles. Obtain specific solution maps ofdinv and drect from Fig. 2c by a similar method described inthe first step. The results are in Fig. 4h and 4i. Read the valuesthat correspond to the point found in the fifth step. Here wefind dinv = 0.300 and drect = 0.456.
Lastly, find the output current by scaling Fig. 3 hori-zontally by 1.58 A and vertically by 3.16 × 107 rad/s asexplained in the first step, and multiplying the map by1.58 A, then finding the point that corresponds to (Is, ω) =(3.856 A, 2π(4.903 MHz)). The resulting output current is2.51 A.
Simulation confirms that zero-voltage and zero-dv/dtswitching occurs in both the inverter and the rectifier switcheswhen f = 4.903 MHz, dinv = 0.300, and drect = 0.475,which are in good agreement with the calculations. The reason
100 101 102 103 104
Is [Ahpp]
2.5
3.0
3.5
4.0
ω [×
107 ra
d/s]
Rload [Ω]
10−310−210−1100101102103104
(a)
100 101 102 103 104
Is [Ahpp]
2.5
3.0
3.5
4.0
ω [×
107 ra
d/s]
Rrect [Ω]
10−310−210−1100101102103104
(b)
100 101 102 103 104
Is [Ahpp]
2.5
3.0
3.5
4.0
ω [×
107 ra
d/s]
Rload −Rrect [Ω]
125100755025
0255075
(c)
100 101 102 103 104
Is [Ahpp]
2.5
3.0
3.5
4.0
ω [×
107 ra
d/s]
Xload [Ω]
10−410−310−210−1100101102103104
(d)
100 101 102 103 104
Is [Ahpp]
2.5
3.0
3.5
4.0ω
[×10
7 ra
d/s]
Xrect [Ω]−10−4
−10−3
−10−2
−10−1
−100
−101
−102
−103
−104
(e)
100 101 102 103 104
Is [Ahpp]
2.5
3.0
3.5
4.0
ω [×
107 ra
d/s]
Xload − (Xrect +ωLs − 1/ωCs) [Ω]
100755025
0255075100
(f)
100 101 102 103
Is [Ahpp]
2.5
3.0
3.5
4.0
ω [×
107 ra
d/s]
Rload −Rrect
= 0
Xload −(Xrect +ωLs−1/ωCs) = 0
(g)
100 101 102 103 104
Is [Ahpp]
2.5
3.0
3.5
4.0
ω [×
107 ra
d/s]
dinv
0.10.20.30.40.50.60.70.80.9
(h)
100 101 102 103 104
Is [Ahpp]
2.5
3.0
3.5
4.0
ω [×
107 ra
d/s]
drect
0.10.20.30.40.50.60.70.80.9
(i)
Fig. 4. Calculations steps to find duty cycles dinv , drect, and the frequency ω to achieve zero-voltage zero-dv/dt switching in both the inverter and therectifier. (a) Specific solution map of Rload obtained from Fig. 2a. (b) Specific solution map of Rrect obtained from Fig. 2a. (c) Rrect subtracted fromRload. The curve on which Rload − Rrect = 0 is where the resistance matches between the inverter and the rectifier. (d) Specific solution map of Xload
obtained from Fig. 2b. (e) Specific solution map of Xrect obtained from Fig. 2b. (f) Xrect + ωLs − 1/ωCs subtracted from Xload. The curve on whichthe result equals to zero is where the reactance matches between the inverter and the load branch. (g) Two curves extracted from Fig. 4c and 4f of which theintersection is marked by a red dot. This dot denotes Is and ω that achieve soft switching. (h) The point in Fig. 4g overlaid on the specific solution map ofdinv for the inverter duty cycle. (i) The point in Fig. 4g overlaid on the specific solution map of drect for the rectifier duty cycle.
TABLE IICOMPARISON OF CIRCUIT PARAMETERS PREDICTED BY THE
CALCULATIONS IN SUBSECTION II-B AND THOSE FOUND IN SIMULATION.
Calculation Simulation
Is 3.86 Ahpp 3.68 Ahppf 4.90 MHz 4.90 MHzdinv 0.30 0.30drect 0.46 0.48Iout 2.51 A 2.44 A
for the discrepancy is that in simulation Is is not perfectlysinusoidal. Table II summarizes the result. Fig. 5 showssimulated waveforms of the voltage across Q [Fig. 5a] andD [Fig. 5b].
III. EXPERIMENTAL VERIFICATION
A. Experimental Setup
We build a class-E dc-dc converter in a structure that uses aloosely coupled transformer [12]–[16] to verify the calculationmethod in section II. Although previous publications [13],[15], [16] describe various design methods, we find it con-venient to design the converter of such structure by followingthe transformation steps in Fig. 6 [23]. The transformationsteps are as follows: first, the conventional structure [Fig. 6a] isaltered so that the ac-ground connection bridges the converterinput and output nodes [Fig. 6b]; next, dc-blocking capacitorsare replaced by an ideal transformer [Fig. 6c]; then, the idealtransformer turn ratio is changed to n : m and parametersare adjusted accordingly [Fig. 6d]; lastly, the inductive two-port network within the dashed lines of Fig. 6d is replaced byan equivalent coupled inductor pair [Fig. 6e]. Because these
(a)
(b)
Fig. 5. Simulated waveforms of the voltage across the inverter switch Q andthe rectifier diode D of a converter in structure of Fig. 1a and with parametersin Simulation column, Table II. (a) Voltage across Q. (b) Voltage across D.
steps preserve equivalence of the circuit operation, designmethods and analyses developed for the conventional structureof Fig. 6a are directly applicable to the structure in use, Fig. 6e.
Compared to the equivalent circuit of the conventionaldesign, Fig. 6e has several advantages, including: input-outputgalvanic isolation; less number of components; more flexibilityin choosing the input-to-output voltage gain; and, in caseof using an air-core transformer, the relatively low couplingcoefficient that eases the implementation when the primaryand secondary inductances are different.
Fig. 7 describes the experimental setup. Fig. 7a and 7bare the schematic and picture of the implemented converter.Nonlinear junction capacitances of Q and D are denoted byCj,Q and Cj,D, which we assume to be 36 pF and 120 pF,respectively. Table III shows the implementation details of theconverter. Shown in Fig. 7c is the test equipment setup forthis experiment. A gate drive chip (SN74LVC1G17, TexasInstruments) receives the gate drive signal from an externalsignal generator and drives Q.
Compared to Fig. 6e, D and Crect in Fig. 7a are connectedto the output node instead of the ground node. This is becausethe diode we use has a thermal pad on the cathode side justas many other rectifier diodes. The configuration in Fig. 7aallows us to add a diode heat sink without its stray capacitanceinfluencing the circuit operation.
We design the converter to operate at switching frequenciesclose to 2 MHz because such frequency level has followingadvantages: first, 48 AWG litz wire becomes very effective inreducing the winding losses; second, 2 MHz is high enoughto implement air-core inductors and thus completely avoidcore losses; third, Cinv and Crect we need are significantlylarger than nonlinear Cj,Q and Cj,D, yielding an almost-linear resonant capacitance and thereby making the circuitoperation in line with the analysis in section II; and finally,2 MHz is slow enough to avoid the power losses of the GaNtransistor under high-dv/dt condition [24], namely when theapplied voltage stress is 100’s of volts peak-to-peak at 10’s of
TABLE IIIIMPLEMENTATION DETAILS OF THE CONVERTER IN FIG. 7B.
megahertz.In consideration of a high-frequency transformer
model [25], non-ideal behaviors of our transformer designthat can possibly have a significant effect on the converteroperation are interwinding capacitance and frequency-dependent winding resistance. Since our transformer isair-core, the core loss or saturation are guaranteed to benon-existent. The interwinding capacitance in our transformeris in the order of a few pF which is less than 1 % of theparallel-connected resonant capacitance Cinv and Crect.Frequency-dependence of the winding resistance from skineffect and proximity effect are taken into account in thesimulation-based analysis in Fig. 14, Fig. 15, and the relevanttext.
B.Duty Cycle and Frequency Modulation
We change Vin from 80 V to 200 V by a step of 40 V, andVout from 5 V to 9 V, 12 V, and 20 V. For each combinationof input and output voltages, we find the frequency and theduty cycle for the converter to achieve zero-voltage zero-dv/dtswitching, and compare them with the theoretical expecta-tions. In all comparisons between theoretical and experimentalresults, we suspect the differences are mostly attributed tothe voltage drop across the diode, series resistance of induc-tors, and the nonlinear junction capacitance of semiconductorswitches.
Fig. 8 and 9 plot the duty cycles of the inverter switch Qand the switching frequencies, respectively, at different inputand output voltages. In both figures, when the input-to-outputvoltage gain increases (toward the top left of figures) theswitching frequency does too, while the duty cycle decreases.
By modulating the duty cycle and the switching frequency,we achieve the desired soft switching conditions throughoutall experiments. As an example, we show in Fig. 10 theexperimental waveforms of the voltage across Q [Fig. 10a]and D [Fig. 10b] when we fix Vout to 12 V and change Vinfrom 80 V to 200 V while modulating the duty cycle andfrequency as indicated in Fig. 8 and 9.
Class-E inverter Class-E rectifier
Lser
dc blocking cap
Linv Lrect
Cinv Crect
VoutVin
QD
(a)
Lser
dc blocking cap
Linv
Cinv
Vin
Lrect
Crect
Vout
QD
(b)
ideal1:1
LserLinv
Cinv
Vin
Lrect
Crect
Vout
QD
(c)
idealn:m
n2Lsern
2Linv
Cinv/n2nVin
m2Lrect
Crect/m2mVout
QD
(d)
Crect/m2mVout
Lp Ls
k
Cinv/n2nVin
QD
(e)
Fig. 6. Transformation steps of the isolated resonant dc-dc converter consisting of a class-E inverter and a class-E rectifier. Because those steps preserveequivalence of the circuit operation, design methods and analyses developed for the conventional structure are directly applicable to any other structures inthe transformation steps. (a) The first step shows the conventional structure. (b) The second step is where the ac-ground connection is relocated. (c) The thirdstep is where dc blocking capacitors are replaced by an ideal transformer. (d) In the fourth step, the ideal transformer turn ratio is changed to n : m andparameters are adjusted accordingly. (e) In the final step, the inductive two-port network within the dashed lines is replaced by an equivalent coupled inductorpair.
C. Output Current and Regulation
Continuous output currents are plotted in Fig. 11. Due tothe lack of design freedom, it is impossible to make the outputcurrent deviate from the values of Fig. 11 without giving upzero-voltage or zero-dv/dt switchings and without changingthe input or output voltages. As experimentally demonstratedin [12] and [13], a proper control strategy such as on-offcontrol should be used to cope with load variations at giveninput and output voltages.
Fig. 12a depicts the measured dc-dc efficiency for differentoutput powers when we try on-off control to regulate the
output voltage. The output power of the converter can beadjusted from the maximum level under continuous operation(indicated by filled markers) down to near-zero power levelunder on-off control scheme (indicated by hollow markers) atthe expense of degraded efficiency and increased input andoutput voltage ripple. Designers should choose parameters ofthe converter so that the maximum output power they need issmaller than or equal to the output power under continuousconverter operation. We show the concept schematic of theclosed-loop controller and the auxiliary circuitry in Fig. 12b,but without implementation. Should anyone interested in build-
Cinv
VinCrect
Lp Ls
k
Q
D
Cin
+
Vout
Cout
+
dinv, ω
Iout
(a)
Lp
Cinv
Crect
gatesig.
Ls
Q
D
Cout
Cin
Vin
Vout
gatebuffer
(b)
signalgen.
electronicload
oscilloscope
6V gate sig.power supply
Vin power supply
dc-dcconverter
thermalcamera
(c)
Fig. 7. Experimental setup to verify the calculation method in section II. (a)The schematic of the class-E dc-dc converter. (b) The implemented converter.(c) The test equipment setup.
ing one, the shown schematic can be one possible way to carryout the task.
D. Efficiency Variation
The efficiency of the converter changes when the duty cycleand the frequency are adjusted for different input and outputvoltages. As shown in Fig. 13, the efficiency decreases withincreasing input-to-output voltage gain both in simulations[Fig. 13a] and experiments [Fig. 13b]. Experimental efficiencyincludes 0.024 W gate buffer power drawn from the 6 V
5 V 9 V 12 V 20 VVout
80 V
120 V
160 V
200 V
Vin
0.096 0.132 0.151
0.082 0.107 0.123 0.159
0.076 0.087 0.107 0.139
0.085 0.096 0.123dinv, theoretical
0.08
0.10
0.12
0.14
0.16
0.18
(a)
5 V 9 V 12 V 20 VVout
80 V
120 V
160 V
200 V
Vin
0.11 0.14 0.18
0.10 0.12 0.14 0.16
0.09 0.10 0.12 0.13
0.09 0.11 0.12dinv, experimental
0.08
0.10
0.12
0.14
0.16
0.18
(b)
Fig. 8. Duty cycles of the inverter switch Q for zero-voltage zero-dv/dtswitching at different input and output voltages. (a) Theoretical (b) Experi-mental
5 V 9 V 12 V 20 VVout
80 V
120 V
160 V
200 V
Vin
2.06 2.02 1.98
2.06 2.05 2.04 1.96
2.06 2.06 2.05 2.01
2.06 2.06 2.04
switching freq. [MHz], theoretical
1.90 MHz
1.95 MHz
2.00 MHz
2.05 MHz
2.10 MHz
(a)
5 V 9 V 12 V 20 VVout
80 V
120 V
160 V
200 V
Vin
2.06 2.02 1.97
2.07 2.06 2.04 1.94
2.08 2.07 2.06 2.00
2.08 2.06 2.03
switching freq. [MHz], experimental
1.90 MHz
1.95 MHz
2.00 MHz
2.05 MHz
2.10 MHz
(b)
Fig. 9. Switching frequencies for zero-voltage zero-dv/dt switching atdifferent input and output voltages. (a) Theoretical (b) Experimental
0 V
100 V
200 V
300 V
400 V
500 V
0.0 μs 0.2 μs 0.4 μs 0.6 μs 0.8 μs 1.0 μs
Vin = 80 V
Vin = 120 V
Vin = 160 V
Vin = 200 V
(a)
-50 V
-40 V
-30 V
-20 V
-10 V
0 V
10 V
20 V
0.0 μs 0.2 μs 0.4 μs 0.6 μs 0.8 μs 1.0 μs
Vin = 80 V
Vin = 120 V
Vin = 160 V
Vin = 200 V
(b)
Fig. 10. Experimental waveforms of the voltage across semiconductor deviceswhen we fix Vout to 12 V and change Vin from 80 V to 200 V whilemodulating the duty cycle and frequency as indicated in Fig. 8 and 9. (a) Thevoltage across the inverter transistor Q. (b) The voltage across the rectifierdiode D.
5 V 9 V 12 V 20 VVout
80 V
120 V
160 V
200 V
Vin
1.43 1.54 1.52
2.13 2.22 2.25 2.26
2.84 2.77 2.96 3.06
3.59 3.53 3.75output current [A], theoretical
1.5 A
2.0 A
2.5 A
3.0 A
3.5 A
4.0 A
(a)
5 V 9 V 12 V 20 VVout
80 V
120 V
160 V
200 V
Vin
1.48 1.52 1.55
2.17 2.18 2.23 2.43
2.84 2.90 2.94 3.30
3.55 3.74 4.04output current [A], experimental
1.5 A
2.0 A
2.5 A
3.0 A
3.5 A
4.0 A
(b)
Fig. 11. Output current variation when duty cycle and frequency aremodulated as in Fig. 8 and 9. (a) Theoretical (b) Experimental
30 %
40 %
50 %
60 %
70 %
80 %
90 %
0 W 5 W 10 W 15 W 20 W
effi
cien
cy
output power
80V to 12V
80V to 9V
80V to 5V
continuous
on-off controlled
(a)
Cinv
VinCrect
Lp Ls
k
Q
D
Cin+
Vout
Cout
+
isolation
amplifier
controller
Vout selection bits
on-off control, d-f modulation
gate driving signal
ADC ADC
digital in
(b)
Fig. 12. Experimental demonstration of on-off control and a possible closed-loop controller design. (a) Experimental efficiency versus output power whenthe output voltage is regulated by on-off control. (b) Concept schematic of aclosed-loop controller and auxiliary circuitry.
external power supply, and excludes the power consumptionof the signal generator.
We simulate the dc-dc converter in order to estimate howmuch efficiency drops are caused by each circuit componentsin Fig. 7a. For Q, we use the manufacturer-provided SPICEmodel for power loss estimation [26]. For D, losses aresimulated by a constant forward voltage drop of 0.5 V andon-resistance of 0.02 Ω to fit the I-V curve for 25 C inthe datasheet [27]. Capacitors Cin, Cinv , Crect, and Coutare assumed lossless. For Lp and Ls, we should model theresistance that increases with frequency due to dielectric lossesand skin effect. We measure the resistance-versus-frequencycurve of Lp and Ls, then construct an inductor model withan RL network [Fig. 14] of which the resistance profilefits the measured curve. The constructed circuits emulate thefrequency-dependent resistance within ±15 percent accuracy
5 V 9 V 12 V 20 VVout
80 V
120 V
160 V
200 VVin
80.8 87.7 90.0
77.1 85.5 88.3 91.5
74.3 83.1 86.4 90.4
81.3 84.4 89.3efficiency [%], simulated
70 %
75 %
80 %
85 %
90 %
(a)
5 V 9 V 12 V 20 VVout
80 V
120 V
160 V
200 V
Vin
78.5 85.5 87.7
73.7 82.6 85.5 89.0
69.9 79.5 83.1 87.3
77.1 80.6 85.5efficiency [%], experimental
70 %
75 %
80 %
85 %
90 %
(b)
Fig. 13. Converter efficiency at different input and output voltages. Exper-imental efficiency includes the gate buffer power drawn from the externalpower supply, and excludes the power consumption of the signal generator.(a) Simulated. (b) Experimental.
up to the third harmonic of the switching frequency, andare used in place of Lp and Ls for the simulation. Dutycycles and switching frequencies for the simulation follow theexperimental values in Fig. 9b and Fig. 8b, respectively.
Fig. 15 shows the simulation results. Efficiency drops aremainly attributed to the loss in the primary transformer wind-ing Lp and the diode D. Lp and D degrade the efficiency byas much as 12.6 % and 9.3 %, respectively, while other twocomponents are not as significant in terms of their impact.Diode losses shows a tendency to increase only with Voutbecause most of the losses are caused by the diode forwardvoltage drop.
Thermal measurements in Fig. 16 agree with the simulatedpower loss breakdown in Fig. 15. Fig. 16a is the thermal imagewhen Vin is 80 V and Vout is 12 V, in which D is slightlyhotter than Lp. When Vin changes to 200 V while Vout remainsthe same at 12 V, Fig. 16b shows Lp becoming noticeablyhotter than D. This is in accordance with the simulated lossbreakdown, in which Lp has a similar loss as D in the formercase and twice as much loss than D in the latter case.
E. Synchronous Rectification
To eliminate the diode loss and improve the efficiency, webuild a converter with synchronous rectification and compareit to the converter above. Fig. 17 shows the schematic and the
Lp or Ls RdcLfit
Rfit
Fig. 14. An inductor with an RL network to emulate the series resistancethat increases with frequency due to dielectric and skin-effect losses. We usethis circuit in place of Lp and Ls while simulating the converter in Fig. 7ato estimate inductor losses.
TABLE IVIMPLEMENTATION DETAILS OF THE CONVERTER IN FIG. 17.
Qinv GS66502B GaN transistorQrect EPC2033 GaN transistorCin 0.2 µF X7R cap.Cout 0.3 µF X7R cap.Cj,Qinv 36 pF approx. of nonlin. cap.Cj,Qrect 720 pF approx. of nonlin. cap.
implementation of the circuit. Cj,Qinv and Cj,Qrect denote thenonlinear junction capacitance of Qinv and Qrect, respectively.Table IV gives the implementation details. As in the previoussection, the gate drive signal is provided by an external signalgenerator.
We fix Vin at 80 V and change Vout from 5 V to 9 V and12 V. When we modulate the frequency and duty cycles asin Table V, both the inverter- and the rectifier-side transistorsachieve zero-voltage zero-dv/dt switching as can be seen inFig. 18.
Fig. 19 verifies the effectiveness of synchronous rectifica-tion in reducing the rectifier loss and thereby boosting theefficiency. Thermal images in Fig. 19a demonstrate that thetemperature of Qrect is significantly reduced when comparedwith Fig. 16a, and hence the power loss. The peak efficiencyis 92.3 % when Vout is 12 V.
IV. CONCLUSION
The duty cycle and frequency modulations presented hereachieve zero-voltage zero-dv/dt switching in a class-E dc-dc converter to retain high efficiency under a wide range ofinput and output voltage conditions. The duty cycle, frequency,
TABLE VOPERATING CONDITIONS OF THE CONVERTER WITH SYNCHRONOUS
RECTIFICATION WHEN Vin = 80 V AND Vout = 5, 9, 12 V.
Vout dinv drect freq. Iout
5 V 0.20 0.60 2.44 MHz 2.62 A9 V 0.22 0.55 2.34 MHz 2.80 A
12 V 0.25 0.52 2.20 MHz 2.24 A
5 V 9 V 12 V 20 VVout
80 V
120 V
160 V
200 VVin
1.0 0.8 0.8
1.4 0.8 0.7 1.0
1.3 1.0 0.8 1.0
0.9 1.2 1.0efficiency drop by Q [%], simulated
0.0 %
2.5 %
5.0 %
7.5 %
10.0 %
12.5 %
15.0 %
(a)
5 V 9 V 12 V 20 VVout
80 V
120 V
160 V
200 V
Vin
7.1 4.4 3.5
10.0 6.3 4.9 3.3
12.6 8.1 6.3 4.2
9.7 7.8 5.1efficiency drop by Lp [%], simulated
0.0 %
2.5 %
5.0 %
7.5 %
10.0 %
12.5 %
15.0 %
(b)
5 V 9 V 12 V 20 VVout
80 V
120 V
160 V
200 V
Vin
1.9 1.5 1.4
2.2 1.7 1.6 1.4
2.6 2.0 1.8 1.5
2.2 1.9 1.6efficiency drop by Ls [%], simulated
0.0 %
2.5 %
5.0 %
7.5 %
10.0 %
12.5 %
15.0 %
(c)
5 V 9 V 12 V 20 VVout
80 V
120 V
160 V
200 V
Vin
9.2 5.6 4.4
9.2 5.8 4.5 2.9
9.3 5.9 4.6 3.0
6.0 4.7 3.1efficiency drop by D [%], simulated
0.0 %
2.5 %
5.0 %
7.5 %
10.0 %
12.5 %
15.0 %
(d)
Fig. 15. Simulated efficiency drops caused by (a) the inverter transistor Q; (b)the primary winding Lp; (c) the secondary winding Ls; and (d) the rectifierdiode D.
ambience :22 °C
D :47.7 °C
Lp :40.6 °C
(a)
ambience :22 °C
D :105.4 °C
Lp :127.8 °C
(b)
Fig. 16. Thermal images of the converter at thermal equilibrium. Temperaturesof Lp and D agree with the simulated loss breakdown in Fig. 15. (a) Thermalimage when Vin = 80 V and Vout = 12 V, in which the loss breakdownpredicts similar loss levels in Lp and D. (b) Thermal image when Vin =200 V and Vout = 12 V, in which the loss breakdown predicts twice as muchloss in Lp than in D.
and the expected output current can be calculated by afew simple mathematical operations that use predeterminedgeneral solution maps. We built a prototype converter in astructure that uses a loosely coupled transformer for simplicity,isolation, and high efficiency. We suggested equivalent circuittransformation steps to design such a converter. Theoreti-cally calculated duty cycle and frequency for soft switchingmatched well with the experimental data. We experimentallydemonstrated the on-off control scheme for output voltageregulation and suggested a concept schematic of the controllerand the peripheral circuitry. We identified the transformer andthe rectifier diode as a major contributor to the power loss,and improved the performance by implementing synchronousrectification to achieve 92.3 % peak efficiency.
ACKNOWLEDGMENT
We thank Huawei for funding this work through the En-ergy/Power Management Systems focus area of Stanford Sys-temX Alliance.
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Cinv
Vin
Crect
Lp Ls
k
Qinv
Cin+
Vout
Cout+
QrectCj,Qinv Cj,Qrect
Iout
(a)
Ls
CinvCrect
inverter gatesignal
Lp
Qinv
Cout
Cin
Vin
Vout
Qrect
rectifier gatesignal
(b)
Fig. 17. The class-E dc-dc converter with synchronous rectification. (a) Theschematic. (b) The implementation.
0 V
50 V
100 V
150 V
200 V
250 V
0.0 μs 0.2 μs 0.4 μs 0.6 μs 0.8 μs 1.0 μs
Vout = 5 V
Vout = 9 VVout = 12 V
(a)
0 V
10 V
20 V
30 V
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60 V
0.0 μs 0.2 μs 0.4 μs 0.6 μs 0.8 μs 1.0 μs
Vout = 5 V
Vout = 9 V
Vout = 12 V
(b)
Fig. 18. Experimental waveforms of the voltage across the inverter- and therectifier-side transistors when Vin = 80 V and Vout = 5, 9, 12 V. (a) Thevoltage across Qinv (b) The voltage across Qrect
ambience :22 °C
Qrect :36.1 °C
Lp :45.5 °C
Qinv :33.9 °C
(a)
80 %
85 %
90 %
95 %
100 %
4V 5V 6V 7V 8V 9V 12Vef
fici
ency
Vout
92.3 %91.2 %
87.4 %
(b)
Fig. 19. Experimental results of the converter with synchronous rectification.(a) A thermal image that shows the reduced power loss in the rectifier-sideswitch when Vin = 80 V and Vout = 12 V. The image demonstrates a clearimprovement when compared with Fig. 16a. Lp shows a higher temperaturebecause this converter processes higher power, namely 26.9 W versus 18.6 Win the output. (b) Efficiency of the converter with synchronous rectification.The peak efficiency is 92.3 % when Vout is 12 V.
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APPENDIX ADERIVATIONS OF GENERAL SOLUTION MAPS IN FIG. 2 AND
FIG. 3
This section derives general solution maps for a class-Etopology as a function of two design variables, namely, thenormalized switching frequency ωn and the switch duty cycled. The derivation resembles those published in [17]–[19].
Consider a class-E rectifier [Fig. 20a] of which the capacitorvoltage vc(t) and the sinusoidal input current is(t) followperiodic waveforms depicted in Fig. 20b. We define parametersas listed below:
• d = drect, L = Lrect, C = Crect• ωn = ω
√LC
• θ = ωt
Lrect
Crect
Vout
Dis(t)
drect, ω
Rrect + jXrect
vc(t) iL(t)
Iout=〈iL(t)〉
(a)
θ = ωt
vc(θ)
is(θ)
D
ON
D
OFF
Is
2π
Φ Is
D
OFF
2π (1 d )
θ = ωt
(b)
Fig. 20. The class-E rectifier schematic and relevant waveforms for solutionmap derivations. (a) The rectifier schematic. (b) Waveforms of the capacitorvoltage vc(t) and the sinusoidal input current is(t) over one cycle of theperiodic operation.
• Is,n = Is√L/C/Vout
• Idc,n = Iout√L/C/Vout
• Rn = Rrect/√L/C = Rrect · (Is/Vout)/Is,n
• Xn = Xrect/√L/C = Xrect · (Is/Vout)/Is,n.
Analytical equations for is(t), vc(t), and the inductor currentiL(t) are described as follows:
is(θ) = Is sin(θ − Φ) (1)
vc(θ) =
Vout
(A sin ( θ
ωn+ φ) + (
Is,nωn
1−ωn2 ) cos (θ − Φ) + 1
),
if 0 < θ ≤ 2π(1− d)
0,
if 2π(1− d) < θ ≤ 2π(2)
iL(θ) =
Vout√L/C
(A cos ( θ
ωn+ φ) +
Is,n1−ωn
2 sin (θ − Φ)
),
if 0 < θ ≤ 2π(1− d)
iL(2π(1− d))− Vout
ωL (θ − 2π(1− d)),
if 2π(1− d) < θ ≤ 2π(3)
where L, C, and Vout are given constants, wn and d arevariables, and A, φ, Is,n, and Φ are unknowns. We needfour conditions in order to determine four unknowns. The firstcondition to be met is the zero-voltage turn-off:
vc(0) = 0. (4)
The second and third are from the zero-dv/dt turn-off:
is(0) = iL(0) (5)
is(2π) = iL(2π). (6)
The last condition is from the zero-voltage turn-on:
vc(2π(1− d)) = 0. (7)
We use (4), (5), (6), and (7) to analytically solve for unknownsin (1), (2), and (3). Plotting Is,n, one of four unknowns, asa function of ωn and d yields the general solution map inFig. 21a. Calculating the time average of iL(θ) described in(3) and plotting it gives us the map in Fig. 21b.
We find Rn and Xn by calculating the fundamental Fouriercoefficient vc(θ) and dividing it by that of is(θ) as shownbelow:
vc,1 =1
2π
∫ 2π
0
vc(θ)e−jθdθ = Voutf (8)
is,1 = Ise−jΦ (9)
Rn+ jXn =
(1√L/C
)vc,1
is,1=
(Is/VoutIs,n
)vc,1
is,1=
f
Is,ne−jΦ
(10)in which f , Is,n and Φ are all a function of wn and d. Plugging(2) into (8) and performing the calculation in (10), we obtainthe plots in Fig. 21c and Fig. 21d.
Fig. 21a reveals that designating the value of Is,n and ωnis enough to uniquely determine every different point on the(d, ωn) plane. We use this property to reconstruct Fig. 21a as afunction of Is,n and ωn and thereby obtain Fig. 2c. Using Is,nvalues that correspond to each (d, ωn) points in Fig. 21a, werearrange the solution fields of Fig. 21 onto the new mappingwith respect to Is,n and ωn, thereby obtaining plots in Fig. 2and Fig. 3.
For a class-E inverter [Fig. 1b], same equations and deriva-tion process apply when we use the following parameterdefinitions instead:
• d = dinv , L = Linv , C = Cinv• Is,n = Is
√L/C/Vin
• Idc,n = Iin√L/C/Vin
• Rn = Rload/√Linv/Cinv
• Xn = −Xload/√Linv/Cinv
The sign of Xn is changed to negative and all the voltage andcurrent waveforms are flipped horizontally because the inverteroperation is time-reversal of the rectifier operation [21], [22].
APPENDIX BPYTHON CODE THAT CALCULATES GENERAL SOLUTION
MAPS OF A CLASS-E TOPOLOGY
import numpy as npfrom numpy import sin, cos, pi, sqrtimport matplotlib.pyplot as pltfrom matplotlib import ticker, cm
####### class-E rectifier solution #######
numstep_d = 100numstep_wn = 100
0.2 0.4 0.6 0.8d
0.60.81.01.21.41.61.82.0
ωn
Is, n
10-4
10-2
100
102
104
106
108
(a)
0.2 0.4 0.6 0.8d
0.60.81.01.21.41.61.82.0
ωn
Idc, n
10-5
10-3
10-1
101
103
105
107
109
(b)
0.2 0.4 0.6 0.8d
0.60.81.01.21.41.61.82.0
ωn
Rn
10-9
10-7
10-5
10-3
10-1
101
103
(c)
0.2 0.4 0.6 0.8d
0.60.81.01.21.41.61.82.0
ωn
Xn −10−11
−10−9
−10−7
−10−5
−10−3
−10−1
−101
−103
10−6
10−4
10−2
100
102
104
(d)
Fig. 21. General solution maps of a class-E topology derived in Appendix A.The derivation follows a similar manner as that in previous works [17]–[19].(a) The normalized sinusoidal ac current. Variables here are circuit parametersnormalized by the dc voltage, resonant inductance and capacitance. (b) Thenormalized dc current. (c) The equivalent resistance. (d) The equivalentreactance.
