- DSP for Space Applications
FP7 Workshop – Space Foundations
Rome, May 29th, 2012
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Summary
European Space DSP Issue
Project
Consortium
Architecture
System on Chip
Target Performance
Demonstrator Board
Processor Design Flow
Software Development Environment
Benchmarks
Conclusions and next steps
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European Space DSP Issue
Atmel TSC21020 The only European DSP
Pros
• No ITAR restrictions
Cons
• Slow (40 MFLOPS)
• Obsolete
• Not compliant with
needs of modern space
missions
US-made
alternatives Pros
• Good performances
Cons
• ITAR restrictions
EC-ESA-EDA directives for
next space technologies
development:
• Independence:
european development
of space technologies
• Non-dependence:
availability of any
required space
technology
Key requirements for next generation space DSP:
• Processing power ≥ 1 GFLOPS
• Radiation hardness (TID > 100 Krad) and protected memories (EDAC)
• Space standard I/O interfaces
• High quality SW Development Environment
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DSPACE Project
Aim
Development of IP Core for new high performance european DSP:
• 1 GFLOP@125 MHz
• FPGA/ASIC (0.18 μm technology)
• Scalable stand-alone processor or embedded HW accelerator
• Complete and Mature «friendly programmable» SDE
• No ITAR restrictions
Context
• Funding scheme: European Community's Seventh Framework Programme ([FP7/2007-2013])
• Project Duration: 2 Years July 2011 – July 2013
• Project Total Budget: 1.6 M€
• International Consortium of 5 partners.
Applications
• Earth Observation missions (e.g. processing of IR sounder and SAR instruments data)
• Science and Robotic Exploration missions (e.g. optical navigation for descent and landing;
camera image compression)
• Telecom applications
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DSPACE Consortium
PROJECT COORDINATOR
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SITAEL S.p.A.
Role in DSPACE project
Project Coordinator DSP architecture selection - Design of VHDL DSP core Development of DSPACE prototypes and validation of project outcomes
Contact: Mr. Giuseppe Piscopiello [email protected]
SITAEL S.p.A. Overview
SITAEL is an Italian Medium Enterprise specialized in design, development, production and qualification of Instruments, Electronics and Microelectronics Systems for a wide range of High Reliability Applications, from Ground to Space. Counting on 130 high qualified employees and state-of-the-art facilities in Apulia and Tuscany regions, SITAEL is able to manage all stages of the production, offering turn-key highly safe and reliable solutions, according to ESA/NASA Standards. SITAEL has successfully taken part in many International Projects (SENTINEL 3, SWARM, INTEGRAL, MSL-Curiosity, PAMELA, AMS-01/AMS-02, GAIA, ATV) and is currently involved in other International Programmes (SENTINEL 1, COSMO Skymed 2nd generation, EarthCARE, ICESat-2, ASTRO-H, CALET, ExoMARS) in collaboration with the main Space Players (ESA, NASA, CNES, JAXA, ASI, Thales Alenia Space, EADS Astrium, OHB, Selex Galileo, COM DEV, RSC Energia.)
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INTECS S.p.A.
Role in DSPACE project
SDE integration of the code optimiser Software test planning, execution and validation
Contact: Ms Elena Cordiviola [email protected]
INTECS S.p.A. Overview
INTECS which was founded in 1974, is at the forefront in the design and implementation of high-tech electronic systems for the Aerospace, Defense, Transportation, and Telecommunication markets, where safety, reliability, innovation, and quality are the key ingredients for success. INTECS is an Italian private company employing circa 700 professionals. Its headquarter is in Rome, while other sites are located in Pisa, Naples, Milan, Turin, Cagliari, Genoa, L’Aquila, Paris and Toulouse. INTECS designs and develops applications, tools, software, and hardware components for advanced electronic systems in cooperation with major European and Italian Industries, Organizations, Universities, and Research Centers. INTECS has always placed great emphasis and commitment in Research and Development activities which range over multiple sectors like Software Engineering (CHESS, ASSERT, HRT-UML and PRIDE), Earth Observation and GIS (GENESIS, ORCHESTRA), Communications (SANDRA, IPERMOB) and others.
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Consorzio Pisa Ricerche Scarl
Role in DSPACE project
DSP architecture selection Contribution to VHDL design and validation Coordination of dissemination and exploitation activities
Contact: Mr Luca Fanucci [email protected]
Consorzio Pisa Ricerche Scarl Overview
Consorzio Pisa Ricerche (CPR) is an italian leading organization in the research and technology development and technology transfer sectors whose main mission is to strengthen the connection between research environment and industry. CPR operates in highly competitive and fast moving fields: Information and Communication Technologies, Electronic Systems and Microelectronics, Energy and Environment, Structural engineering, Industrial Technologies. The Electronic Systems and Microelectronics division (CPR-TEAM) employs highly qualified and skilled professionals with competence in design and verification of ICs and HW/SW embedded systems and development of electronic systems based on microcontroller, FPGA and DSP technologies. CPR-TEAM develops projects for industrial customers as well as participates with Research Centers and Industry partners in applied research projects, in the framework of Italian and European programmes or tenders by Government Institutions and Agencies.
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Space Applications Services N.V./S.A.
Role in DSPACE project
Selection and specification of benchmarks Benchmarks implementation DSP performance evaluation
Contact: Mr Frederic Reiter [email protected]
Space Applications Services N.V./S.A. Overview
Space Applications Services (SA) is an independent Belgian company founded in 1987, with a subsidiary in Houston, USA. Our aim is to develop innovative systems, solutions and products and provide services to the aerospace and security markets and related industries: • Design, develop and integrate, mission critical systems, ground segments, command and control
centres and scientific payloads. • Research, design and develop specific technology solutions which may be used stand alone or
integrated within an overall system. • Operate facilities and command and control centres and train persons to perform operations. Its activities cover manned and unmanned spacecraft, launch/re-entry vehicles, robotics, air traffic management and a wide range of information systems.
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RWTH Aachen University
Role in DSPACE project
LISA DSPACE IP Core Modelling Analysis of architectural/benchmarking requirements Development of software tools (code optimiser)
Contact: Mr Rainer Leupers [email protected]
RWTH Aachen University Overview
RWTH Aachen University, Germany, is an internationally top-ranked technical university with around 30,000 students and is a member of the IDEA league. Its Institute for Communication Technologies and Embedded Systems (ICE) performs research and development in different areas of embedded system design technology, especially covering algorithms, architectures, and tools for wireless communication systems. ICE maintains tight cooperations with semiconductor vendors, system houses, and EDA companies, and frequently provides industrial consulting. ICE receives funds from the Deutsche Forschungsgemeinsschaft (DFG). Further funding is received from EU FP7 projects like EUROTILE and HiPEAC, as well as from industry partners like Siemens, Nokia, Infineon, Huawei, ACE, and Tokyo Electron. Many R&D projects at ICE have contributed to the development of industrial products. Moreover, several successful EDA spin-off originated from the ICE, e.g. Cadis (acquired by Synopsys), Axys (acquired by ARM), and LISATek (acquired by CoWare and later Synopsys).
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DSPACE Architecture
• 8-issues VLIW architecture
• Clustered architecture: 2
identical data paths
• 64 32-bit registers
• 8 functional units:
4 ALUs
2 MUL units
2 AGUs (address
generation unit)
• Conditional execution of all
instructions
• Data formats:
32-bit fixed-point
32-bit (IEEE 754 single
precision) floating-point
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DSPACE System On Chip
SRAM,
SDRAM,
DDRAM,
EEPROM
2 SpW interfaces
for high-speed
connectivity
Memory Controller
interfaces with
external SRAM,
SDRAM, DDRAM,
EEPROM;
Includes EDAC
I-Cache: 32KB
with EDAC
DMA Controller:
moves data
between caches
and off-chip
memory
D-Cache: 64 KB
with EDAC
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DSPACE Target Performance
Atmel ATC18RHA
• Available
• Space Qualified
• 180 nm ASIC Technology
ST Microelectronics DSM65
• Available in near future
• Space Qualified
• 65 nm ASIC Technology
DSP target performance
750 MFLOPS (peak)
@ 125 MHz
DSP target performance
> 1 GFLOP
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DSPACE Demonstrator Board
SRAM
SRAM
SRAM
SRAM
DDRAM
DDRAM
DDRAM
DDRAMXilinxFPGA
Power Supply
FLASH
SRAM
MIL1553
SpW
USB/ETH to Serial
Co
mp
act-
PC
I
CAN Bus
PRELIMINARY BOARD LAYOUT Candidate FPGA
Xilinx Virtex5 FPGA (XC5VLX110)
• Equivalent ground version of
space qualified “Virtex5-QV
XQR5VFX130”
• Expected DSP clock rate 40
80 MHz
• Rad-hard design implemented
Standard
Compact PCI 3U, 2Slots
For C-PCI crates As stand-alone desktop board
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DSPACE Processor Design Flow
LISA Architecture Description Language (ADL)
High-level abstraction processor modeling
LISA Architecture Description Language (ADL)
Automatic generation of SW tools (assembler, linker,
simulator)
LISA Architecture Description Language (ADL)
Automatic generation of VHDL Code
ADVANTAGES • Shortening of development time
• Improving of generated SW tools and HW
consistency
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DSPACE SW Development Environment
Reuse of GCC C compiler output
Performed by means of Glue Software and
Code Optimizer
Glue Software
Translation to DSPACE Linear Assembly language
Code Optimizer
Register allocation, scheduling and optimisations
Assembler, Linker and Debugger
Generated by LISA SW tools
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DSPACE Benchmarks
Adoption of ESA DSP SW benchmarks specification
“Next Generation Space Digital Signal Processor Software Benchmark,TEC-EDP/2008.18/RT,
December 2008”
• Application-oriented
benchmarks
• Main kernel algorithms:
FIR filters (code developed
in C and Assembly)
FFTs (code developed in C
and Assembly)
Standard CCSDS Lossless
Data Compression
Image Data Compression
• Execution for performance
measurement on:
Cycle Accurate Simulator
FPGA demonstrator
Conditional execution of
all instructions
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Conclusions and Next Steps
PROJECT STATUS
• DSP architectural design complete
• first VHDL model of DPU core available
• SW Development Environment under construction
ACTUAL OUTPUTS
• DSPACE DSP is a VLIW floating-point DSP
• target performance is 1 GFLOPS with the latest space ASIC technologies
• rad-hard by design and space-standard interfaces
NEXT STEPS
• Completion of SoC processor VHDL development
• Demonstrator board design and production
• SDE Integration
• HW and SW testing and validation
• Benchmarks performance evaluation
• Beta Testing investigation
SITAEL S.p.A. S. P. 231, KM. 79.900 - 70026 Modugno (BA)
Via Livornese 1019 - 56122 Pisa (PI)
ITALY
www.sitael.com
Thank you for your
attention!
Giovanni Tuccio Sales and Marketing Manager
phone: +39 050 99 12 116
e-mail: [email protected]