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“Memory Management Function”
Presented By
Lect. Rimple Bala
GPC,Amritsar
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Contents
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Basic memory management Swapping Virtual memory Paging Page replacement algorithms Modeling page replacement algorithms Design issues for paging systems Implementation issues Segmentation
Memory Management Memory – a linear array of bytes
Holds O.S. and programs (processes)Each cell (byte) is named by a unique memory address
Recall, processes are defined by an address space, consisting of text, data, and stack regions
Process executionCPU fetches instructions from the text region
according to the value of the program counter (PC)Each instruction may request additional operands from
the data or stack region
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Memory Management Ideally programmers want memory that is
largefastnon volatile
Memory hierarchy small amount of fast, expensive memory – cache some medium-speed, medium price main memorygigabytes of slow, cheap disk storage
Memory manager handles the memory hierarchy
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Multiprogramming with Fixed Partitions
Fixed memory partitionsseparate input queues for each partitionsingle input queue
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Modeling Multiprogramming
CPU utilization as a function of number of processes in memory
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Degree of multiprogramming
Names and Binding
Symbolic names Logical names Physical names○ Symbolic Names: known in a context or path
file names, program names, printer/device names, user names
○ Logical Names: used to label a specific entity job number, major/minor device numbers, process id (pid), uid.
○ Physical Names: address of entityinode address on disk or memoryentry point or variable addressPCB address
Address Binding Address binding
fixing a physical address to the logical address of a process’ address space
Compile time bindingif program location is fixed and known ahead of time
Load time bindingif program location in memory is unknown until run-time
AND location is fixed
Execution time bindingif processes can be moved in memory during executionRequires hardware support
P: : push ... jmp 175 :
foo: ...
0
100
175
LibraryRoutines
P: : push ... jmp 1175 :
foo: ...
1000
1100
1175
LibraryRoutines
P: : push ... jmp 1175 :
foo: ...
1000
1100
1175
LibraryRoutines
P: : push ... jmp 175 :
foo: ...
0
100
175
LibraryRoutines
1000
Base register
Execution Time Address Binding
Load Time Address Binding
Compile Time Address Binding
Dynamic relocation with a base register
Memory Management Unit (MMU) - dynamically converts logical addresses into physical address
MMU contains base address register for running process
process i
Operatingsystem
Max addr
0
Max Mem
0
Physical memory address
Relocation register for process i
1000
+
MMU
Program generated address
Protection using base & limit registers
Memory protectionBase register gives starting address for processLimit register limits the offset accessible from the
relocation register
base
+
Physicaladdress memory
register
<
limitregister
yes
no
addressing error
logicaladdress
Logical vs. Physical Address Space
The concept of a logical address space that is bound to a separate physical address space is central to proper memory management.○ Logical Address: or virtual address - generated by CPU○ Physical Address: address seen by memory unit.
Logical and physical addresses are the same in compile time and load-time binding schemes
Logical and physical addresses differ in execution-time address-binding scheme.
04/20/23 12Edusat lect. Rimple GPC,Amritsar
Features of Memory Management Relocation
1. Static
2. Dynamic
Protection Sharing Logical organization Physical organization Memory Compaction
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Various Methods used by OS
Swapping
Virtual Memory
Paging
Segmentation
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Swapping
Memory allocation changes as processes come into memoryleave memory
Shaded regions are unused memory15
Swapping
Allocating space for growing data segment Allocating space for growing stack & data segment
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Memory Management with Bit Maps
Part of memory with 5 processes, 3 holestick marks show allocation unitsshaded regions are free
Corresponding bit map Same information as a list
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Memory Management with Linked Lists
Four neighbor combinations for the terminating process X
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Managing memory with linked lists Searching the list for space for a new process
First FitNext Fit
○ Start from current location in the listBest Fit
○ Find the smallest hole that will work○ Tends to create lots of really small holes
Worst Fit○ Find the largest hole○ Remainder will be big
Quick Fit○ Keep separate lists for common sizes
Virtual Memory Virtual Memory
○ Separation of user logical memory from physical memory.
○ Only PART of the program needs to be in memory for execution.
○ Logical address space can be much larger than physical address space.
○ Need to allow pages to be swapped in and out.
Virtual Memory can be implemented viaPagingSegmentation
Virtual Memory
The position and function of the MMU
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Paging
The relation betweenvirtual addresses
and physical memory addresses given
bypage table
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Page Tables
Internal operation of MMU with 16 4 KB pages23
Page Tables
32 bit address with 2 page table fields Two-level page tables
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Top-level page table
Page Tables
Typical page table entry
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TLBs – Translation Look aside Buffers
A TLB to speed up paging
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Inverted Page Tables
Comparison of a traditional page table with an inverted page table
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Page Replacement Algorithms Page fault forces choice
which page must be removedmake room for incoming page
Modified page must first be savedunmodified just overwritten
Better not to choose an often used pagewill probably need to be brought back in soon
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Page Replacement Algorithms
Optimal Page Replacement
Not Recently Used Page Replacement Algorithms.
FIFO Page Replacement Algorithms
Second Chance Algorithms
Clock Page Replacement Algorithms
Least Recently used
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Optimal Page Replacement Algorithm
Replace page needed at the farthest point in futureOptimal but unrealizable
Estimate by …logging page use on previous runs of processalthough this is impractical
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Not Recently Used Page Replacement Algorithm
Each page has Reference bit, Modified bit bits are set when page is referenced, modified
Pages are classified1. not referenced, not modified
2. not referenced, modified
3. referenced, not modified
4. referenced, modified
NRU removes page at random from lowest numbered non empty class
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FIFO Page Replacement Algorithm
Maintain a linked list of all pages in order they came into memory
Page at beginning of list replaced
Disadvantagepage in memory the longest may be often used
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Second Chance Page Replacement Algorithm
Operation of a second chancepages sorted in FIFO orderPage list if fault occurs at time 20, A has R bit set
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The Clock Page Replacement Algorithm
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Least Recently Used (LRU) Assume pages used recently will used again soon
throw out page that has been unused for longest time
Must keep a linked list of pagesmost recently used at front, least at rearupdate this list every memory reference !!
Alternatively keep counter in each page table entrychoose page with lowest value counterperiodically zero the counter
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Review of Page Replacement Algorithms
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Modeling Page Replacement Algorithms Belady's Anomaly
FIFO with 3 page frames FIFO with 4 page frames P's show which page references show page faults
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Stack Algorithms
State of memory array, M, after each item in reference string is processed
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7 4 6 5
Page Size
Small page size Advantages
less internal fragmentation better fit for various data structures, code sectionsless unused program in memory
Disadvantagesprograms need many pages, larger page tables
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Page Size
Overhead due to page table and internal fragmentation
Where s = average process size in bytes p = page size in bytes e = page entry
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2
s e poverhead
p
page table space
internal fragmentatio
n
Optimized when
2p se
Shared Pages
Two processes sharing same program sharing its page table41
Implementation Issues
Four times when OS involved with paging1. Process creation
determine program size create page table
2. Process execution MMU reset for new process TLB flushed
3. Page fault time determine virtual address causing fault swap target page out, needed page in
4. Process termination time release page table, pages
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Backing Store
(a) Paging to static swap area(b) Backing up pages dynamically
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Separation of Policy and Mechanism
Page fault handling with an external pager
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Segmentation
One-dimensional address space with growing tables One table may bump into another
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Segmentation
Allows each table to grow or shrink, independently46
Implementation of Pure Segmentation
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Segmentation with Paging: MULTICS
A 34-bit MULTICS virtual address
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Segmentation with Paging: MULTICS
Conversion of a 2-part MULTICS address into a main memory address
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Segmentation with Paging: MULTICS
Disadvantages of Segmentation 1. Segmentation mapping requires two memory references
per logical address which slows down the computer system . Caching is the method used to solve this problem
2. Where there is more number of segments, segment table size will grow. so it cannot be accommodated in any of the registers and has to be kept in memory
3.Segmentation is prone to external fragmentation. This may occur when all the blocks in memory are too small to accommodate a segment
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Advantages of Segmentation Protection bits are associated with segments, which
check that attempt to write a read only segment should fail.
As with paging sharing of code or data is possible even with the segmentation technique. Here entries in two different segment tables can be made to point to a common physical location.
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Comparison of paging and segmentation
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Summary The memory management allows us how to manage the memory. The virtual memory is the memory which does not existence. The paging process which allows us to change the pages from
memory to the secondary storage devices such processes are known as swap in and swap out.
The segmentation allows us to make the division of the memory into the various segments
The fragmentation occurs due to internally or externally wasteage of memory.
The page replacement is the concept of changing the page from the various frames in the memory whenever required.the page replacement is needed due to the page fault.
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