CHAPTER 1

INTRODUCTION

1.1 FLOATING POINT UNIT

The FLOATING POINT UNIT is a dedicated execution unit designed for performing math functions on

floating point numbers. A floating point number is any number other than an integer; any number with a

decimal point required to represent it is a floating point number. Integers (and data stored as integers)

are processed using the processor's integer execution unit(s).

In computing, floating point describes a method of representing real numbers in a way that can support

a wide range of values. Numbers are, in general, represented approximately to a fixed number of

significant digits and scaled using an exponent. The base for the scaling is normally 2, 10 or 16. The

typical number that can be represented exactly is of the form:

Significant digits × baseexponent

A method for storing and calculating numbers in which the decimal points do not line up as in fixed

point numbers. The significant digits are stored as a unit called the "mantissa," and the location of the

radix point (decimal point in base 10) is stored in a separate unit called the "exponent." Floating point

methods are used for calculating a large range of numbers quickly.

FPU Stands for "Floating Point Unit." The first computer processors were far better at dealing with

integers than with real numbers (a.k.a. floating point numbers). So a separate FPU processor was

developed to handle the floating point calculations. That way, when the CPU encountered a floating-

point expresion (ie. 1.62 * 0.87359), it would send the calculation to the FPU. Since the FPU is

specifically designed to handle floating-point math, it computes expressions involving real numbers

more efficiently. While the first floating point units used to be manufactured as individual chips, they

are now typically integrated into the CPU.

The FPU, also known as a co-processor, used to be an option when the first PCs came on the market.

Modern PCs are now all provided with a co-processor. Although the original PC-XT has evolved

considerably over the years, the FPU itself has not changed appreciably during that same period. Apart

from a few minor instructions having been added, the main improvement has been the extended range

of some of the existing instructions.

The entire set of assembler instructions for the FPU is relatively small and could be memorized rapidly.

Learning which parameter(s) can be used with each instruction should take only slightly longer. The

main difficulty is in developing sound programming techniques to avoid some of the pitfalls peculiar to

the FPU.

1

The main purpose of this document is to show that using the FPU can be relatively easy with minimal

effort. Once the basics have been mastered, any computation however complex can be performed.

A floating point number is a binary number carried out to a specific number of digits, and containing a

radix (or decimal) point somewhere in the digit sequence. Such numbers are stored in three parts: the

sign (either plus or minus), the mantissa (sequence of meaningful digits), and the exponent (power or

order of magnititude), which determines the position in the mantissa where the radix point is placed.

The main operations of the FPU consist of conventional arithmetic such as addition and multiplication.

Some FPUs can also perform more sophisticated.

1.2 MULTIPLIER

A MULTIPLIER is an electronic hardware device used in digital electronics or a computer or other

electronic devices to perform rapid multiplication of two numbers in binary representation.if the

multiplier digit is a 1,the multiplicand is simply copied down and represents the product. If the

multiplier digit is a 0 the product is also 0.

The advantage of floating array multiplier comes from its regular structure. since it is regular, it is easy

to layout, has a small size and time to layout is less as compared to tree multipliers.

FLOATING ARRAY MULTIPLIER is used to multiply the floating point number i.e decimal number.

Multipliers are key components of many high performance systems such as FIR filters,

microprocessors, digital signal processors, etc. A system’s performance is generally determined by the

performance of the multiplier because the multiplier is generally the slowest clement in the system.

Furthermore, it is generally the most area consuming. Hence, optimizing the speed and area of the

multiplier is a major design issue. However, area and speed are usually conflicting constraints so that

improving speed results mostly in larger areas. As a result, a whole spectrum of multipliers with

different area-speed constraints have been designed with fully parallel. Multipliers at one end of the

spectrum and fully serial multipliers at the other end. In between are digit serial multipliers where

single digits consisting of several bits are operated on. These multipliers have moderate performance in

both speed and area. However, existing digit serial multipliers have been Plagued by complicated

switching systems and/or irregularities in design.

2

1.3 BINARY MULTIPLIER

A binary multiplier is an electronic circuits used in digital electronics, such as a computer, to

multiply two binary numbers.

Techniques involve computing a set of partial products, and then summing the partial products

together.

It’s just repeated addition.

Multiplication can be done with the help of adders.

AND operation is equivalent to multiplication on two.

In digital signal processing operations such as correlation, convolution, filtering and frequency

analysis one need to perform multiplication.

Multiplier may be classified as under-

1) Serial form.

2) Serial/Parallel form.

3) Parallel form or Array multiplier

Binary multiplication example

1 1 0 1 Multiplicand

x 0 1 1 0 Multiplier

0 0 0 0 Partial products

1 1 0 1

1 1 0 1

+ 0 0 0 0

1 0 0 1 1 1 0 Product

3

BLOCK DIAGRAM OF FLOATING ARRAY MULTIPLIER

Fig 1 Block Diagram of Floating Array Multiplier

FLOATING POINT REPRESENTATION

Fig 2 Floating Point Representation

4

CHAPTER2

BRIEF LITERATURE SURVEY

Jian Liang et.al (2003): Presents a most commercial and academic floating point libraries for FPGAs

provide only a small fraction of all possible floating point units. In contrast, the floating point unit

generation approach outlined in this paper allows for the creation of a vast collection of floating point

units with differing throughput, latency, and area characteristics.

Jasbir N.Patel et.al (2004): Presents a VLSI implementation of a low power floating point divider in

cmos 0.18um technology using radix-2 over redundant number system. This divider implementation is

well suited for ieee 754 floating point and can be widely used in dsp applications. In the proposed

divider designs, different ppm adders, based on 24, 22 and new 16 transistor circuits are used to

implement the carry for addition/subtraction unit.

Chun Hok Ho et.al (2009): Presents architecture for a reconfigurable device that is specifically

optimized for floating-point applications. Fine-grained units are used for implementing control logic

and bit-oriented operations, while parameterized, reconfigurable word-based coarse-grained units

incorporating word-oriented lookup tables and floating-point operations are used to implement data .

Haping Sun et.al (2003): Presents a novel architecture for the MAF operation is presented.According

to the fact that some steps of MAF operation are mutually exclusive, the composing steps are organised

into two data-paths, and each data-path only contains the indispensable computation steps.one takes

effect when the effective subtraction occurs, and the other takes effect when the effective subtraction

does not occur.

Ahmet akka et.al (2002): Presents a robust method for automatically monitoring numerical errors and

can be used to solve problems that cannot be efficiently solved with floating-point arithmetic.this paper

presents the design and implementation of a combined interval and floating point comparator/selector,

which performs interval intersection, hull, magnitude, maximum, and comparisons, as well as floating

point minimum, maximum and comparisons

Lamiaa S. A. Hamid et.al (2010): Presents a high speed generic Floating Point Unit (FPU) consisting

of a multiplier and adder/subtractor units is proposed. A novel multiplication algorithm is proposed and

used in the multiplier implementation. The new algorithm depends on dividing the multiplication

operation into several smaller multiplications performed in parallel. The output from these

multiplications is then manipulated in a manner to give the final result of the original multiplication

operation. The adder/subtractor unit is implemented using the Leading One Detector (LOD) algorithm.

In order to achieve high maximum, speed, both units were deeply pipelined.

5

S.M.Aziz et.al (1998):present the design of variable array multipliers using VHDL. Multipliers of

various operand sizes for different target processes can be implemented using the proposed VHDL

based approach. The multipliers will be testable with a constant number of the operand word lengths. A

fast test pattern generator is also developed for simulation of the multiplier designs and subsequent

testing of the fabricated chips.

Hasan krad and Aws yousif Al-Taie (2008) has presented the study of multipliers which is done on

the basis of their speeds. Multipliers are designed using VHDL and incorporating two adders in the

designs carry look ahead adders and ripple carry adders. On the basis of performance we studied that

multiplier with carry ahead adder is better than the other one with ripple carry.

Marcelo Rosa Fonseca et.al(2005) has presented that carry save adders are one of the most widely

used techniques which have the ability to add numbers with minimal carry propagation. Carry save

adders are used in the multiplier,to speed up the carry propagation along the array multipliers.power

saving of about 20% is achieved. Less no. of full adders is used in partial product lines which reduces

area and delay values. This reduces switching activity and glitching transition,which leads to power

reduction.

Behnam Amelifard et.al(2005) has presented a new design of low performance adder. This paper deals

with design of carry select adder. It provides the design methodology to design carry select adder in

various stages of different widths. The proposed adder is a compromise between 4select adder.

Whenever there is requirement of less area and low power design and speed is not a constraint,this

adder can be used.

Zhan yu et.al(2000) has proposed a multiplier, which used the encoding property of booth encoder,and

simple modification in carry save adder is done which reduced total switching activity inside the adder

array and reduces power dissipation without any area overhead.

Vojin G. et.al(1995) has presented improvements in bit reduvtion techniques and a final adder is

optimized for the uneven signal arrival profile in cmos multiplier.different column compression counter

architectures are considered to enhance the speed.

C.N.Marimuthu et.al(2008) have presented a good direction to reduce dynamic power that is the major

part of total power dissipation.in this paper,a high speed low-power multiplier adopting the new SPST

implementing approach is proposed.this multiplier is designed by equipping the spurious power

suppression technique (SPST) on a modified booth encoder which is controlled by a detection unit using

an AND gate. With modified Booth encoded the number of partial products generated is reduced by

half.the SPST adder will avoid the unwanted addition and thus minimize the switching power

dissipation.the proposed high speed low power multiplier can attain 30% speed improvement and 225

power reduction in modified booth encoder when compared with the conventional array multipliers.

6

CHAPTER 3

OBJECTIVE AND METHODOLOGY

3.1 PROBLEM FORMULATION

Literature survey describe that switching reduces in tree multipliers as compared to array multiplier s

but array multipliers follow the simple and regular structure hence easy to Layout whereas tree

multiplier are complex in structure and huge number of wires adds to the power dissipation .Dynamic

power is the main source of power dissipation, so it must be reduced to attain the low power multiplier.

Adder architecture plays important role in multiplier. To maintain a balance between three parameters

speed, power and area is a tough challenge so, we must think of the application we require. In this work

we focused on floating array multiplier and took adder architecture as a base to design optimized

multiplier. The main motive of this synopsis work is to design a multiplier that consumes low power

and less area as compared to other multiplier. For this carry select adder has been taken as the base

adder to design an floating array multiplier.

Higher booth encoding technique technique to reduce the partial productivity which will reduce the

delay of multiplier, enhance increase a speed.

Use of spurious power suppression technique can be done to reduce the power consumption.

3.2 OBJECTIVES

1 VHDL modelling of floating array multiplier.

2 Modification of floating array multiplier design.

3 Improvement in area utilization.

4 Improvement in power reduction.

5 To reduce delay by developing efficient algorithm.

3.3 METHODOLOGY/PLANNING OF WORK

1 Carefully construct the architecture in VHDL so that overflow, underflow are avoided and

quantisation errors, if any are within acceptable limits.

2 Synthesize the HDL description.

3 Timing analysis using Timing analyzer.

4 Design of floating array multipliers using VHDL modelling.

5 Carefully study the detail, importance, specification and application of floating array

multiplier.

7

3.4 PRESENT WORK

In this I have discussed the work still I have done for the above discussed problem.

BINARY MULTIPLICATION EXAMPLE

Fig 3 Binary Multiplication

A 2X2 BINARY MULTIPLIER

The AND gates produce the partial products. For a 2-bit by 2-bit multiplier, we can just use two half

adders to sum the partial products. In general, though, we’ll need full adders. Here C3-C0 are the

product.

Fig 4 A 2x2 Binary Multiplier

8

B1 B0 x A1 A0 A0B1 A0B0

+ A1B1 A1B0 C3 C2 C1 C0

RIPPLE CARRY ADDER

a) Four full adders together used.

b) There are nine total inputs:

I. Two 4-bit numbers, A3 A2 A1 A0 and B3 B2 B1 B0

II. An initial carry in, CI

c) The five outputs are:

I. A 4-bit sum, S3 S2 S1 S0

II. A carry out, CO

Fig 5 Ripple Carry Adder

9

MULTIPLICATION OF 4X 4 ARRAY MULTIPLIER

Fig 6 Multiplication Of 4x 4 Array Multiplier

10

A 4X4 MULTIPLIER DIAGRAM

Fig 7 A 4x4 Multiplier Diagram

11

RTL VIEW OF 4X4 ARRAY MULTIPLIER

Fig 8 RTL View Of 4x4 Array Multiplier

12

INTERNAL CIRCUIT DIAGRAM OF 4X4 ARRAY MULTIPLIER

Fig 9 Internal Circuit Diagram Of 4x4 Array Multiplier

13

SYNTHESIS REPORT

Device utilization summary:

Selected Device : 3s200ft256-5

Number of Slices: 16 out of 1920 0%

Number of 4 input LUTs: 27 out of 3840 0%

Number of IOs: 16

Number of bonded IOBs: 16 out of 173 9%

Timing Report:

Speed Grade: -5

Minimum period: No path found

Minimum input arrival time before clock: No path found

Maximum output required time after clock: No path found

Maximum combinational path delay: 15.325ns

14

SIMULATION RESULT

Fig 10 Simulation Result

15

REFERENCES

1. Jian Liang , “Floating Point Unit Generation and Evaluation for FPGAs”, Proceedings of the

11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’03)

1082-3409/03 2003 IEEE.

2. Haiping Sun , “A novel architecture for floating point multiply add-fused operation”,

0-7803-8185-8 march 2003 IEEE.

3. Ali malik, “a study on the floating point adder in FPGAS”.,1-4244-0038-4

IEEE CCECE/CCGEI, Ottawa, May 2006.

4. Jasbir n.patel, “VLSI implementation of a floating point divider”,0-7803-8656-6

april.(2004).

5. ChunHokHo,, “Floating point FPGA:Architecture and Modeling”,1063-8210/2009 IEEE.

6. Ahmet Akkas ,“A combined interval and floating point comparator/selector”, 2002 IEEE.

7. Christian Jacobi , “Automatic Formal Verification of Fused-Multiply-Add FPUs Proceedings of

the Design”, Automation and Test in Europe Conference and Exhibition

(DATE’05) 1530-1591 may 2005 IEEE.

8. Yee Jern Chong, “Configurable Multimode Embedded Floating-Point Units for FPGAs” ,1063-

82 oct 2010 IEEE.

9. Neil Hockert-FFPU: “fractured floating point for FPGA Soft Processors”, 978-1-4244-4377-

2/sep2009.

10. Jochen Preiss , “Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point

Units”, 1063-6889/09 2009 IEEE DOI 10.1109/ARITH.2009.17.

11. Hasan krad and Aws Yousif Al-Taie, “Performance analysis of a 32-bit multiplier with a carry

look-Ahead adder and a 32-bit multiplier with a ripple adder using VHDL”, journal of computer

science 4 (4):pp 305-308,2008.

12. Marcelo Rosa fonseca, “ Performance optimization of radix-2^m multiplier using carry save

adders”,in XI workshop iberchip,Salvador-BA.,pp.126-131,2005.

13. Behnam amelifard, “closing the gap between carry select adder and ripple carry adder: a new

class of low power high performance adders”, in proc. Of IEEE international symposium on Quality

Electronic Design (ISQED),2005.

14. Zhan yu, “ A painless way to reduce power dissipation by over 18% in Booth-encoded carry-

save array multipliers for DSP”, in IEEE workshop on signal processing systems,pp.571-580,2000.

15. C.N.Marimuthu, “ Low power high performance multiplier”,ICGST-PDSC,Volume 8,issue

1,pp.31-38,December 2008.

16