0 VERSAMPLED analog-to-digital (A/D)...

1746 IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 26, NO. 12, DECEMBER 1991

A 50-MHz Multibit Sigma-Delta Modulator for 12-b 2-MHz A/D Conversion

Brian P. Brandt, Student Member, IEEE, and Bruce A. Wooley, Fellow, IEEE

Abstract -0versampling techniques offer several advantages for the implementation of high-resolution analog-to-digital (A/D) converters in VLSI technologies. This paper examines the application of oversampling techniques to A/D conversion at rates exceeding 1 MHz. A cascaded multibit sigma-delta (EA) modulator that substantially reduces the oversampling ratio required for 12-b conversion while avoiding stringent component matching requirements is introduced. Issues concerning the design and implementation of the modulator are presented. At a sampling rate of 50 MHz and an oversampling ratio of 24, an implementation of the modulator in a I-Fm CMOS technology achieves a dynamic range of 74 dB at a Nyquist conversion rate of 2.1 MHz. The experimental modulator is a fully differential circuit that operates from a single 5-V power supply and does not require calibration or component trimming.

I. INTRODUCTION VERSAMPLED analog-to-digital (A/D) converters 0 based on sigma-delta (CA) modulation have previ-

ously been used for high-resolution signal acquisition in voice-band telecommunications, digital audio, and ISDN applications. In these applications, the use of oversampling techniques has resulted in robust implementations by exploiting the enhanced speed and circuit density of scaled VLSI technologies to overcome resolution limitations resulting from component mismatch and reduced supply voltages. This work examines the application of oversampling techniques to A/D conversion at rates exceeding 1 MHz with a resolution of 12 b or more. While Nyquist-rate converters are capable of achieving this level of performance in a CMOS technology using a pipelined architecture [ 11, there are several distinct advantages to using an oversampling approach. Oversampled A/D converters can achieve high resolution without trimming or calibration because of their tolerance for component mismatch and circuit nonidealities. These converters also simplify system integration by reducing the burden on the supporting analog circuitry. Specifically, they do not re-

Manuscript received May 1, 1991; revised July 26, 1991. This research was supported by the Semiconductor Research Corporation under Con- tract 91-DJ-112 and by a grant from Texas Instruments Incorporated.

B. P. Brandt was with the Center for Integrated Systems, Stanford University, Stanford, CA 9430.5. He is now with Texas Instruments Incorporated, Dallas, TX 75265.

B. A. Wooley is with the Center for Integrated Systems, Stanford University, Stanford, CA 9430.5.

IEEE Log Number 9103221.

quire precision sample-and-hold circuitry and they relax the performance requirements on the analog antialias filter that precedes the sampling operation. Oversampled A/D converters include an inherent digital filtering capa- bility and their resolution versus conversion rate is easily tailored to allow use of the same converter in a variety of applications.

Increasing the conversion rate of an oversampled A/D converter may be accomplished by increasing the modulator sampling rate or decreasing the oversampling ratio M , which is the ratio of the modulator sampling rate to the conversion rate. To achieve conversion rates above 1 MHz using CMOS switched-capacitor circuit techniques, it is advantageous to reduce the oversampling ratio below the range of 64 to 512 typically used in oversampling converters. For 12-b resolution, an oversampled A/D converter based on a second-order X A modulator [2] would require an oversampling ratio of 50 in an ideal implementation. In a practical implementation, an oversampling ratio of 64 or higher may be required to compensate for circuit nonidealities such as electronic noise. One method of reducing the oversampling ratio below that required for a second-order XA modulator is to increase the order of the noise shaping by including additional integrators in the modulator’s forward path [31. However, at low oversampling ratios the effectiveness of increasing the order of the modulator’s noise shaping is significantly reduced. Moreover, the performance improvement is further reduced when gain factors less than unity are included in the modulator’s forward path to improve stability.

Alternatively, the 1-b quantizer typically used in a ZA modulator can be replaced by a multibit quantizer to increase the dynamic range (DR) according to

DR Increase = 2010g( 2 N - 1) dB (1) where N is the resolution of the multibit quantizer in bits. For example, when a 4-b quantizer is used instead of a 1-b quantizer, the quantization level spacing is reduced by a factor of 15 for constant outermost quantization levels, resulting in a dynamic range increase of nearly 24 dB. Note that the dynamic range improvement is independent of the oversampling ratio and is therefore particularly attractive in the present application. However, while modulators based on multibit quantization are tolerant of nonlinearity in the quantizer’s analog-to-digital converter

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Fig. 2. Linear model of the cascaded multibit Z A modulator.

(ADC) because of noise shaping, they may impose stringent linearity requirements on the quantizer’s digital-to- analog converter ( D A C ) . In these modulators, the error due to DAC nonlinearity effectively enters the modulator at its input. Therefore, the modulator’s linearity and resolution are limited by the precision of the multibit D/A converter. Section I1 introduces a cascaded multibit modulator that avoids the sensitivity to DAC precision. Issues concerning the implementation of this modulator are then addressed in Section 111. The design of an experimental implementation is described in Section IV, and measurement results characterizing its performance are presented in Section V.

11. CASCADED MULTIBIT XA MODULATOR The cascaded multibit modulator shown in Fig. 1 avoids

sensitivity to the DAC precision by placing the multibit quantizer in the final stage of a third-order cascaded modulator. The more critical first-stage quantizer has

only two analog output levels and is therefore inherently linear. The modulator consists of a second-order stage with a 1-b quantizer followed by a first-order stage with a multibit quantizer and is similar to a cascade of two stages with 1-b quantization proposed previously [41. The input to the second stage is a weighted difference of the output and the input of the first-stage quantizer. When the coupling coefficients, a and p, are unity, the input to the second stage is the quantization error of the first stage. This cascaded modulator is more tolerant of imper- fections in the circuits used for its implementation than a cascade of three first-order stages [5], [6], as will be discussed in Section 111.

Fig. 2 shows a linear approximation of the modulator in Fig. 1 wherein the quantizers are modeled by signal-independent additive error sources, while the integrators are represented by their transfer functions in the z domain. E , ( z ) and E J z ) model the quantization error of the first and second-stage A/D converters, respectively. E,(z) also contains a representation of nonlinearity in the sec-

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1748 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO. 12, DECEMBER 1991

ond-stage A/D converter, and E J z ) models the error resulting from nonlinearity in the multibit D/A converter in the second stage. A corresponding error source does not appear in the first stage because of the inherent linearity of the 1-b D/A converter.

For the linearized model of Fig. 2, the 2 transform of the output of the first-stage is

Y, (Z ) = 2 - ' X ( 2 ) + ( l - 2 - ~ ) 2 E , ( 2 ) . ( 2 )

Thus, the output of the first stage includes the input to the modulator delayed by one sample period plus the second-order difference of the first-stage quantization error E,(z) . When a = p = l , the input to the second stage is E1(z) and the transform of the second-stage output is

Y2( 2 ) = z- l (E1( 2 ) - E,( 2) ) + (1 - 2-1)E2( 2 ) . (3)

Y ( 2 ) = 2 - ' Y , ( z ) - ( l - z - ~ ) 2 Y 2 ( 2 ) (4)

The error cancellation logic combines the digital outputs from the two stages according to

so as to cancel the quantization error of the first stage.

tained by substituting (2) and (3 ) into (4): The resulting output of the overall modulator is ob-

Y ( 2 ) = 2-2x( 2 ) + 2 - ' ( 1 - 2-1 ) 2 E D ( 4

- (1 - z-1)-?E2( *). ( 5 ) Thus, ideally the quantization error of the first stage is cancelled and the quantization error of the second stage is attenuated in the baseband by third-order shaping. As in a cascade of three first-order stages, third-order shaping is achieved without instability because the constituent stages are independently stable. Also, because the quantization error of the second stage originates from a multibit quantizer, the modulator's dynamic range is improved according to (1).

In contrast to a single-stage multibit modulator, the error resulting from DAC nonlinearity, E J z ) , does not enter this modulator at its input but instead is attenuated in the baseband by second-order shaping, as is evident in (5). The second-order shaping makes the cascaded multibit modulator much more tolerant of DAC nonlinearity than the single-stage modulator, as indicated in Fig. 3. This figure compares the simulated [7] baseband spectra for the modulator of Fig. 1 with that of third-order single-stage multibit modulator under the circumstance of 5-b DAC integral linearity. The spectrum for the single- stage modulator exhibits a substantially increased noise floor and harmonic distortion, while the spectrum of the cascaded modulator exhibits a noise floor only slightly higher than that resulting from an ideal DAC. More importantly, the cascaded modulator does not display any harmonic distortion, a consequence of the second-order shaping and the fact that the input to the second stage contains the quantization error of the first stage, which is substantially decorrelated from the input to the modulator.

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Fig. 4. Simulated sensitivity to DAC linearity.

Fig. 4 compares the sensitivity to DAC linearity for the cascaded and third-order single-stage multibit modulators. To achieve 12-b dynamic range, the cascaded modulator requires a DAC linearity of only 6 b, while more than 10-b linearity is needed in the single-stage modulator. Moreover, even with 10-b DAC linearity, the single- stage modulator continues to exhibit harmonic distortion.

In Fig. 4 it is seen that the single-stage modulator achieves a 6-dB larger dynamic range for DAC linearity greater than 12 b. This is a consequence of a signal range reduction that must be performed in the cascaded modulator. With the coupling coefficients (Y and p equal to unity, the input to the second stage is the entire quantization error of the first stage. The large amplitude of the quantization error produced by the second-order first stage would overload the input range of the second stage (which is the same as the input range of the first stage) and therefore must be attenuated by reducing (Y and p. When (Y and p are reduced equally, the output of the second stage, Y2(z), must be digitally scaled by a- ' be- fore the error cancellation logic described by (4) is performed. The resulting output of the modulator is then Y( 2 ) = P X ( 2 ) + .I[ 2 - I ( 1 - 2-1)2ED( 2 )

- (1 - 2-')-?E2( z ) ] . (6)


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Fig. 5 . Simulated SNDR for a sinusoidal input at M = 16.

Note that both error terms increase because of the scaling of the second-stage output by a-'. This scaling is respon- sible for the 6-dB loss in dynamic range for DAC linearity exceeding 12 b seen in Fig. 4, where a = 0.5. Note that it is advantageous to make a-' a power of 2 so that the digital scaling may be'implemented with a simple shift of bit significance.

It is not necessary that a equal p. When a is not equal to p, the input to the second stage is given by

( P - a ) YI( 2 ) + "E,( z ) . (7)

Thus a component of Y , ( z ) will be present in the output of the second stage, Y2(z). However, this component can be easily removed digitally prior to the error cancellation logic described in (4) by preprocessing the outputs of both stages according to

Fig.

Y2p( Z ) = a- '[ Y2( Z) - z-'( /3 - a)Y,( z) ] . (8)

Y 2 p ( t ) takes the place of Y2(z) in (4) and the combined output of the modulator is given by (6). Again, it is useful to make a-' and ( p - a ) powers of 2.

Suitable values of a and p may be determined through simulation. Fig. 5 shows the simulated signal-to-(noise + distortion) ratio (SNDR) for three pairs of coupling coefficients. For input signals smaller than -5 dB, the SNDR is independent of p, consistent with its absence in (6). Therefore, p may be optimized to constrain the signal range at the input to the second stage to allow the largest possible value of a. It is evident that there are trade-offs between small-signal performance, large-signal performance, and hardware complexity. If a=0.5 and p = 1, the dynamic range is maximized. If a = 0.25 and p = 1, the signal amplitude at which the SNDR begins to de- crease is maximized. Finally, if a = 0.25 and p = 0, the hardware complexity is reduced by eliminating the subtraction node at the input to the second stage.

Fig. 6 shows the simulated probability density functions at the input to the second stage for a -5-dB modulator input and the same three pairs of coupling coefficients considered in Fig. 5. A fairly even distribution is produced if a=OS and p=1. Both the a=O.5, p=1 and

SECOND-STAGE INPUT (A)

6. Simulated probability density functions at input of the second stage for a - 5-dB sinusoidal modulator input.

the a = 0.25, p = 0 couplings result in small tails that extend beyond *0.5A, which defines the input range of both the first and second stages. For modulator inputs larger than -5 dB, these tails grow and result in the premature reduction in SNDR for increasing signal am- plitudes seen in Fig. 5. Additional information concerning the selection of appropriate coupling coefficients is presented elsewhere [8].

111. IMPLEMENTATION Fig. 7 shows a fully differential, switched-capacitor

CMOS implementation of the cascaded multibit ZA modulator. The first stage consists of two parasitic-insensitive integrators, a comparator that serves as the 1-b ADC, and a distributed two-level (1 b) DAC. The second stage consists of a single integrator, a 3-b flash ADC, and a 3-b differential DAC. The modulator operates on a two-phase nonoverlapping clock consisting of a sampling phase and an integration phase. During phase 1, the integrators sample their inputs by closing switches S1 and S 3 and the first-stage comparator and second-stage ADC are strobed. The nodes labeled Kmi set the common-mode input voltage of the fully differential operational amplifiers.


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Fig. 7. Fully differential CMOS implementation of the cascaded multibit ZA modulator (shown for a = 0.25 and p = 0).

Switches S 2 and S4 conduct during phase 2 to perform the subtraction and integration functions. Switches S 3 and S4 are opened slightly ahead of switches SS and S2, respectively, to reduce signal-dependent charge injection [9]. Note that the pipelined nature of this implementation reduces the critical path to one integrator delay per clock cycle.

Two modifications of the modulator in Fig. 1 are evident in Fig. 7. First, both integrators in the first stage include delays in their forward paths, as well as gain factors of 1/2 at their inputs that are set by the ratio of their sampling and integrating capacitors. Thus, the transfer function of both first-stage integrators is

s z- ‘ H ( 2 ) = - . - 2 1 - 2 - l . (9)

This configuration reduces the signal range required at the outputs of the first-stage integrators to about 1.5 times the modulator’s input range, k0SA [lo]. The output of the first stage given in (2) is changed only slightly to include an additional delay preceding X ( z ) .

The second modification present in Fig. 7 is that the input to the second stage is simply the differential output of the second integrator in the first stage. The combina- tion of this simple coupling and the 1/2 gain factors in the first-stage integrators implement a = 0.25 and p = 0. In the experimental circuit presented in Section V, two additional sampling capacitors and additional switches were included in the second-stage integrator, as shown in Fig. 8, to allow selection among the three pairs of coupling coefficients listed in Fig. 5. The nodes labeled V,,,

in Fig. 8(b) are biased at the reference voltage used to establish the common-mode output level of the operational amplifiers.

The performance of cascaded modulators is typically more sensitive to circuit nonidealities than single-stage modulators because of the absence of feedback around the entire modulator. The cancellation of the first-stage quantization error depends on the noise shaping specified in (2) precisely matching the shaping performed in the error cancellation logic. In practical implementations the first-stage noise shaping deviates from that given in (2 ) because of circuit nonidealities such as capacitor mismatch and the finite dc gain and bandwidth of operational amplifiers. As a result, the quantization error of the first stage is not completely cancelled, and it degrades the modulator’s performance. However, the modulator of Fig. 1 has an advantage over a cascade of three first-order stages [ 5 ] , [61 in that uncancelled quantization error from the first stage is attenuated in the baseband by second- order shaping rather than only first-order shaping [8]. The sensitivity to first-stage error leakage is further reduced in the present application because of the reduced oversampling ratio. The difference between second and third-order shaping is reduced at low oversampling ratios. Thus, the impact of the uncancelled second-order shaped error from the first stage is not as great as at higher oversampling ratios.

The expected magnitude of the uncancelled quantization error from the first stage influences the resolution chosen for the multibit quantizer in the second-stage. In an ideal implementation, the multibit quantizer resolution

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3 10 ... ... ?... .... * ....... t ........ * ........ t ........ *. ........ e ........ 4 ....... .+ ........e

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Fig. 9. Dynamic range increase provided by the second stage for M = 16.

the sensitivity to gain error. At increasing levels of gain error, the performance of the modulator becomes domi- nated by uncancelled first-stage quantization error and less benefit is derived from increasing the second-stage quantizer resolution. The use of a 1-b quantizer in the second stage as reported previously [4], [12] increases the dynamic range by less than 10 dB at low oversampling ratios but results in a large tolerance for gain error. The use of a multibit second stage provides a means of trading some of this tolerance for increased dynamic range without imposing strict constraints on the precision of the multibit D/A converter. Thus, a designer can tailor the modulator to the expected capacitor matching of the fabrication process.

A 2% gain error tolerance was selected to ensure a robust implementation of the modulator in the present work. While this tolerance may be larger than required by capacitor matching considerations, it eases the require-

a = 0.5,

can be increased indefinitely to improve the dynamic range according to (1). However, in a practical implementation, increasing the resolution of the multibit quantizer reduces the second-stage quantization error and thereby increases the sensitivity to uncancelled quantization error from the first stage. Fig. 9 presents analytical results derived using the linear model of Fig. 2 [ill, as well as supporting simulation results, that provide a basis for choosing the resolution of the second-stage multibit quantizer. With the quantizer resolution as a parameter, the increase in dynamic range provided by the second stage relative to the first stage is plotted as a function of the error in the 1/2 gain factors in the first-stage integrators. For example, the second-order first stage provides a dynamic range of 49 dB at an oversampling ratio of 16. A second stage with a 3-b quantizer increases the dynamic range of the modulator by 26 dB when the error in the ratio of the sampling and integrating capacitor sizes is 2%.

ments on other circuit nonidealities, such as incomplete linear settling of the integrator outputs. At a gain error of 2%, the benefit of a 4-b over a 3-b quantizer is approximately 4.5 dB and does not justify doubling the size and loading of the second-stage quantizer. Hence, as indicated in Fig. 7, a 3-b quantizer was chosen for the second stage. At higher oversampling ratios the performance of a cascaded modulator is more sensitive to uncancelled quantization error from the first stage and the additional tolerance provided by a 1-b second-stage quantizer may be required. Thus, the use of multibit quantization in the second stage is most attractive at low oversampling ratios.

The performance of a cascaded modulator may also be degraded by integrator leakage resulting from the finite dc gain of the operational amplifiers. The transfer function of a leaky integrator is given by

1 H ( 2) =

1-(1- A,')z-' Several observations can be made concerning the re-

sults shown in Fig. 9. Increasing the resolution of the multibit quantizer increases both the dynamic range and

where A,, = H(1) is the dc gain of the operational amplifier. For this case the transform of the output of the first

1752 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO. 12, DECEMBER 1YY1

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20 30 40 50 60 70 80 -80

DC GAIN, Adc (dB)

Fig. 10. Dependence of the baseband error power on operational amplifier dc gain.

stage given in (2) becomes approximately

Y,( 2 ) = z - I X ( 2 ) + [ (1 -

+2A,'z-'(l- z - ' )+AJ , ' z -2]E1(2 ) . (11)

The first term in the bracket is cancelled by the error cancellation logic. However, the second and third terms are not cancelled and result in first-order shaped and unshaped quantization error appearing at the combined modulator output Y ( z ) . The first-order shaped error is inversely proportional to Ad=, while the unshaped error is inversely proportional to the square of Adc. The resulting baseband quantization error power, relative to the power of a sine wave with a peak-to-peak amplitude of A, is given by

8rr2 2 ( 12) s, = s,, + ~ + ~

9M3A;, 3MA4,,

where S,, is the nominal baseband error power with infinite dc gain. For typical dc gain values and oversampling ratios, the contribution of the unshaped error represented by the last term in (12) is negligible.

Fig. 10 shows the dependence of the baseband quantization error power on the dc gain given by (121, along with supporting simulation results, for the cascaded multibit modulator. Approximately 60 dB of dc gain is required to prevent performance degradation. This gain is lower than required for a cascade of three first-order stages, wherein unshaped first-stage quantization error inversely proportional to the dc gain is leaked to the output of the modulator [6].

Cascaded modulators are susceptible to the appearance of discrete noise tones in their output when the first-stage quantization error is not entirely cancelled because of integrator gain error or leakage [131. These tones arise from repetitive patterns that occur in the first-stage quantization error for certain modulator inputs [14]. In an ideal cascaded modulator, the first-stage quantization error, including the tones, is cancelled. Moreover, while quantizer overload has prevented an exact analysis of the cascade of a second-order and a first-order stage [15],

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Fig. 11. Fully differential folded-cascode operational amplifier with common-mode feedback.

simulations indicate that the second-stage quantization error is free from discrete noise tones.

The second-order first stage can produce tones as strong as 52 dB below full scale at an oversampling ratio of 16 [13]. In the absence of integrator gain error and leakage, the tones are cancelled. In the presence of 1% and 2% gain errors, the tones are reduced by 40 and 34 dB, respectively. An operational amplifier dc gain of 60 dB results in tones that are 91 dB below full scale.

IV. CIRCUIT DESIGN The cascaded multibit ZA modulator depicted in Fig. 7

has been designed for fabrication in a 1-pm CMOS VLSI technology with the goal of verifying experimentally the aforementioned attributes of this modulator. The performance objective was a Nyquist conversion rate greater than 1 MHz and a dynamic range of 12 b while operating from a single 5-V power supply.

The operational amplifier used in the integrators is the most critical element of the modulator. Simulations indicate that the signal range required at the output of the second-stage integrator is less than that needed in the first-stage integrators. As noted previously, the first-stage operational amplifiers require an output range of about 1.5 times the modulator input range. Incomplete settling of the integrator outputs can be considered a gain error if the settling process is linear [lo], [13]. However, the settling speed of the integrators ultimately limits the achievable sampling rate of the modulator, even if com- plete settling is not required. Slew-rate limiting represents a departure from linear settling and must be avoided.

The need for fast settling, coupled with a relatively modest gain requirement of 60 dB to suppress harmonic distortion and leakage of quantization error from the first stage, encouraged the use of the folded-cascode operational amplifier shown in Fig. 11 [16]. The common-mode output level of the amplifier is maintained by the switched-capacitor feedback circuitry also shown in Fig. 11. Capacitors C1 and C2 have equal value and form a voltage divider to drive node A , the gates of the NMOS current source transistors in the output stage. Only

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changes in the common-mode output are coupled to node A , which returns the common-mode output voltage to the desired level through negative feedback. During phase 1, corrective charges are transferred onto C1 and C2 from refresh capacitors to prevent drift in the common-mode output voltage.

The performance of the modulator is relatively insensitive to offset and hysteresis in the first-stage comparator because the effects of these impairments are attenuated in the baseband by second-order noise shaping. A fast regenerative latch [171 without preamplification, as described in [13], has been used to implement the first-stage comparator. The modulator performance is also very tolerant of nonlinearity and hysteresis in the second-stage 3-b A/D converter because their effects are attenuated in the baseband by third-order noise shaping. The design of this A/D converter is complicated by the fact that it must compare the differential output voltage of the second- stage integrator to seven differential reference voltages. This is accomplished by charging seven pairs of capacitors to unique differential voltages derived from a reference resistor string during phase 1, as shown in Fig. 12 [18]. During phase 2, the left sides of the capacitors are driven by the outputs of the second-stage integrator. Seven regenerative latches of the same type used for the first-stage comparator are strobed at the end of phase 2 to perform the 3-b conversion. In the actual implementation, source followers are placed at the outputs of the second-stage integrator to buffer the loading resulting from the seven comparators. Equivalent buffers are placed between the resistor string and the comparators to compensate for gain error and nonlinearity introduced by the source followers.

The modulator's tolerance of nonlinearity in the second-stage 3-b DAC permits the use of a simple differential tapped resistor string for its implementation, as is also illustrated in Fig. 12. A 1-out-of-8 code produced by the AND gates in the 3-b flash ADC selects the proper pair of taps from the resistor string. The l-out-of-8 code is also converted into the 3-b binary output of the second stage by simple encoding circuitry (not shown).

V. EXPERIMENTAL RESULTS The cascaded multibit CA modulator has been fabri-

cated in a 1-pm CMOS technology with metal-to-polycide capacitors and polysilicon resistors [19]. Fig. 13 is a die photograph of the modulator, which has an area of 0.65 mm2 and operates from a single 5-V supply with a power dissipation of 41 mW.

The performance of the modulator was evaluated by driving its input with a high-quality differential sinusoidal signal source [20], acquiring the digital outputs from the first and second stages, and transferring the acquired data to a workstation for processing. A simple passive first- order antialias filter was used at the input to the modulator. The clock input was generated using a pulse generator triggered by a frequency-locked RF sine-wave source. Bias voltages were supplied externally using low-noise voltage references. The simple digital logic required to cancel the quantization error of the first stage, as well as decimation filtering and signal analysis, were performed on a workstation with the same software used for simulations of the modulator [7]. Performance metrics such as SNDR were determined using the sinusoidal minimum error method [211.

I751 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, NO. 12, DECEMBER 1991

Fig. 13. Die photograph of the cascaded multibit X A modulator.

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Fig. 14. Measured SNDR for a 1-MHz baseband.

Fig. 14 shows the measured SNDR as a function of the input sine-wave amplitude. An input level of 0 dB represents a sine wave whose peak-to-peak amplitude equals the input range of the modulator A , which is 3 V (differential) in this implementation. The frequency of the input sine wave was 100 kHz and the modulator sampling rate was 50 MHz, which produced a 2.1-MHz Nyquist conversion rate at an oversampling ratio of 24. The modulator achieves a 74-dB dynamic range and a peak SNDR of 69 dB.

The measured baseband spectrum for a 100-kHz sine- wave input, obtained from a 4096-point fast Fourier transform, is shown in Fig. 15. The small second and third harmonic components present in the spectrum also appear in the output spectrum of the first stage and are therefore not attributable to nonlinearity in the multibit D/A converter in the second stage. The linearity of the metal-to-polycide capacitors was far better than required

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Fig. 15. Measured baseband spectrum,

in this application, as established earlier [13]. The noise floor is higher than predicted from thermal noise generated by the sampling switches onto the 200-fF sampling capacitors in the first integrator. The noise floor is also higher than calculated for thermal and flicker noise in the operational amplifiers. Quantization noise limitations alone should allow a dynamic range exceeding 80 dB at an oversampling ratio of 24.

Both the noise floor and the harmonic distortion were quite sensitive to changes in package and test board features such as the grounding configuration, the location of decoupling capacitors, and the loading on the output pins. A second generation of the test board, designed around a leadless chip carrier instead of a 40-pin DIP, extended the sampling rate from 36 to 50 MHz. There was also strong evidence of substrate coupling from the output pad drivers to the modulator. On-chip circuitry performed a serial-to-parallel conversion to slow the output data rate by a factor of 4. However, this increased the number of output pad drivers from four to 16. The voltage swing of these CMOS drivers had to be reduced to 1.5 V to minimize the coupling to the sensitive analog circuitry.

As mentioned previously, the experimental modulator was designed to allow selection among the three pairs of coupling coefficients listed in Fig. 5. Experimentally, there was less than a 2-dB difference in dynamic range among the three pairs of coupling coefficients because the modulator's performance was not limited by quantization noise. The results presented in Figs. 14 and 15 were obtained for a = 0.25 and p = 0 since this coupling eliminates the need for the subtraction node at the input of the second stage.

The performance of the modulator degrades above a sampling rate of 50 MHz principally because of incomplete settling of the integrator outputs. At 50 MHz, the integrator outputs have about 3.5 time constants in which to settle. This is equivalent to a gain error of 3% if the settling is linear. Thus, at sampling rates above 50 MHz, it is expected that the quantization noise will increase and surpass the noise due to packaging and substrate cou-

BRANDT AND WOOLEY: 50-MHz MULTIBIT SIGMA-DELTA MODULATOR

TABLE I CASCADED MULTIBIT HA MODULATOR PERFORMANCE SUMMARY

Dynamic Range Peak SNDR Sampling Rate Oversampling Ratio Conversion Rate Signal Band Differential Input Range Supply Voltage Power Dissipation Area Technology

74 dB (12 b) 69 dB 50 MHz 24 2.1 MHz 1 MHz 3 v 5 v 41 mW 0.65 mm2 1-pm CMOS

pling. The frequency of the sine-wave input was limited to 100 kHz by the signal generator.

Key performance parameters for the modulator and the operational amplifier are summarized in Tables I and 11, respectively. The operational amplifier performance measurements were obtained from isolated test structures. Measurements of the unity-gain frequency, slew rate, and settling time constant were obtained using low-capaci- tance active probes [22].

VI. CONCLUSION The implementation of CMOS oversampling A/D con-

verters with conversion rates exceeding 1 MHz is facili- tated by lowering the oversampling ratio. ZA modulators based on multibit quantization are particularly attractive at low oversampling ratios, but they may impose stringent linearity requirements on DAC linearity. The cascaded multibit modulator presented here avoids the dependence on DAC linearity by placing the multibit quantizer in the second stage, where the effects of DAC nonlinearity are attenuated by second-order noise shaping.

An experimental implementation of the proposed modulator has demonstrated that oversampling analog-to-dig- ita1 converters can achieve 12-b resolution at conversion rates exceeding 2 MHz in a 1-pm CMOS technology. The advantages of using an oversampling approach are evident in this modulator’s ability to achieve 12-b resolution without requiring more than 6-b precision in any of the analog circuit components. While the sampling rate of the modulator is limited by the settling of the integrator outputs, the resolution of the modulator could possibly be extended through improved packaging and test fixturing as well as better isolation techniques to reduce substrate coupling.

ACKNOWLEDGMENT The authors wish to thank the members of the Semi-

conductor Process and Design Center of Texas Instru- ments Incorporated for the fabrication of the experimental circuits and their support of this research. They are especially indebted to Dr. R. Hester for his support and encouragement. They also gratefully acknowledge the in- valuable assistance of D. Wingard and Dr. M. de Wit, as well as the contributions and support of simulation tools provided by L. Williams.

TABLE I1 MEASURED OPERATIONAL AMPLIFIER PERFORMANCE

DC Gain 58 dB Unity-Gain Frequency 200 MHz Settling Time Constant 2.5 ns Slew Rate 350 V/ps Linear OutDut Range 4.5 v

REFERENCES

[l] Y.-M. Lin, B. Kim, and P. Gray, “A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-pm CMOS,” IEEE J . Solid-state Circuits, vol. 26, pp. 628-636, Apr. 1991.

[2] J. Candy, “A use of double integration in sigma delta modulation,” IEEE Trans. Commun., vol. COM-33, pp. 249-258, Mar. 1985.

[3] K. Chao, S. Nadeem, W. Lee, and C. Sodini, “A higher order topology for interpolative modulators for oversampling A/D converters,” IEEE Trans. Circuits Syst., vol. 37, pp. 309-318, Mar. 1990.

[4] L. Longo and M. Copeland, “A 13 bit ISDN-band oversampled ADC using two-stage third order noise shaping," in Proc. Custom Integrated Circuits Conf., May 1988, pp. 21.2.1-4.

[SI Y. Matsuya et al., “A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping,” IEEE J . Solid-state Circuits, vol. SC-22, pp. 921-929, Dec. 1987.

(61 M. Rebeschini et al., “A 16-b 160-kHz CMOS A/D converter using sigma-delta modulation,” IEEE J . Solid-state Circuits, vol. 25, pp. 431-440, Apr. 1990.

[7] L. Williams, B. Boser, E. Liu, and B. Wooley, MIDAS User Manual, Version 2.0, Integrated Circuits Lab., Stanford Univ., Stanford, CA, Aug. 1989.

(81 L. Williams and B. Wooley, “Third-order cascaded sigma-delta modulators,” IEEE Trans. Circuits Syst., vol. 38, pp. 489-498, May 1991.

[9] K. Lee and R. Meyer, “Low-distortion switched-capacitor filter design techniques,” IEEE J . Solid-state Circuits, vol. SC-20, pp. 1103-1113, Dec. 1985.

[IO] B. Boser and B. Wooley, “The design of sigma-delta modulation analog-to-digital converters,” IEEE J . Solid-state Circuits, vol. 23, pp. 1298-1308, Dec. 1988.

[ l l ] B. Brandt, “Oversampled analog-to-digital conversion,” Ph.D. dis- sertation, Stanford Univ., Stanford, CA, Aug. 1991.

[12] D. Ribner et al., “16b third-order sigma-delta modulator with reduced sensitivity to nonidealities,” in ISSCC Dig. Tech. Papers, Feb. 1991, pp. 66-61.

[I31 B. Brandt, D. Wingard, and B. Wooley, “Second-order sigma-delta modulation for digital-audio signal acquisition,” IEEE J . So/id-State Circuits, vol. 26, pp. 618-627, Apr. 1991.

[14] J. Candy and 0. Benjamin, “The structure of quantization noise from sigma-delta modulation,” IEEE Trans. Commun., vol. COM- 29, pp. 1316-1323, Sept. 1981.

[15] R. Gray, “Quantization noise spectra,” IEEE Trans. Inform. The- ory, vol. 36, pp. 1220-1244, Nov. 1990.

[161 T. Choi et al., “High-frequency CMOS switched-capacitor filters for communications application,” IEEE J . Solid-state Circuits, vol. SC-18, pp. 652-664, Dec. 1983.

1171 A. Yukawa, “A CMOS 8-bit high-speed A/D converter IC,” IEEE J . Solid-state Circuits, vol. SC-20, pp. 775-779, June 1985.

[18] S. Lewis and P. Gray, “A pipelined S-Msample/s 9-bit analog-to- digital converter,” IEEE J . Solid-state Circuits, vol. SC-22, pp. 954-961, Dec. 1987.

[191 C. Kaya et al., “Polycide/metal capacitors for high precision A/D converters,” in IEDM Tech. Dig., Dec. 1988, pp. 782-783.

1201 SG 505 Option 02 Oscillator Instruction Manual, Tektronix, Inc., Beaverton, OR, Nov. 1982.

[21] B. Boser, K. Karmann, H. Martin, and B. Wooley, “Simulating and testing oversampled analog-to-digital converters,” IEEE Trans. Computer-Aided Design, vol. 7, pp. 668-674, June 1988.

[22] Model I 9 Picoprobe Operating Instructions, GGB Industries, Inc., Naples, FL, 1990.

Brian P. Brandt 6’84) was born in Indianapolis, IN, in 1962. He received the B.S.E.E. degree from Purdue University, West Lafayette, IN, in 1985 and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 1986 and 1991, respectively.


He worked at Eastman Kodak, Rochester, NY, and at Magnavox, Fort Wayne, IN, from 1982 to 1984 as part of a cooperative education program. During the summers of 1985 and 1987, he designed and tested gallium-arsenide integrated circuits at the Hughes Research Labora- tories, Malibu, CA. From 1986 to 1987 he was a Member of the Technical Staff at the Gould Research Center, Rolling Meadows, IL, where he characterized gallium-arsenide devices and circuits. He is currently a Member of the Tech-

nical Staff in the Semiconductor Process and Design Center of Texas Instruments Incorporated, Dallas, TX, where his interests lie in the design of analog, data conversion, and signal processing integrated circuits.

Dr. Brandt received the Beatrice Winner Award for Editorial Excel- lence at the 1991 International Solid-State Circuits Conference. He was awarded graduate fellowships from the Hughes Aircraft Company and the Semiconductor Research Corporation and was the IEEE Fortescue Fellow for 1985-1986. He is a member of Phi Beta Kappa, Tau Beta Pi, and Eta Kappa Nu.

Bruce A. Wooley (S’64-M’70-SM’76-F’82) was born in Milwaukee, WI on October 14, 1943. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from the University of California, Berkeley, in 1966, 1968, and 1970, respectively.

From 1970 to 1984 he was a member of the research staff at Bell Laboratories in Holmdel, NJ. In 1980 he was a Visiting Lecturer at the University of California, Berkeley. In 1984 he assumed his present position as Professor of Electrical Engineering at Stanford University, Stanford, CA. His research is in the field of integrated circuit design and technology where his interests have included monolithic broad- band amplifier design, circuit architectures for high-meed arithmetic, analog-to-digital conver-

sion and digital filtering f o r ‘telecommunications systems, high-speed memory design, and circuit techniques for video A/D conversion and broad-band fiber-optic communications.

Prof. Wooley was the Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS from 1986 to 1989. He was the Program Chairman of the 1990 Symposium on VLSI Circuits and the Co-chairman of the 1991 Sympo- sium on VLSI Circuits. He was the Chairman of the 1981 International Solid-State Circuits Conference, and he is a former Chairman of the IEEE Solid-state Circuits and Technology Committee. He has also served on the IEEE Solid-State Circuits Council and the IEEE Circuits and Systems Society Ad Com. In 1986 he was a member of the NSF-sponsored JTECH Panel on Telecommunications Technology in Japan. He is a member of Sigma Xi, Tau Beta Pi, and Eta Kappa Nu. He received an Outstanding Panelist Award for the 1985 International Solid-state Circuits Conference and the B. Winner Award for Editorial Excellence at the 1991 ISSCC. In 1966 he was awarded the University Medal by the University of California, Berkeley, and he was the IEEE Fortescue Fellow for 1966-1967.

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