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propagation delay of a design. Consequently, the only way to

dramatically reduce the delay is to achieve a routing which is able

to minimize the resistances associated with top levels. Through the

annealing process our program will produce clock trees with very

small resistance values, usually merely fractions of those generated

by a wire optimization program, at top levels via the cost function

we defined, thereby significantly reducing the delay.

To further explore the delay minimization mechanism, we analyzed

the outputs produced from both the wire length and the delay

minimization modes by SASPOM using the same SizeFactor 100.

Fig. 10 illustrates the paths from the sam e sink subset to the roots for

both wire length and delay optimization modes. We observed that the

subtrees

(T)

below node id 767 are identical for both outputs. This

implies that since the RC effect at lower levels have little influence

on the delay, the delay minimization mode just optimized the wire

length to reduce the overall capacitance. However, as the level goes

up, the configurations are different.

In Fig. 10(a), The longest accumulated delay is 12.056 which is

about 87.5%

of

its overall routing, and this agrees with the dominance

claim we made. The longest accumulated delay in Fig. 10(b) is 2.938,

which is about 58.7% of its overall routing. Compared to Fig. 10(a),

the delay shown in Fig. 10(b) has been reduced by 75.6% at the top

two levels for this particular example.

Because the delay information of CL+I6 is not available, we

compared our results to those

of

Tsay and KCR/BK which are the

first and one of the best previous works. Table I1 contains the details

using a 1 0 0 driver. Due to similarity, we om it the results using a

5 0 0 driver. The total delay was calculated according to equation

(3). Compared to KCIUBK, 74.39 and 84.72% average propagation

delay r educt ion w ere ach ieved by SA SP O M and SA S P O I w hen a

[I21 Y.-M. Li and M. A. Jabri, A zero-skew clock routing scheme for VLSI

circuits, in Proc. IEEWACM ICCAD, 1992, pp. 4584 63 .

[I31 W. Smith, How to find Steiner minimal trees in Euclidean d-space,

Algorithmica, vol. 7, no. 2-3, pp. 137-177, 1992.

1141

R.-S.

Tsay, Exact zero skew, in Proc. IEEE ICCAD, 1991, pp.

336339.

1151

P. Widmayer,

Y.-F.

Wu, and C.-K. Wong, On som e distance problems

in fixed orientations, SIAM

J

Computing, vol. 16, no. 4, pp. 728-746,

Aug. 1987.

C-Testable Design Techniques

for

Iterative Logic Arrays

Shyue-Kung Lu, Jen-Chuan W ang, and Cheng-Wen Wu

Abstract-A design-for-testability (DFT) approach for VLSI iterative

logic arrays (ILAs) is proposed, which results n a small constant number

of test patterns. Our technique applies to arrays with an arbitrary

dimension, and to arrays

with

various connection types, e.g., hexagonal

or octagonal ones. Bilateral ILAs are also discussed. The DFT technique

makes general ILAs C-testable by using a truth-table augmentation

approach. We propose an output-assignment algorithm for minimizing

the hardware overhead. We give a CMOS systolic array multiplier as an

example, and show that an overhead of no more than 5.88% is sufficient

to make it C-testable, i.e., 100% single cell-fault testable with only 18 test

patterns regardless of the word length of the multiplier.

Our

technique

guarantees that the test set is easy to generate. Its corresponding built-

in-self-test structures are also very simple.

Index Terms-C-testable, cellular array, design for testability, iterative

logic array, logic testing, multiplier, systolic array.

1 0 0 driver was used, and the percentages were 73.96 and 81.47%

in average when a 50R driver was used. Incidentally, SASPO still

length.

I.

INTRODUCTION

jor contributors to todays high-performance digital signal process-

performed

percent better

than

K C R /B K in terms

Of

wire

VLSI array

processors

have been recognized as one of the ma-

REFERENCES

H. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Read-

ing, MA: Addison-Wesley, 1990.

K. D. Boese and A. B. Kahng, Zero-skew clock routing

trees

with

minimum wirelength, in

Proc. 5th IEEE Int. Con ASIC

(New York,

T.-H. Chao, Y.-C.

Hsu,

and J.-M. Ho, Zero skew clock net routing in

Proc.

29th

ACMIIEEE DAC, June 1992, pp. 518-523.

T.-H. Chao, J.-M. Ho, Y.-C. Hsu, K. Boese, and A. Kahng, Zero skew

clock routing with minimum wirelength, IEEE Trans. Circ.,

Syst.

vol.

N.-C. Chou and C.-K. Cheng, Wire length and delay minimization in

general clock net routing, in Proc. IEEWACM ICCAD (Santa Clara,

CA), Nov. 1993, pp. 552-555.

W. W.-M. Dai, R outing MCMs,

IEEE Spectrum,

vol. 29, pp. 6144,

1992.

M. Edah iro, Minimum skew and minimum path leng th routing in VLSI

layout design, NEC

Res.,

Development, vol. 32, no. 4, pp. 569-575,

Oct. 1991.

M. Edahiro, A clustering based optimization algorithm in zero-skew

routings, in Proc. 30th ACM/IEEE DAC, June 1993, pp. 612416.

M. Jackson, A. Srinivasan, and E.

S .

Kuh, Clock routing for high

performance ICs, in Proc.

27th

ACM/IEEE DAC, 1990, pp. 573-579.

A.

B.

Kahng, J. Cong, and

G.

Robins, High-performance clock routing

based on recursive geo metric matching, in Proc. 28th ACWIEEE DAC,

1991, pp. 322-327.

S.

Kirkpatrick, C . D. Gelatt, Jr, and

M. P.

Vecchi, Optimization by

simulated annealing, Sei., vol. 220, pp. 671 68 0, May 13, 1983.

NY ), 1992 , pp. 17-21.

39, pp. 799-814, NOV . 1992.

ing (DSP) technologies. In many high-speed applications, general-

purpose computers (even the parallel ones) are far from satisfactory

for real-time processing of digital signals. Application-specific VLSI

circuits, especially. those with iterative-log ic-array (ILA) structu res,

offer affordable solutions to such applications. This investigation in

turn boosts research concerned with ILA testing.

The general logic testing problem is known to be N P - c o m p le t e

[l].

For ILAs, however, the testing problem usually is much easier

to cope w ith. The research on ILA testing dates back at least as far as

1967 [2], and has been going on stead ily ever since [3]-[16]. In short,

their research has mostly been focused on the following two areas:

1) seeking (sufficient) conditions that categorize testable ILAs and

proposing design-for-testability (DFT) approaches, and 2) developing

test generation algorithms for ILAs. We call an array testable with

a constant test set a C-tes table array.

Manuscript received February 15, 1993; revised January 14, 1994. This

work was supported in part by the National Science Council, Taiwan, R.O.C.,

under Contracts N SC80-0404-E007-02 and NSC80-0404-E007-33.

S.-K. Lu was with the Department

of

Electrical Engineering, National Tsing

Hua University, Hsinchu, Taiwan. He is now with the Department of Electrical

Engin eering , National Taiwan University, Taipe i, Taiwan.

J.-C. Wang was with the Department

of

Electrical En gineering, National

Tsing Hua University, Hsin chu, Taiwan. He is now with the Computer and

Communication Laboratory, ITRI, Hsinchu, Taiwan.

C.-W. Wu is with the Department

of

Electrical Engineering, National Tsing

Hua University, Hsinchu, Taiwan.

IEEE Log Number 9408379.

1063-8210/95$04.00

.O

1995 IEEE

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INTEGRATION (VLSI) SYSTEMS,

VOL.

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In this paper we propose DFT techniques for ILA's based on

particular C-testability conditions

[

141 which results in a minimal

constant number of test patterns. Our technique applies to ILA's

with an arbitrary dimension, and even to arrays with various other

connection types, e.g., hexagonal or octagonal ones. Bilateral ILA's

are also discussed. We can make non-C-testable arrays C-testable

by using a truth-table augmentation technique. To illustrate our

approach, we give a CMOS systolic array multiplier as an example,

and show that an overhead of no more than

5.88%

is sufficient

to make it C-testable. It requires only

18

test patterns to achieve

100% single-cell-fault coverage regardless of the word length of the

array multiplier. Our technique guarantees that the test set is easy

to generate, and the corresponding BIST structure requires smaller

hardware overhead and has a more regular structure.

11.

C-TESTABLE ILATERALTERATIVEOGICARRAYS

We follow the definitions given in [14]. A

cell

is a combinational

machine

(E,

A , # ) , where f

: C

-+

A

is the cell function, and

C

= A = (0, l} .

An iterative logic array (ILA) is an array of

cells. We use the terms

array

and

I L A

interchangeably. An ILA is

unilateral when signals propagate in only one sense with respect to

each axis. It is bilateral when signals propagate in both directions

with respect to some axis. We denote the array as

A (

f

).

We say

that an array is 2 -testable when it is testable with 2 patterns

regardless of the array size, where s the input/output word length

of a cell. A

minimal complete exhaustive)

nput sequence

U

for a cell

is an input sequence consisting of

all

possible input combinations for

the cell, i.e.,

U

is a permutation of

( T I , 0 2 .

.

, ~ W ,

where the

0 , ' s

are the distinct input words. A minimal complete output sequence

6 is defined analogously. We say that f is x-injective when V j ,

V ~ I

i z

f i l , j )# f ( i 2 , j ) . We say

f

is x-bijective if it is x-

injective and C

= A ,

where

f

is the x-projection of f (i.e.,

f

: C

x

Cy A ).

Note that if

A y

= 0 hen we also may say

f (instead of f ) is 2-bijective. Y-injective and y-bijective are

defined analogously.

We assume that the cell's behavior is invariant over time, even if it

is faulty. That is, we are testing for combina tional faults-faults that

will not turn a combinational cell into a sequential one. For detecting

sequential (e.g., CMO S stuck-open) faults, we have developed a novel

technique which can be found in [16]. We do not consider pattern-

sensitivity or bridging am ong cells either. To completely test an array ,

therefore, it suffices to verify the function of every cell in the array.

Verifying a cell function involves generating inputs for the cell and

propagating outputs from the cell to external outputs. A faulty cell is

a combinational machine (E ,

A, f'),

where f '

:

C

- A

and f #

f .

This model is called the cell aul t model, which has been used as the

cell-level fault model by most researchers working on ILA testing.

We also assume that there is at most one faulty cell in the array, i.e.,

the single

cell

fault model is adopted.

It has been shown in

[

141 that a k-dimensional

I L A

is C-testable

if

it has a bijective cell unction, where

b

is an arbitrary positive integer.

A

2-D +45 tessellation is shown in Fig. 1[3]. The w hole array can

be pseudoexhaustively verified with only 2 tests regardless of how

many cells there are in the array (i.e., it is 2 -testable) if the cell

function is bijective.

Bilateral arrays have been discussed in

[81,

[ 9 ] ,

[171, [141, [Is].

We now propose a simpler scheme for C-testable bilateral arrays.

Fig. 2(a) shows a 1-D bilateral array in which

Cy = A y =

0. The

cell notation is shown in Fig. 2(b). In the figure,

xl

and

cT

denote the

left-bound and the right-bound inputs, respectively;

1

and

i,

denote

the left-bound and the right-bound outputs, respectively.

Bilateral arrays in general are much harder to deal with. All known

methods are complicated and difficult to implement. Our strategy is

.

J S J ,

Fig.

1.

A 2-D +45" tessellation.

- 1 ' 2 3 - +

I31

Fig.

2.

(a) A bilateral ILA of combinational cells. (b)

The

cell.

to make bilateral ILA's unilateral, and use the techniques developed

for unilateral ILA's. In Fig. 2(a), let 01

= ( I l r , 1 2 , )

be a minimal

complete input sequence of

celll.

Since

f

is bijective, the output

sequence uz

= (1zr,I1,)

should also be minimal complete, where

I z , is transmitted to xr of cell2 directly. If we c an apply 3

= 111

to

11

of cellz, hen cell2 receives a minimal complete input sequence.

It then produces a minimal complete output sequence

03 = 13r, 21 .

The recursive definition of 121 clearly hinders the realization of this

idea. To tackle it, we put a multiplexer in front ofkach cell which

selects the input for the cell, either from

21

of its left neighbor

or

from

2 1

of its right neighbor. By doing

so,

cell, receives a minimal

complete sequence

U =

( l t , , I ~ z - l ~ l ) V i .

he

il

output of

cell,

(the

rightmost cell) is routed to the left primary output in test mod e. If this

ILA is fault free then the left and right primary output terminals will

produce a correct complete output sequence. The idea is illustrated

in Fig. 3(a). The multiplexers

are

marked

M,

which are controlled by

a mode selection signal that indicates whether the ILA is in test

or

normal mode. When it is in normal mode, all the multiplexers take

the normal inputs coming from their direct predecessors. If it is in

test mode, the multiplexers take the inputs coming from their direct

successors, except for the boundary cells. The test path is highlighted

in the figure. The width of the routing channel is constant. It is clear

that the test path turns the array unilateral. Therefore, a bilateral ILA

with a bijective cell function can be ma de 2 '-testable in this way.

The approach shown in Fig. 3(a) has a drawback in test mode: there

exist two global wires. One is from the right primary input to Z I of

celll, and the other is from PI of cell, to the left primary output.

Their lengths grow with respect to

n,

the array size. An alternative

configuration is shown in Fig. 3(b). Extra input and output terminals

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II

I I'

I

I

4

(b)

Fig.

3.

(a) Modified ILA. (b) An alternative configuration.

(b)

Fig. 4.

(a) A linear bilateral ILA with vertical output. (b) The basic cell.

are included to eliminate the long wires, which in turn reduce the

propagation delay. The routing channel width is reduced 50 , and

the number of multiplexers is reduced from n + 1 to n. It should be

noted that the pin count usually is very small in 1-D ILA's, so these

extra

YO

terminals can hardly create any problem.

In Fig. 4(a), a linear bilateral ILA with vertica l I/O

is

shown.

The cell notation is shown in Fig. 4(b). Let the cell function be

f : C ' x CzTx Cy A.1 x A"? x Ay.T h e x - p r o j e c t i o n o f f ,

fAz

x

E .

x

Cy + A"

x

A"., is defined as f z ( i r , i l , j ) =

i r , i l ) ,

where

f(&., i l , j)

= & . , ; l , j ) . The y-pro jec t ion of f is

defined analogously. We say that f s x -b i j ec t iv e w hen V j E Cy

and

Axl

x A ? = E ' x

C Z r .

Observation Let A f ) be a linear bilateral ILA as shown in

Fig. 4, with cell function

f .

Then A ( f ) an be made C-testable by

adding multiplexers to the cells in the same manner as shown in

Fig. 3(a) if f is bijective,

or

f is x-bijective.

A linear ILA bears a n atural resemblance to a finite state machine

(FSM), i.e. , it may be used to model an FSM. We may view the

x signals as the state variables, and the

y

signals as the external

inputs/outputs of the FSM. C onsider the linear bilateral array A(

f )

as shown in Fig. 4 again. Its function may therefore be represented

in the form of a state transition table, such as the one shown in

Fig. 5(a). The state transition table has a 1-to-1 correspondence to

a state transition diagram, as shown in Fig. 5(b). Since we view the

x signals as the state variables, the state transition diagram is called

an x-transition

graph.

Observation

If the linear bilateral array has a zero initial state and

an Eulerian 2-transition graph, then the controllability of the array is

100% within a test sequence of length 2 .

V ( i l r r i l l ) ( i 2 r , i 2 1 ) E C X 1

C X T ,

( i l r , i l I , j ) # f 2 ( i 2 r , i 2 1 , j )

Of0Q

W

(b)

Fig.

5 .

corresponding state transition graph.

(a) A state transition table

of

a linear bilateral ILA. (b)

The

Proof:

Fig. 5(a) depicts a state transition table of an ILA which

satisfies our conditions, i.e., its corresponding z-transition graph is

Eulerian (see Fig. 5(b)). The property of an Eulerian graph implies

that there exists a cycle in the graph spanning all edges (i.e. , covering

all state transitions), which further implies that all possible input

combinations for the cell can be generated by a minimal complete

input sequence. The length of the Eulerian cycle clearly is 2 . Now

consider the whole array. Since it has a z ero initial state, we can begin

with this state, for each and every cell in the array, and traverse the

Eulerian cycle once. Then each cell receives a minimal complete

input sequence simultaneously: all the cells go through an identical

state transition sequence.

Observability is not guaranteed. We can, however, introduce

exclusive-NOR gates in each cell to compare the internal neighboring

xl signals. They should remain equivalent at any time. Since the cell

function is a bijection (implied by the Eulerian 2-transition graph),

any fault can be propagated to some observable outputs (provided

that the

XOR

gates

are

included). Since the length of the Eulerian

cycle is 2 , the entire array is 2 -testable.

The above discussion can be generalized to multidimensional

arrays in a straightforward way. For example, a 2-D bilateral array

A ( f ) as shown in Fig. 6(a) can be m ade 2 -testable by adding

multiplexers and test paths as shown in Fig. 6(b) if

f

is bijective.

Note that if multiplexers are used for mode control, they cannot

be fully tested in test mode. Usually an all-0 and an all-1 input in

operation mode can be used to test the m ultiplexers (in this case the

extra test inputs should be assigned the complement value

to

cover

possible stuck-at faults on the mode-selection control line). Therefore,

the number of test patterns is still a small constant.

111. BIJECTIVITY

ODIFICATION

If the cell function satisfies the bijectivity condition, then the testing

of the array clearly is easy. If it does not, then we c an use a truth-table

augmentation technique which modifies the cell function to make it

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1

52

J3

(b)

Fig. 6.

array.

(a) A bilateral 2-D array with a 45O tessellation. (b) The modified

bijective. Instead of modifying the flow table as shown in [18], we

modify the truth table. The modification results in a circuit that has

two modes:

o p e r a t i o n

and

tes t

[14].

Test Mod e:

The added wires are treated as ordinary

U 0

ires. The

cell function is then bijective, and can

be

tested easily. If we add c

input bits, then the number of test vectors will be 2 +=, where s

the original number of input bits.

Operation Mode:

Ground the added input wires and neglect the

added output wires. The modified cell then operates as the original

one.

The heuristic algorithm for our output assignment is based on a

simple

goal-reflection

or

complementary reflection

(defined below).

Our goal is to find an output assignment of the new (i.e., augmented)

truth-table such that the new function has the simplest logic. It is

well known that

an

array can be used to simulate a finite state

machine (FSM). The output assignment problem of the cell truth-

table described here however is different from the state assignment

problem of the FSM as depicted in [19].

The entries in the original

truth-table cannot be altered (reassigned), i.e., they are constants for

a given function (while states are variables). Although the goal of

simplifying the logic is the same, the degree of freedom in our

assignment problem is different: it lies in the large amount of ways

to fill up the holes in the right-hand side of the expanded truth-table

such that the new function is bijective.

For ease of discussion, and without loss of generality, we assume

that there are

no

more than two identical entries in the output part

of

the original truth table, i.e., only one extra input bit

2)

and one

extra output bit

( 2 )

are added. We also assume that the truth tables

are fully expanded, i.e., there are no don't-care terms. In reality,

don't-cares can be assigned in an arbitrary way. We of course will

assign them such that the number of identical output words is as

small as possible (or even disappear). If

N

is a feasible assignment

of values for the entries of the augmented truth table, then

c y u

(&

resp.) denotes cy confined to the input (output resp.) variable v (6

resp.), i.e.,

cyu (&

resp.) assigns only the values for

v

(6 resp.).

The assignment

cy

confined to the upper half of the table is denoted

no

he assignment confined to the lower half is

cy1.

An assignment

au

for an input or output variable

ZI

is said to be

reflexive

if in

the augmented truth table, the values assigned by cy: are one-to-

one corresponding to those assigned by

ab

It is

complementarily

reflexive,

or simply

complementary.

if the assigned values by CY: are

one-to-one corresponding to the complement of those assigned by

at .

On the augmented truth-table, each input variable

v

# z always

has a reflexive assignment, while

z

has a complementary one.

We therefore are mainly concerned with the assignment for the

output variables. In what follows, w denotes the word length of

the modiJied cell, i.e., the original cell word length

is

w

-

1.

The cell input is assumed to be represented by the w-bit word

uU,--1vw--2

. .VIZ while the cell output is represented by the word

vW-1v

w-2...v1z.

Also,

cy;_-1

and

Ci.

E

o:w l

. . .

a:,.

The following observation describes a

necessary condition which must be true for any feasible assignment.

Observation:

In the augm ented truth table, each column contains

Pro03

Since

no

don't-cares are allowed in the table, there are

2 rows wh ich, in the input part, represent all of the

2

possible

words. And the fact that the modified cell function is a bijection

results in the appearance of all possible

2 words at the output part

of the augmented truth table. The observation follows directly.

Our first step is an initial assignment of

& '

(and hence

):

V i

=

I r 2 , . . . , w - 1,

if the number of

1 's

equals the number of

0's

in

then assign

cy:%

exactly as

a:,,

(reflexive), else assign

akt

as the complement of

cy:,

(complementary). This initial assignment

of

Ci.

conforms to the condition stated in the above observation.

The reason for a reflexive or complementary assignment is clearly

illustrated in the following example. It ends up with a very small

amount of hardware overhead. A reflexive assignment

cyc,

implies

that the output function

6,

remains the same as in the original cell,

so no

extra device is required.

We apply the algorithm to the 2-D systolic-array multipliers, and

it gives a very good result-only two extra transistors, or 5.88%

overhead. A 2-D array for pipelined carry-save multiplication is

shown in Fig.

7

[2O], [21]. The cell function is given as follows

-

. . * ^

iy t w _ ,

1's and

2 - l

0's.

w 1

= a

b = b

i e c 6 a . b

E = s . c + c . a . b + s . a . b

where

a

and

b

represent the multiplier and multiplicand bits, s is the

s um m an d b it , F d c is the carry bit. Their respective output bits are

denoted as

, b , i

and

e

respectively, which are propagated to the

next stage. From the truth table we see that the cell function is not

bijective. For example, the inputs

0,

O,O, 1) and O , O , 1 , O ) map to

the same output O , O , 1 , O ) . We add an extra input

z

(in the third

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(b)

Bit-parallel pipelined multiplier

array

and the cell function.

ig.

7.

dimension) and a corresponding output to the cell, and modify

the cell function as given in Fig. 7.The modified function clearly is

bijective, and is given as follows

& = a

b = b

i = s @ c @ a . b

i

= s. +

c

.

a .

b

+

s.

a .

)

.,z

The function modification is based

on

the procedure described

above, where ,

b ,

i re reflexive assignments, and is complemen-

tary. The extra output

i

an be assigned any element in

2 = {s,e} .

A

typical CMOS implementation is shown in Fig. 8.Fig. 8(a)

shows the original cell with 34 transistors. Fig. 8(b) is the m odified

cell which has 36 transistors-an overhe ad

of

only 5.88 in terms

of transistor count. In the modified function, there are only one extra

input bit and one extra output bit need to be added. The reason is

C

i

C

b a

C

b

(b)

Fig. 8.

CMOS

cell circuits: (a) before and (b) after function modification.

that no three different inputs map to the same output in the original

function. The word length of the modified cell function is

5.

The

resulting num ber of test patterns is 32 for the e ntire array, regardless

of its size.

The truth-table augmentation technique is general. For the array

multiplier, we propose yet another technique to m ake the cell function

bijective in test mode. There is no extra input or output needed,

so

the resulting number of test patterns is only 16. The output column

violating bijection is i.. We modify a;-and obtain the modified cell

function as shown in Fig. 9(a). We use the CMOS implementation

as shown in Fig. 9(b), where a multiplexer (M) is inserted. This

multiplexer is controlled by a mode selection signal that indicates

whether the

ILA

is in test or normal m ode. If it is in test mode, the

multiplexer takes its input from s, and

= s,

so the cell function

is bijective, and the multiplier is C-testable according to Theorem

1. When it is in normal operation mode, the multiplexer takes the

normal input.

The highlighted line segment in Fig. 9(b) is not tested in test mode.

In order to increase the fault coverage, we test this line by applying

the pattems (0,

0, 0, 0)

and (I , 1, 1,

I )

to the cell, which detect

stuck-at-1 and stuck-at-0 faults on the line, respectively. Parallel

testing of the cells and automatic fault propagation by these two

tests are guaranteed. Only 18 patterns are required to test the w hole

multiplier array, as compared to 32 using the original method. The

area overhead is only slightly higher than the original method (Fig.

8),

since no extra

2

input and output are required. The pin number and

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(b)

Fig. 9.

modification.

Alternative CMOS cell circuits: (a) before and (b) after function

word length are reduced, which results in an actually lower hardware

overhead.

We now describe our built-in self-test schemes. Based on the

test pattern tessellation shown in Fig. 1, a BIST structure is given

in Fig. 10, where the array is assumed to be C-testable. In the

figure, extra circuit elements and wires are highlighted, and only

the test pattern generation and routing mechanism is shown. The test

generator is marked

G,

which is simply a binary counter that counts

from 0 to 2 - 1. Note that the counters length is w 4 or the

above example), which is very small as compared to the conventional

approach (in which case the pseudorandom pattern generators size

grows with respect to the array size). The multiplexers

are

marked

Ai

which are controlled by a mode-selection signal that indicates

whether the circuit is in test or normal mode. Conside r the ILA show n

in Fig.

10.

If it is in test mode, all multiplexers take the inputs which

are highlighted. Therefore, if the pattern generator (G) generates a

minimal complete input sequence I I , 1 for

c e l l l l ,

all other cells

subsequently receive their own minimal complete input sequences.

When it is in normal mode, all multiplexers take the inputs which

are drawn in thin line segments, i.e., the test paths are disabled, and

the array returns to normal operation.

IV. CONCLUSIONS

We propose

DFT

techniques based on our C-testability concept.

Our techniques apply to ILAs with an arbitrary dimension, and arrays

Fig.

IO.

BIST structures for a C-testable 2-D L A .

with various other connection types, e.g., hexagonal or octagonal

ones. We can make non-C-testable arrays C-testable by using a truth-

table augmentation technique. We give a systolic array multiplier as

an example, and show that an overhead of no more than

5.88%

is

sufficient to make it C-testable. With our approach , design automation

of C-testable ILAs and their BIST structures can be done easily.

Judged from the test time and the hardware overhead, our approach

is better than the scan-path approach.

Our approach

also

may be applied to VLSI data paths. Built-in

testing and testable design of VLSI data paths are other important

issues. Some work has been done in this area (see, e.g., [22]-[26]).

Since data paths are usually heterogeneous and irregular, their testing

is difficult in general.

No

single approach has been found that

effectively and efficiently applies to the whole data path of a

VLSI processor chip. A more feasible way of doing this is to

adopt different approachs or methodologies for different modules

in the data path [23]. The divide-and-conquer strategy resembles

the pseudoexhaustive technique [27], in which the whole circuit is

partitioned into modules-each being verified exhaustively. In the

data path, certain modules

are

inherently of, or can be p artitioned into,

array structures, e.g., arithmetic arrays in the ALU. The techniques

presented in this paper can be used in conjunction with the I-path

[23], [24], the T-p ath [25], and the F -pa th [26] approaches to make

BIST of VLSI data paths much easier.

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