Date post: | 14-Apr-2018 |
Category: |
Documents |
Upload: | vijay-preetham |
View: | 219 times |
Download: | 0 times |
of 28
7/30/2019 01 Digital Logic Transistors
1/28
7/30/2019 01 Digital Logic Transistors
2/28
7/30/2019 01 Digital Logic Transistors
3/28
CMPE12 Summer 2009 01-3
The Transistor: Past and Present
7/30/2019 01 Digital Logic Transistors
4/28
CMPE12 Summer 2009 01-4
Moores LawThe number of active components per chip will double every 18 months.
7/30/2019 01 Digital Logic Transistors
5/28
CMPE12 Summer 2009 01-5
GPU Speed Compared to CPU
7/30/2019 01 Digital Logic Transistors
6/28
7/30/2019 01 Digital Logic Transistors
7/28CMPE12 Summer 2009 01-7
How big is a transistor?
If a CPU die were as big as this wholeclassroom
A transistor would be
7/30/2019 01 Digital Logic Transistors
8/28
7/30/2019 01 Digital Logic Transistors
9/28
7/30/2019 01 Digital Logic Transistors
10/28CMPE12 Summer 2009 01-10
p-type MOS transistorp-type is complementary to n-type
when Gate has positive voltage,open circuit between #1 and #2(switch open)
when Gate has zero voltage,short circuit between #1 and #2
(switch closed)
Gate = 1
Gate = 0
Terminal #1 must beconnected to +2.9V in
this example.
7/30/2019 01 Digital Logic Transistors
11/28
7/30/2019 01 Digital Logic Transistors
12/28CMPE12 Summer 2009 01-12
Digital Values for Analog Signals
Use the switch behavior of MOS transistors to
implement logical functions: AND, OR, NOT
Digital symbols:
We assign a range of analog voltages to
each digital (logic) symbolAssignment of voltage ranges depends on
electrical properties of transistors being used
7/30/2019 01 Digital Logic Transistors
13/28
7/30/2019 01 Digital Logic Transistors
14/28
7/30/2019 01 Digital Logic Transistors
15/28CMPE12 Summer 2009 01-15
Truth Table
The most basic
representation of a logicfunction
Lists the output for allpossible input
combinations How many rows of the
truth table needed? 2#inputs
X Y A B
OutputsInputs
X Y A B
OutputsInputs
7/30/2019 01 Digital Logic Transistors
16/28CMPE12 Summer 2009 01-16
Truth Table: Inverter
Inverted signals are
denoted with an overbar Or with a prime symbol
A
Input Output
A Y = A
7/30/2019 01 Digital Logic Transistors
17/28
7/30/2019 01 Digital Logic Transistors
18/28
7/30/2019 01 Digital Logic Transistors
19/28CMPE12 Summer 2009 01-19
AND gate
Add an inverter toa NAND.
A B C
0 0 0
0 1 0
1 0 0
1 1 1
7/30/2019 01 Digital Logic Transistors
20/28
7/30/2019 01 Digital Logic Transistors
21/28CMPE12 Summer 2009 01-21
NOR Gate: NOT-OR
A B C
0 0 1
0 1 0
1 0 0
1 1 0
Note: Serial structure on top, parallelon bottom.
7/30/2019 01 Digital Logic Transistors
22/28
7/30/2019 01 Digital Logic Transistors
23/28
7/30/2019 01 Digital Logic Transistors
24/28
CMPE12 Summer 2009 01-27
Synthesis of AOI Gates
AOI means AND-OR-Invert
Truth table to a AOI gate (transistor-level)
Recall:
PMOS (with the bubbles) on top
NMOS (no bubbles) on bottom
Series structure makes AND
Parallel structure makes OR
7/30/2019 01 Digital Logic Transistors
25/28
7/30/2019 01 Digital Logic Transistors
26/28
7/30/2019 01 Digital Logic Transistors
27/28
CMPE12 Summer 2009 01-30
Synthesis of AOI Gates
Method 2: Sum of products for Y
Cover the zeros
Build pull-down branch first, using asserted inputs
Derive pull-up branch as a dual of the pull-downbranch
Y= VDD
Y
VSS
A B C Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
7/30/2019 01 Digital Logic Transistors
28/28