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ON-CHIP ESD PROTECTION CIRCUIT DESIGN WITH NOVELSUBSTRATE-TRIGGERED SCR DEVICE IN SUB-QUARTER-MICRON CMOS PROCESS

Ming Dou Ker and Kuo Chun Hsu

Integrated Circuits Systems Laboratory, Institute of ElectronicsNational Chiao Tung University, Hsinchu, Taiwan

ABSTRACTA novel design concept totur on the SCR device by

applying the substrate-triggered method is first proposed inthe literature for effective on-chip ESD protection design.To avoid the transient-induced latch-up issue, the substrate-triggered SCR devices are stacked in the ESD protectioncircuits. The turn-on efficiency of SCR can be greatlyimproved by applying the substrate-triggered method. Theon-chip ESD protection circuits designed with thesubstrate-triggered SCR devices for input pad, output pad,and power pad have been suc cessfilly verified in a 0.25-pmCM OS process. The substrate-triggered SCR device with a

smaller layout area of only 40pmx20pm can sustain theHBM ESD stress of higher than 7kV.

1. INTRODUCTIONTo provide effective electrostatic discharge (ESD)

protection for CMOS ICs, the on-chip ESD protectioncircuits have to be added around the input, output, andpower pads of the CMOS ICs. The lateral Silicon

ontrolled Rectifier (SCR) device was therefore used in theinput (or output) ESD protection circuits to effectivelyprotect the CMO S IC against ESD damage [l ]. Due to thelow holding voltage (Vhold, about -l V in general CMO Sprocesses) of SCR d evice, the power dissipation (PowerG

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Such a STSCR device has been drawn in layout andfabricated in a 0.25-pm CMOS process. The experimentalsetup to measure the I-V characteristics of the STSCRdevice is illustrated in Fig.3(a), and the measured results areshown in Fig.3(b). The trigger current that applied into thetrigger node has a step of1mA in Fig.3(b). When theSTSCR device has no substrate-triggered current (Ibias=O),the STSC R is turned on by its N-well to P-substrate junctionbreakdown. In Fig.3(b), the switching voltage of thefabricated STSCR device is as highs 22V, when thesubstrate-triggered current is zero. But, the switchingvoltage of the fabricated STSCR device is reduced to only9V, when the substrate-triggered current is5mA. Moreover,the switching voltage of the fabricated STSCR device isreduced to only1.85V, which almost equals to the holdingvoltage -1.35V) of the STSCR, when the substrate-triggered current is increased to8mA. So, the STSCR canbe triggered on by applying the trigger current into thistrigger node. The dependence of the switching voltage ofthe STSCR device on the substrate-triggered current isshown in Fig.4. The higher the substrate-triggered currentleads to a much lower switching voltage in the STSCRdevice.

2 S T S C R

T

1

--- - --3 ----Voltage 5Vldiv. )

b)Fig.3 a) The experimental setup used to measure theI-V curvesof the STSCR device, and(b) the measured I-Vcurves of theSTSCR device.

With a lower switching voltage in the STSCR device, theturn-on speed of STSCR device can be further improved toquickly discharge the ESD current. This isa very excellentfeature of this STSCR device for using in the on-chip ESDprotection circuits. However, another issue of using the SCR

device as the ESD protection device is the transient-indlatch-up concern[SI, when the IC is under normal circoperation. Therefore, the total holding voltage of the protection circuit with the SCR devices must be desiggreater than the maximum voltage level of VDD innormal circuit operating condition to avoid the latcissue. This can be achieved by stacking the STSCR devin the ESD protection circuits. Fig.5 shows the dependenof the total holding voltage on the temperatures ofSTSCR devices with different number of stacked STdevices. The total holding voltage will become smawhen the operating temperature is increased, becausecurrent gain p) of the parasitic bipolar transistor in the Sdevice is increased with the increase of operatemperature. But, the total holding voltage can be still raup by increasing the number o f the stacked STSCR devSuch stacked STSCR devices can be simultaneotriggered on, when the trigger currents are simultaneoapplied into the trigger nodes of the STSCR devices.

0 2 4 8 8 10

S u b s t r a t e - Tr i g g e r e d C u r r e n t m A )Fig.4substrate-triggered current in theSTSCR device.

Dependence of the switching voltage of he STSCR on the

jc_- - - - - - - - - -*S T S C Rt2 a BO 8 1 0 0 l20

Te m p e r a t u r e O C )Fig.5

of the stacked STSCR devices with differentstacked number.

The temperature dependenceon the total holding voltag

3. ON-CHIP ESD PROTECTION DESIGN

3.1 ESD Protection Design fo r the InpuUOutput PadsThe ESD protection circuits for input and output p

realized with the stacked STS CR devices, are shown in 6(a) and 6(b). All the p-trigger nodes of the stacked ST

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(a) (b)Fig.6 The ESD protection circuitsfor the (a) input pad, and (b)output pad, by using the proposed STSCR devices in stackedconfiguration.

3.2 ESD Protection Design fo r the Power RailThe STSCR device can be also applied to design the

power-rail ESD clamp circuits. The VDD-to-VSS ESDclamp circuit realized with the stacked STSCR devices isshown in Fig.7. The number of the stacked STSCR devicesbetween the VDD and VSS power rails is dependent on themaximum voltage level between the VDD and VSS in thenormal circuit operating condition to avoid the latch-upissue. The function of the ES D-detection circuit is similar tothe ESD-detection circuit used in the I/O pads, but the RCisdesigned with a time constant of about-Ips to distinguishthe VDD power-on event (with a rise time of -ms) orESD-stress events (with a rise time of -ns). During normalVDD power-on transitionfrom low to high), the inputof

devices are connected to the outputof the ESD-detectioncircuit, which is formed with a resistor and an inverter.The input of the inverter is connected to VDD through theresistor R. The resistor R is better realized by using thediffusion resistance for the concern of antenna effect[9]. Acapacitor C is placed between the input of the inverter andVSS. This capacitor can be formed by the parasiticcapacitance at the input nodeof the inverter. In the normalcircuit operating condition with VDD and VSS powersupplies, the input of the inverter is kept at VDD. T herefore,the output of the inverter is biased at VSS due to the turn-onof NMO S in the inverter. The p-trigger nodes of the stackedSTSCR devices are biased at VSS by the output of theinverter,so the stacked STSC R devices are guaranteed to bekept off in the normal circuit operating condition.

When the positive-to-VSS ESD stress zapping on thepad, the input of the inverter is initially kept at zero, and theinverter is biased by the ESD energy on the pad. The RC inthe ESD-detection circuit is designed to keep the input ofinverter with a relative low voltage level during the ESDstress condition. Thus, the outputof the inverter is chargedup to high by the ESD energy to generate the trigger current

into the p-trigger nodes of the stacked STSCR devices.Therefore, the STSCR devices are turned on by the triggercurrent generated from the inverter output, and the ESDcurrent is discharged from the pad toVSS through thestacked STSC R devices.

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the inverter in Fig.7 can follow up in time with thepower-on VDD signal, so the output of the inverter is keptat zero. Hence, the stacked STSC R devices are kept off anddont interfere the functions of internal circuits.

When a positive ESD voltage is applied to the VDD pinwith the VSS pin relatively grounded, the RC delay willkeep the input of the inverter at a low voltage level for along time, therefore the output of the inverter will becomehigh to trigger the stacked STSCR devices. While thestacked STSCR devices are triggered on, the ESD current isdischarged from VDD to VSS through the stacked STSCRdevices. By suitable design on the ESD -detection circuit, thestacked STSCR devices can be quickly triggered on todischarge the ESD current.

VDD

c T I- +,TSCR-K

lntemalcircuits

vssFig.7 The VDD-to-VSS ESD clamp circuit realizedwt thestackedSTSCR devices.

4. EXPERIM ENTAL RESULTSThe proposed ESD protection circuits have been

designed with different number of stacked STS CR devicesand fabricated in a 0.25-pm CMOS process. The human-body-model (HBM) and machine-model (MM) ESDstresses are applied to the ESD protection circuit to verifythe ESD robustness of the design shown in Fig.7. The ESDtest results are compared in Fig.8. Because the total holdingvoltageof the stacked configuration between the VDD andVSS pow er rails is increased with the number of the stackedSTSCR devices, the HBM and MM ESD levels of the ESDprotection circuit is decreased with the increase on thenumber of the stacked STSCR devices. However, it is stillhigh enough for ESD protection. If the ESD protectioncircuit is realized with 3 stacked STSCR devices for 3-V ICapplications, the HBM (MM) ESD robustnessis as high as7.5kV (725V), where each STSCR device is realized with alayout area of only 40pmx20pm in the 0.25-pm CMOSprocess. This has verified the excellent area-eficiency ofthe ESD protection circuits realized with the proposed

stacked STSC R devices.In order to investigate the turn-on efficiency of the ESDprotection circuit realized with the stacked STSCR devices,a voltag e pulse with a pulse width o f 40011s and a rise timeof lOns is applied to the VDD of Fig.7. First, onestand-alone STSCR device without ESD-detection circuit istested. The STSCR cannot be triggered on until the pulse

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height of the applied voltage pulse is increased up to 20V.After the triggering on, the voltage level on the VDD line isclampe d to -2.4V. The voltage wave form on the VDD lin e,clamped by the stand-alone STSCR device without ESD-detection circuit, is measured and shown in Fig.9. Becauseof the internal output resistance of the pulse generator andthe turn-on resistance of the STSCR device, the clampedvoltage (-2.4V) is greater than the holding voltage (-1.35V)of a STSCR device measured in Fig.3.

O= n o

2 0

18

I S :: I 4 -

l 1 2 ;

= 0 5 0

I- O - t o - z o v t r i g g e r v o l t a g e I. I I

II

I

rh

II

3 S T S C R

2 S T S C R

1 S T S C R

o 100 2 0 0 3 0 0 4 0 0 5 0 0

T i m e n s )Fig.10 The measured voltage waveformsat the VDD lineclamped by the ESD protection circuit with ESD-detection circuitand different number of stacked STSCR devices.

On the contrary, even if the ESD protection circdesigned with multiple stacked STS CR devices, the voltpulse with a smaller pulse height can trigger on the Eprotection circuit if there is the ESD-detection circuitFig.10, a 0-to-5V voltage pulse waveform applied on VDD line is clamped to 1.6V (3.2V) by the ESD proteccircuit with one (two) stacked STSCR dev ices and the Edetection circuit.A 0-to-8V voltage pulse, applied to tESD protection circuit with three stacked STSCR deviand ESD-detection circuit, is clamped to -4.7V in FigWhen the voltage pulse is applied to the VDD pin, voltage pulse is quickly clamped to a low voltage lewithin several ns. This has successfully verified the turnspeed of the proposed STSCR devices to fast dischargeESD transient current of ESD events. The clamped voltlevel of the ESD protection circuit can be linearly adjuby changing the number of stacked STSCR devices practical applications in CMOS IC products with diffeVDD voltage levels.

5 CONCLUSIONESD protection circuits, designed with the substr

triggered SCR devices in stacked configuration, have bsuccessfully verified in a 0.25-pm CMO S process. The Eprotection circuits with the stacked STSCR devices ESD-detection circuit have the adv antages of low sw itcvoltage, low holding voltage, fast turn-on speed, occusmaller layout area, and a much higher ESD robustnwhich are very useful in CMOS IC products fabricatesub-quarter-micron CMO S processes.

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