8/11/2019 01158061

1/5

8/11/2019 01158061

2/5

The number of diodes in the stacked diodestring isdepended on the power supply voltageof CMOS ICs inapplications. To avoid the latchup issue, the total holdingvoltage will be designed greater than the power supplyvoltage. The total holding voltage V h ) of asubstrate-triggered SCR device with k-stacked diodes can

be written asV h =V h - ,+k x V, , 1)

where yhscR is the holding voltage (-1.35V) of aP-STSCR (or N-STSCR) device, andV is the cut-involtage (-0.6V) of a diode in forward-biased condition.

The P-STSCR and N-STSCR devices with differentnumbers of stacked diodes have been drawn in layout andfabricated in a 0.25-pm STI CM OS process. The DCI-Vcharacteristics of stand-alone P-STSCR and N-STSCRdevices are measured in Figs. 2(a) and 2(b), respectively.The experimental setups to measure the DC I-Vcharacteristics of the P-STSCR and N-STSCR devices arealso inserted into Figs. Z(a) and 2(b), respectively.

The dependences of the switching voltage of theP-STSCR and N-STSCR devices on the substratelwell-triggered current are shown in Figs. 3(a) and 3@),respectively. Wh en the P-STSCR device has nosubstrate-triggered current (Ibias=O), the P-STSCR isturned on by its original N-welVP-substrate junctionbreakdown. In Fig. 2(a), the switching voltage of theP-STSCR device is as high as 22V, when thesubstrate-triggered current is zero.But, the switchingvoltage of the P-STSCR device is reduced to only9V,when the substrate-triggered current is5mA. Furthermore,the switching voltage of the P-STSCR device can bereduced to only l.SSV, when the substrate-triggeredcurrent is increased up to 8mA. Without through theavalanche breakdown m echanism, the P-STSCR can betriggered on by ap plying the trigger cu rrent into its triggernode. In the N-STSCR device, it also has the similarcharacteristics asthat of the P-STSCR device.

With a much lower switching voltage, the turn-onspeed of the P-STSCR I N-STSCR device can be furtherimproved to quickly discharge the ESD current. This is avery excellent feature of this proposed ESD protectiondevice for using in the on-chip ESD protection circuits insub-quarter-micron CMOS processes. Fig.4 shows thedependence of the total holding voltageof the ESDprotection device realized by the P-STSCR with stackeddiode string on the number of diodes under differenttemperatures. With increase of the number of stackeddiodes, the holding voltage of ESD protection device israised. However, the total holding voltage slightly reduceswhen the operating temperature is increased, because thecurrent gain p) of the parasitic bipolar transistor in theSCR device is increased with the increase of operatingtemperature. For safe applications in a 2.5-V CMOS IC,two diodes must be stacked with the P-STSCR orN-STSCR devices in the ESD protection circuitsto avoid

the latchup issue in normal circuit operating cond itions.~~ ~~ ~ ~~

I ...sl I

' . . . i , , ,

(a) (b)Fig. 2 The experimental setups andthe measured DC I-Vcurves of (a) the P-STSCR device, and (b) the N-STSCR device,fabricated in a 0.25-pm shallow-trench-isolation (STI) CMOSprocess.

I 10 2 1 IO s 2 1 $0

(I t&.IDiDo*.d c-I nul W d I T n n s M C u m l l n U ,

(a) (b)Fig. 3 Dependences of the switching voltage of (a) theP-STSCR deviceon the substrate-triggered current,and b) theN-STSCR deviceon the well-triggered current.

I I0 1 2 1 , 5 1 1

Numb.rOfDl&

Fig. 4 Dependence of the total holding voltage of theP-STSCR with stacked diode string on the number of stackeddiodes under different temperatures.

111. ON-CHIP ESD P R O T E C T I O NDESIGNA. ESD protect ion designsfor U 0 a d

The ESD protection circuits forVO pad, realized withthe complementary substrate-triggered SCR devices, areshown in Figs. 5(a) and5 @ . In Fig. 5(a), the p-trigger(n-trigger) node of the P-STSCR (N-STSCR) device is

230

8/11/2019 01158061

3/5

conn ected to the outp ut of the inv-1 (inv-2). The inp utofthe inv-1 (inv-2) is conn ected to VDD (VS S),thro ugh theresistor R. The resistor R is better realized by using the N+diffusion resistance for the con cern of antenna effect[9]A capacitor C is placed between the input of the inv-l

(inv-2) and VSS (VD D). This capacitor can be formed bythe parasitic capacitance at the input no de o f the inverter.In the norm al circuit operating conditions with VDD andVSS power supplies, the input of inv-l is biased at VDD.Therefore, the output of the inv-l is biased at VSS due tothe tur on of NMOS in the inv-I. The p-trigger node ofthe P-STSCR devic e is kept atV by the outputof theinv-I, so the P-STSCR device is guaranteed to be keptoffin the no rmal circuit o peratin g conditions . For inv-2in thenormal operating conditions, its gate is biased at VSS.Thus, the output of the inv-2 is kept at VDD due to thetur on o f the PMO S in the inv-2. The n-trigger node ofthe N-STSCR device is biased at VDD by the output ofthe inv-2, so the N-STSCR is also guar anteed to be keptoff in thenormal circuit operating conditions.

Under the positive-to-VSS ESD-zapp ing condition, theinput of the inv-l is initially floating with a zero voltagelevel, thereby the PMOS of the inv-1 will be turned ondue to the positive ESD voltage on the pad.So, the outputof the inv-l is charged up by the ESD energy to generatethe trigger current into the p-trigger nodeof the P-STSCRdevice.

Ther efore, the P-STSCR devic e is triggered on by the

(4 b)Fig 5 a) The ESD protection circuit designedwith thesubstrate-triggered SCR devices for the I1 0 pad. @) Themodified designo (a) to avoid latchup issue.mm

C l r n i t .b d

* . r.. P l

P

V M

(4 (b)Fig. 6 (a) Another ESD protection circuit designedwith thesubstrate-triggered SCR devices for the 11 pad. b) Themodified designof (a) to avoid latchupissue.

triggered current generated from the outputof the inv-I,and the ESD current is discharged from pad to VSSthrough the P-STSCR device. The RC time constant isdesigned to keep the inputof the inv-1 at a relatively lowvoltage level during E SD stress condition. Under negative-

to-VDD ESD -zapping condition, the input of the inv-2 isinitially floating with a zero voltage level, and theNMOSof the inv-2 will be turned on due to the negative ESDvoltage at the pad. So, the outpu t of the inv-2 is pulleddown by the negative ESD voltage to draw the triggercurrent out from the n-trigger node of the N-STSCRdevice. Therefore, the N-STSCR device is triggered on bythe triggered current generated from the output of theinv-2, and the ESD cu rrent is discharged from pad to thegrounded VDD pin through the N-STSCR device.

Fig. 5(b) is a m odified design of Fig. 5(a) to make theESD p rotection circuit latch-up free un der norm al circuitoperating conditions. The total holding vo ltage of the ESDprotection device must be d esigned greater than the pow ersupply voltage. By changing the num ber of stacked diodes,the total holding voltage can be ad justed to meet differentcircuit applications.

Fig. 6(a) shows another ESD protection circuitdesigned with the substrate-triggered SCR d evices for theYO pad. When a p ositive-to-VSS ESD zapping on the pad,the positive transient voltage on the pad is coupledthrough the capacitor C to the gate of M n. The Mn with apositive coupled gate bias can be turned on to conductsome ESD current from the pad into the p-trigger node ofthe P-STSCR devic e. Ther efore, the P-STSCR istriggered on to discharge the ESD current from the pad toVSS. When a negative-to-VDD ESD zapping.on the pad,the negative transient voltage on the pad is coupledthrough the capacitor C to the gate of M p. The Mp with a

negative coupled gate bias can be huned on to draw someESD current out from the n-trigger node of the N-STSCRdevice. Therefore, the N-STSCR is triggered on todischarge the ESD current from V DD to the pad. The RCvalue in Fig. 6(a) must be tuned at the same value, wherethe coupled voltage under normal circuit operatingconditions must be smaller than the threshold voltageofMn/Mp, but greater than the threshold voltage of Mn/Mpunder ESD zapping conditions. Fig. 6(b) is the modifieddesign of Fig. 6(a) with the stacked diodes to overcomethe latchup issue.

B. ESD protect ion design fo r the power p adThe P-STSCR / N-STSCR device can also be applied

to design the power-rail ESD clamp circuits. TheVDD-to-VSS ESD clamp circuit realized with theP-STSCR / N-STSCR device and the stacked diode stringare show n in Figs. 7(a) an d 7(b), respectively. Thefunction of the ESD-detection circuit, which is formedwith resistor, capacitor, and inverter, is similar to theESD-detection circuit usedin the input pad, but the RC isdesigned with a time constant of about-Ips to distinguish

231

8/11/2019 01158061

4/5

the VDD power-on event (with a rise time of-ms) orESD-stress events (with a rise time of -ns). During norm alVDD p ower-on transition (from low to high), the input ofthe inverter in Fig. 7(a) can follow up in time with thepower-on VDD signal,so the output of the inverter is kept

at zero. Hence, the P-STSCR device with diode string arekept off and don't interfere the functions of internalcircuits.

When a positive ESD voltage is applied to VDD pinwith VSS pin relatively grounded, the RC delay will keepthe input of the inverter at a low voltage level for arelatively long time, therefore the outputof the inverterwill be pulled high to trigger the P-STSCR devic e. Wh ilethe P-STSCR devic e is triggered on, the ESD c urren t isdischarged from VDD to VSS through the P-STSCRdevice and the stacked diode string. With suitable ESD-detection circuit, the P-STSCR device can be qu icklytriggered on to discharge the ESD current.

In Fig. 7(b), during n o m 1 VDD power-on transition,the input of the inv-1 will be biased at VDD,so the outputof the inv-1 (the input of the inv-2) will be biased at zero,therefore the output of the inv-2 will be kept at VDD.Hence, the N-STSCR device with diode string are kept offand don't interfere the functions of internal circuits.However, when a positive ESD voltage is applied to theVDD pin, the RC delay will keep the inputof the inv-1 ata low voltage level for a relatively long time, therefore theoutpu t of the inv-1 (the inpu t of the inv-2) will beco mehigh, then the output of the inv-2 will be kept at lowvoltage level to trigger the N-STSCR device. While theN-STSCR devic e is trigger ed on, theESD current isdischarged from VDD to VSS through the N-STSCRdevice and the stacked diode string.

(a) @)Fig. 7 The VDD-to-VSS ESD clampcircuit realized by (a) theP-STSCR device with stacked diode string,and (b) theN-STSCR device with stacked diode string.

IV. EXPERIMENTAL RESULTSA. ESD robustness

The proposed ESD protection devices and circuits forthe V O and the power pads have been fabricated in a0.25-pm CMOS process. The layout top views of theP-STSCR device with two stacked diodes and theN-STSCR device with three stacked diodes are show n inFigs. 8 a) and 8(b), respectively. Th e dev ice dimensions ofthe P-STSCR and N-STSCR are drawn as 20 prn x2 1pm

and each diode has a 30p mx 3pm anode layout area. Thehuman-body-model (HBM) and machine-model (MM)ESD stresses are used to verify the ESD level of theproposed ESD protection circuits designed with thesubstrate-triggered SCR devices and different number o f

the stacked diodes. The E SD test results are com pared inFig. 9.The ESD -generated power across the ESD protection

devices is Powerz EsoxVhold.Thus, the HBM and MMis decreased when the number of stacked diodes isincreased. For power supply voltage of 2.5V, the ESDprotection circuit can be free to latchup issue even if theoperating temperature is at 125 C , when the num ber ofstacked diodes is two. In this condition, the HB M (MM ) isstill as high as >8kV (6SOV), it is still high enough forESD protection. The ESD levels of substrate-triggeredSCR devices are the same as that of the traditional SCRdevice under the same layout area because of the samedischarging path and area. The aim of this literature istoreduce the switching voltage, to avoid the transient-induced latchup issue, and to enhance the turn-on speed ofthe SCR device. In comparison, for gate-groundedNMOSdevice in the same 0.25 -pm CM OS process, it consumes alarge layout area of 25.8pmx60pm to sustain the ESDlevel of on ly 3.5kV.

ag &li

~

. :.. : ~: .::..... :\:: i L:.a) (h)

Fig. 8 The layout top views of (a) the P-STSCR with twostacked diodes, and (b) the N-STSCR devicewith three stackeddiodes.

1 1 , 1 1 1H n b . r a t o k 4 .

Fig. 9 Dependence of HBM and M M ESD levels on thenumber of stacked diodes for theESD protection circuitrealizedwith the P-STSCR device and stacked diode string.

232

8/11/2019 01158061

5/5

B. h r n on verificationIn order to verify the functions of the ESD protection

circuits realized with the R,C, inverter, and P-STSCRwith stacked diode string, a voltage pulse with a pulsewidth of40 0n s and a rise time ofIons to simulate the ESD

triggering is appliedto the VDD of Fig. 7(a), which theVSS is connected to ground. InFig. 10, a 0-to-5V voltagepulse applied on the VDD is clamped to 1.6V (3.2V) bythe ESD pro tection circuit with P-STSCR and zero (two)stacked diodes. By increasing the number of the stackeddiodes, the clamped voltage o n VDD is increased.

By using this method, theturn-on efficiency o f the

I . J

Tlm. ,.,00 200 300 I D 0

Fig. 10 The measured voltage waveforms to verify the turn-onefficiency of the power-rail ESD clamp circuitin Fig.7(a) withdifferent number of tacked diodes.A 0-to-5V voltage pulse isapplied to the VDD node with the VSS grounded.

I I

(b)

0 , m m w . mTin*