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A HIGH-SPEED MAGNITUDE COMPARATORWI TH SMA LL TRANSISTOR COUNT

Shun-Wen ChengTamkang Univ., Taipei,TAIWANswcheng@ieee.org

ABSTRACTThe comparator is a very basic and useful arithmeticcomponent of digital systems. An individual, compact,high-performance, good cost-benefit ratio comparatorcore plays an important role on almost all hardwaresorters. The study proposes a tine cost-performance ratiocomparator design. Based on modified 1s complementprinciple and conditional sum adder scheme, theproposed design has small transistor count and shortpropagation delay. Post-layout simulations based onTSMC 0.6um lP3M CMOS process has completed. Itshown a 64-b static CMOS comparator of the proposedarchitecture only needs 1,556 transistors and 4.211s.Index Term- agnitude comparator, digital comparator,sorter, 1s complement, conditional sum adder, CMOS,digital IC and VLSI.

1. INTRODUCTIONSorting is one of the most important problems incomputer science. Many fundamental processes in

computing and communication systems require sorting ofdata. Sorting network play a key role in the areas ofparallel computing, multi-access memories andmultiprocessing [I], [2], [SI.

As depicted in Fig. 1 , compare and swap elementsof data are vital for sorting. In conventional computersystems, instruction COMPARE and instructionSUBTRACT often share the hardware. This can reducecost. And the time complexity is limited on O(n) of radixsort or O(n log n) of quick sort in average cases [SI.

Figure 2 displays an eight number three-levelhitonic sorter. It uses 24 comparators to attain a higherperformance target. The time complexity of n (log n) -comparator bitonic sorter is O((log n)), far better thancommon software solutions [I] , [2].

But if someone needs to process long digit integersorting, then directly design a corresponding hardwaresorter, the comparators array will become very large. Atthis time, a compact, high-performance comparator coreis very important.

max(a,b)a#; ;#bmin(a,h) h a

a P b a < bmin(a, b) a#; ;#;

ba ax(a,b) b a < b a 2 bFigure 1.Compare & swap elements are vital for sortingLevel-1 Level-2 Level -3 sub-sonerstage 1 -.tage 1 stage2 stage 1 stage2 s tage3, , , ,

. .Figure 2. A three-level bitonic sorter

Ancient magnitude comparators are shown in Fig. 3[41. The circuit compares two binary number A and B,and produces three output: A>B, A=B, A

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A>=B4(a ) I-bit magnitude comparator.

-(b) %bit comparator.

-(c) 4-bit comparator.

A,*BfYd) 16-bitcomparator.

x =0 1 0 I O 1 0 o , = 8 4 , ,Y = o I n o o n I I , = 67,,,A. X Y =01010100- 0 lOOOOll (84 >67)

O l O l O l D O =x+ 1 0 1 1 1 I Do='s CUmplementofY

~ c o u t ~ o0 1 0 0 0 0 = Sum,-.. - - --- --- -+....................... ,I@-around cany_bilJ

= CarrectAnswer: 17,"Campm0 0 0 1 0 0 0 1B.X - =01010100 - 01010100 (84= 84)

0 1 0 1 0 1 0 0 =x+ I 0 I 0 1 0 K ='s wmplementofX

I C a m p r n l 1 1 I 1 1 1 1 = Cclrrecthswer.~ C a m p ~ O0 0 0 0 0 0

+ 1 =Edarry-in bit 1

C.Y - X 01000011-01010100 (67 Y , bit Cout =1. IfX $Y, bit Cout =O. After modificalion, the schemealways adds a fixed carry, then if X L Y , bit Comp =1. IfX < Y , bit Comp =O. Thus the status of hit Comp fits theconvention of comparison. The classic designs in Fig. 3,they need two hits to express the same information, i sineffective.

In common discussions, both ONO numbers arepositive. If two numbers have different signs, directlycompare the sign bit and then the answer is obtained. Ifboth two numbers are negative, the answer is justoonosite. At this time make the fixed cam-in bit = 0.always, then the output signal Comp =Comp Cl? Sign-hit,and the condition is solved.Figure3.The classic circuit of magnitude comparators.

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Stage0 i Stage 1 Stage 2 Stage 3A7B7

ASBS

Comp = 1 , A>=B;Comp =0, A

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design The Proposed The Proposeddesignwith design withCornoaratorf I staticBit Number [41 I l lseudo-NMOS staticCMOS

64

I

1 , 522p+1 ,522n 375p+742n 7 4 2 p + 7 4 2 n

2 I 3 8 p + 3 8 n I 8 p + 1 3 n I 1 3 p + I 3 n I

32

4 0 0 ~ x 3 8 0 ~

(=72,172w)omparator,576pmx120pm(=69,120p2)TheProposed Comparator.(using static CMOS)I I I ITable 2. Transistor count and simulation comparisons

of 64-b comparator designs. (All are based on TSMC0.6um CMOS prncess.)

The total gate count of N-hit comparator is,INV x N +ANDZx N+OR2x(N- ) +Mux2fols,,,, x(N- )+M~2~~Lzb~, .b7~rz,xzC2*l)l-(N-l) Iwhere M=log N.

So the total transistor count of the 8-b static CMOScomparator is (lp+ln)x8 + (3p+3n)x8 + (3p+3n)x7 +(2p+2n)x7 + (3p+3n)x(ll-7) =79p + 7911.The totaltransistor count of N-bit static CMOS comparator is,(4p+4n)N +(5p+5n)(N - 1 ) +( 3 p +3 n ) [ x ( 2 * l)I-(N -I)where M =log N. If N =M-hit, and eighteen buffers areused for increasing driving capability, therefore the totaltransistor count is 742x2 +18x4 =1,556.

Under the proposed comparator architecture,implement AND gate and OR gate by NMOS logic, anduse pure NMOS multiplexer networks, will have thefewest transistor count but large power dissipation andslow operation speed. Complementary Pass-transistorLogic (CPL) can reduce the data skew problem andpower dissipation. We can use CPL to replace staticCMOS logic gates i n low-power low-voltage applications.The circuit easily partitions to several stage pipelines forincreasing the hardware sharing and data throughput.

1Ii *.I

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4. CONCLUSmIG REMARKSThe complexity informarion is listed in Table 1. Theauthor found the transistor count of the new design is lessthan that required in the conventional design, while the

transistor count of the new design with static CMOS isonly approximately half of the conventional design.Post-layout simulation results are summarized inTable 2. The comparisons of a:omparator design are basedupon TSMC 0.6um Single-layer Polysilicon Triple-layer

Metal (1P3M) CMOS Process Technology. The transistorcount and layout area of the proposed comparator areboth less than 1998 Chua-Chin Wangs Comparator [71and 2003 Chung-Hsun Huangs Comparator [31. And theworst propagation delay is shorter than their designs.

ACKNOWLE!DGEMENTThe author, Shun-Wen Cheng, would like to thankhis advisor Prof. Kuo-Hsing Cheng, for his previous

teaching on IC design. Prof. Cheng has already left Dept.of EE, Tamkang University, Tamsui, TAIWAN, and nowhe joins Dept. of EE, National Central University,Chung-Li, TAIWAN. One of the stars of Tamkang hasgone.. .

REFERENCES[I] K. E. Batcher, Sorting Networks and Their Applications,in Proc. AFIPS 1968 Spring Joinr Computer Conference,pp. 307-314, Apr. 1968.[2 ] Shun-Wen Cheng, Arbitrtuy Long Digit Sorter HWISWCo-Design, in Proc. Asia and South Pacific Design

Auromarion Co nj , ASP-DAC03, pp. 538-543, Jan. 2003.[3] Chung-Hsun Huang and Jinn-Shyan Wang, High-Performance and Power-Efficient ChllOS Comparators,

IEEE J. Solid-state Circuiis,Vol. 38, pp. 254-262, Feb.2003.[4] Kai Hwang, Computer Arithmetic-Principles, ArchitectureandDesign. Reading: John Wiley & Sans, 1979.[51 D. E. Knuth, Soning and Searching. Reading: Addison-Wesley, 1973.[6] J. Sklansky, Conditional-Sum Addition Logic, IRE

Transncrions on Elecrronic Computers, Vol. EC-9, No. 2,pp. 226-231, June 1960.[7 ] Chua-Chin Wang, C.-F. Wu, and K.-C. Tsai, A 1.0 GHz64-bit High-speed Comparator Using ANT DynamicLogic with Two-Phase Clocking, IEE Proceedings -

Compurers and Digital Te,rhniques, vo l . 145, no. 6, pp.433436, Nov. 1998.[8] N. H. E. Weste and K. E:ihraghian, Principle of CM O SVLSIDesign, 2nd Ed., Reading: Addison-Wesley. 1993.

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