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Combinational Logic Synthesis with VHDL

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Outline Concurrent versus Sequential Concurrent statements (chapter 5 of Pedroni)

Using operators When...else With Select When GENERATE BLOCK

Sequential statements (chapter 6 of Pedroni) If then else Case when Loop Wait until

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Combinational vs Sequential Logic

Combinational logic is that in which the output of the circuit depends solely on the current inputs (figure 5.1(a)) in principle, the system requires no memory and can be implemented using conventional logic gates.

Sequential logic is defined as that in which the output does depend on previous inputs (figure 5.1(b)) storage elements are required, which are connected to the combinational logic block through a feedback loop, such that now the stored states (created by previous inputs) will also aect the output of the circuit. 4

Concurrent vs Sequential Code VHDL code is inherently concurrent (parallel). Only statements placed inside a PROCESS,

FUNCTION, or PROCEDURE are sequential. Still, though within these blocks the execution is sequential, the block, as a whole, is concurrent with any other (external) statements.

Concurrent code is also called dataflow code. In general we can only build combinational logic

circuits with concurrent code. To obtain sequential logic circuits, sequential code

(chapter 6) must be employed. Indeed, with the latter we can implement both, sequential as well as combinational circuits.

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Concurrency

A VHDL concurrent body A VHDL sequential body

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Concurrent codeIn summary, in concurrent code the following can be used: Operators; The WHEN statement (WHEN/ELSE or WITH/SELECT/WHEN); The GENERATE statement; The BLOCK statement.

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Combinational Logic

Combinational logic can be implemented with concurrent and sequential statements.

Concurrent statements are used in dataflow and structural descriptions.

Sequential statements are used in behavioral descriptions.

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Concurrent statements :

Sequential statements : Execute at the same time in parallel

Execute one at a time in sequence

Concurrent statements vs Sequential statements

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Concurrent Statements Lie outside of a process Signal assignment

Concurrent Selective (with-select-when) Conditional (when-else) Generate

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Concurrent assignment statements

or Concurrent Signal Assignment (CSA)

X

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Using Operators

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Table 5.1 Operators.

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Simple Concurrent StatementsAssignment Operator

Assignment operator

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Example 5.1: Multiplexer #1---------------------------------------

LIBRARY ieee;USE ieee.std_logic_1164.all;---------------------------------------

ENTITY mux ISPORT ( a, b, c, d, s0, s1: IN STD_LOGIC;

y: OUT STD_LOGIC);END mux;---------------------------------------

ARCHITECTURE pure_logic OF mux ISBEGIN

y

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Complex Concurrent StatementsWith-select-when

Example---- library statements (not shown)entity my_test is

port( a3,a2,a1,a0: in std_logic_vector(3 downto 0);s: in std_logic_vector(1 downto 0);y: out std_logic_vector(3 downto 0));

end entity my_test;architecture behavior of my_test isbegin

with s selecty

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when_else The signal is assigned a value based on

a condition.signal_name

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when-else implementation of MUXentity mux is port(

a,b,c,d : in std_logic_vector(3 downto 0);s : in std_logic_vector(1 downto 0);x: out std_logic_vector(3 downto 0));

end mux;architecture when_else of mux isbeginx

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Tri-state Buffer1 LIBRARY ieee;2 USE ieee.std_logic_1164.all;3 ----------------------------------------------4 ENTITY tri_state IS5 PORT ( ena: IN STD_LOGIC;6 input: IN STD_LOGIC_VECTOR (7 DOWNTO 0);7 output: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));8 END tri_state;9 ----------------------------------------------10 ARCHITECTURE tri_state OF tri_state IS11 BEGIN12 output 'Z');14 END tri_state;15 ---------------------------------------------- 44

Simulation results of example 5.3.

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Example 5.4: EncoderThe top-level diagram of an n-by-m encoder is shown in figure 5.8. We assume that n is a power of two, so m = log2n. One and only one input bit is expected to be high at a time, whose address must be encoded at the output. Two solutions are presented, one using WHEN / ELSE, and the other with WITH / SELECT / WHEN. 46

Encoder with WHEN/ELSE1 ---- Solution 1: with WHEN/ELSE -------------2 LIBRARY ieee;3 USE ieee.std_logic_1164.all;4 ---------------------------------------------5 ENTITY encoder IS6 PORT ( x: IN STD_LOGIC_VECTOR (7 DOWNTO 0);7 y: OUT STD_LOGIC_VECTOR (2 DOWNTO 0));8 END encoder;9 ---------------------------------------------10 ARCHITECTURE encoder1 OF encoder IS11 BEGIN12 y

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Example 5.5: ALU An ALU (Arithmetic Logic Unit) is shown in figure 5.10. As

the name says, it is a circuit capable of executing both kinds of operations, arithmetic as well as logical. Its operation is described in the truth table of figure 5.10. The output (arithmetic or logical) is selected by the MSB of sel, while the specific operation is selected by sels other three bits.

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Operation tale of ALU

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1 ---------ALU----------------------------------2 LIBRARY ieee;3 USE ieee.std_logic_1164.all;4 USE ieee.std_logic_unsigned.all;5 ----------------------------------------------6 ENTITY ALU IS7 PORT (a, b: IN STD_LOGIC_VECTOR (7 DOWNTO 0);8 sel: IN STD_LOGIC_VECTOR (3 DOWNTO 0);9 cin: IN STD_LOGIC;10 y: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));11 END ALU;12 ----------------------------------------------13 ARCHITECTURE dataflow OF ALU IS14 SIGNAL arith, logic: STD_LOGIC_VECTOR (7 DOWNTO 0);15 BEGIN16 ----- Arithmetic unit: ------17 WITH sel(2 DOWNTO 0) SELECT18 arith

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Combinational Logic with GENERATE

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GENERATE GENERATE is another concurrent statement (along

with operators and WHEN). It is equivalent to the sequential statement LOOP (chapter 6) in the sense that it allows a section of code to be repeated a number of times, thus creating several instances of the same assignments. Its regular form is the FOR / GENERATE construct, with the syntax shown below. Notice that GENERATE must be labeled.

Syntax of FOR / GENERATE:label: FOR identifier IN range GENERATE

(concurrent assignments)END GENERATE;

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IF/GENERATE An irregular form is also available, which uses

IF/GENERATE (with an IF equivalent; recall that originally IF is a sequential statement). Here ELSE is not allowed. In the same way that IF/GENERATE can be nested inside FOR/GENERATE (syntax below), the opposite can also be done.

IF / GENERATE nested inside FOR / GENERATE:label1: FOR identifier IN range GENERATE

...

label2: IF condition GENERATE(concurrent assignments)

END GENERATE;...

END GENERATE; 58

Example:SIGNAL x: BIT_VECTOR (7 DOWNTO 0);SIGNAL y: BIT_VECTOR (15 DOWNTO 0);SIGNAL z: BIT_VECTOR (7 DOWNTO 0);...

G1: FOR i IN x'RANGE GENERATEz(i)

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1 ------------------Vector Shifter------------------------------2 LIBRARY ieee;3 USE ieee.std_logic_1164.all;4 ------------------------------------------------5 ENTITY shifter IS6 PORT ( inp: IN STD_LOGIC_VECTOR (3 DOWNTO 0);7 sel: IN INTEGER RANGE 0 TO 4;8 outp: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));9 END shifter;10 ------------------------------------------------11 ARCHITECTURE shifter OF shifter IS12 SUBTYPE vector IS STD_LOGIC_VECTOR (7 DOWNTO 0);13 TYPE matrix IS ARRAY (4 DOWNTO 0) OF vector;14 SIGNAL row: matrix;15 BEGIN16 row(0)

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Example:b1: BLOCK

SIGNAL a: STD_LOGIC;BEGIN

a

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Sequential Code

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Sequential Code VHDL code is inherently concurrent. PROCESSES,

FUNCTIONS, and PROCEDURES are the only sections of code that are executed sequentially. However, as a whole, any of these blocks is still concurrent with any other statements placed outside it.

One important aspect of sequential code is that it is not limited to sequential logic. Indeed, with it we can build sequential circuits as well as combinational circuits.

Sequential code is also called behavioral code. The statements discussed in this section are all

sequential, that is, allowed only inside PROCESSES, FUNCTIONS, or PROCEDURES. They are: IF, WAIT, CASE, and LOOP.

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Variables VARIABLES are also restricted to be used in

sequential code only (that is, inside a PROCESS, FUNCTION, or PROCEDURE). Thus, contrary to a SIGNAL, a VARIABLE can never be global, so its value can not be passed out directly.

We will concentrate on PROCESSES here. FUNCTIONS and PROCEDURES are very similar, but are intended for system-level design, being therefore seen in Part II of this book.

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Behavioral Statements Concurrent assignment statements and

structural descriptions are sufficient to model any hardware architecture

State machines and storage devices are hard to model using dataflow and structural descriptions

Most algorithms are semi-sequential in nature Behavioral descriptions greatly simplify

sequential models VHDL provides sophisticated mechanisms for

sequential descriptions

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Processesprocessname : process(sensitivylist)is

declarationsbegin

sequentialstatementsend process processname;

-- sensitivylist : list of signals triggering the process on event-- declarations: types, variables that will be used in the process-- signal definitions are not allowed here! (behavioral code)-- processname: identifier of the process (optional)

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Processes

process constructs are used to describe behavioral models

A process lives in an architecture An architecture may include multiple processes A process may NOT include CSA or SSAs

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81 82

Processeslibrary ieee;use ieee.std_logic_1164.all;

entity foo isport(x,y : in std_logic;

z : out std_logic);end foo;

architecture beh of foo issignal s : std_logic;

beginprocess(x,y) is begin

s

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Wait Statements Wait statements are more powerful, but also

more difficult to synthesize!--generates clock with T=20ns --useful in testbenchesarchitecture beh of clkgen isbegin

processbegin

clk

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ifthenend if

if condition thenstatements A ;

elsestatements B ;

end if ;

if A = B thenF

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Case is when CASE signal X IS

when value_1 =>statements A ;

when value_2 =>statements B ;

:

when others =>statements P ;

END CASE;

Value must ExclusiveWhen others cover all others valueValue may be:

only one constant (when 101 )up to two constant (when 3 | 7 | 9 )Interval (when 5 to 9 )

Value_1

Value_2

Statements A

Statements B

Statements A

NO

NO

yes

yes

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Case is when

case A iswhen 00 => y y y y y x x

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library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.STD_LOGIC_arith.all;use IEEE.STD_LOGIC_unsigned.all;

entity decode38 isport(

A : in STD_LOGIC_VECTOR(2 downto 0);Y : out STD_LOGIC_VECTOR(0 to 7)

);end decode38;

architecture decode38 of decode38 isbeginprocess(A)variable j: integer; begin

j := conv_integer(A);for i in 0 to 7 loop

if(i = j) thenY(i)

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111 112

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Implicit memory Signals in VHDL have a current value and may

be scheduled for a future value If the future value of a signal cannot be

determined, a latch will be synthesized to preserve its current value

Advantages: Simplifies the creation of memory in logic design

Disadvantages: Can generate unwanted latches, e.g., when all of the

options in a conditional sequential statement are not specified

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Implicit memory:Example of incomplete specification

Note: the incomplete specification of the IF...THEN... statement causes a latch to be synthesized to store the previous state of c

ARCHITECTURE archincomplete OFincomplete IS

BEGINim_mem: PROCESS (a,b)BEGIN

IF a = '1' THEN c

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7-Segment Display

D a b c d e f g0 1 1 1 1 1 1 01 0 1 1 0 0 0 02 1 1 0 1 1 0 13 1 1 1 1 0 0 14 0 1 1 0 0 1 15 1 0 1 1 0 1 16 1 0 1 1 1 1 17 1 1 1 0 0 0 0

a

b

c

d

e

f g

a

b

c

d

e

f g

D a b c d e f g8 1 1 1 1 1 1 19 1 1 1 1 0 1 1A 1 1 1 0 1 1 1b 0 0 1 1 1 1 1C 1 0 0 1 1 1 0d 0 1 1 1 1 0 1E 1 0 0 1 1 1 1F 1 0 0 0 1 1 1

Truth tableseg7decD(3:0) AtoG(6:0)

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-- seg7decwith digit selectssg Segs Segs Segs Segs Segs Segs Segs Segs Segs Segs Segs Segs Segs Segs Segs Segs Segs

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ARCHITECTURE Behavior OF alu IS BEGIN PROCESS(S, A, B) BEGIN

CASE S IS WHEN "000" => -- Pass A through

F -- AND

F -- OR

F -- Not A

F -- Add

F -- Subtract

F -- Increment

F -- Decrement

F

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architecture comp_arch of comp isbeginCMP: process(A,B)variable AVS, BVS: signed(width-1 downto 0);begin

for i in 0 to width-1 loopAVS(i) := A(i);BVS(i) := B(i);

end loop;A_EQ_B

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library IEEE;use IEEE.STD_LOGIC_1164.all;

entity gray2bin isgeneric(width:positive := 3);port(

G : in STD_LOGIC_VECTOR(width-1 downto 0);B : out STD_LOGIC_VECTOR(width-1 downto 0)

);end gray2bin;

architecture gray2bin of gray2bin isbegin

process(G)variable BV: STD_LOGIC_VECTOR(width-1 downto 0);begin

BV(width-1) := G(width-1);for i in width-2 downto 0 loop

BV(i) := BV(i+1) xor G(i);end loop;B