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VHDL - a recapitulation
VHDL - a recapitulation
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Books - Archaic
• Digital Design - 1990M.Morris Mano £33Prentice-Hall International ISBN 0-13-212994-9
• Computer Engineering ( Hardware Design ) - 1988M.Morris Mano £33Prentice-Hall International ISBN 0-13-162926-3
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Books - Less Archaic
• Digital Design (Principles and Practices) - 3rd Ed. 2000,John F Wakerly £37Prentice-Hall International ISBN 0-13-082599-9
• Logic and Computer Design Fundamentals - 2000Mano,M. Morris; Kime,Charles R. £30Prentice-Hall International ISBN 0-13-012468-0
– p.s. Prices from Waterstones as of 20/10/2000,not that I’m recommending them for sales.
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Oh, and…
• http://tech-www.informatik.uni-hamburg.de/vhdl/
lots of VHDL links including to Peter Ashenden’s‘VHDL Cookbook’
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VHDL- Overview
• VHDL= VHSIC Hardware Description Language
• Commissioned for US Department of Defense contracts– Initially for simulation only !
• Looks similar to programming language ADA (which islike Pascal)
• Now governed by IEEE standards– 1076-1987/1993
• Popular description language for European design houses
• Support from all major CAD tool vendors– Lots of different design tools available
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VHDL - Overview
• The job :– Create Hardware designs
– Create Hardware designs which can be Synthesised
– Create Hardware designs which can be simulated / verified» Allow for the creation of test vectors
» Functional verification
» Timing verification
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Why/Why not Machine Code ?
• You’ve been asked to code“The Sims VIII - It’s a Jungle Out There” by Maxis.
C++ or assembler, and why ?
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VHDL- A First Look I
• Each description comprises 2 components– Interface description- a list of the connections (ports) in and out
– Architecture body- some description of how the block works
– A,B,Z are the interface
– AND gate is the architecture
A
B
Z
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VHDL- A First Look II
• So, what does the corresponding code in VHDL look likefor our simple AND gate ?
entity ANDGATE is
port ( A,B: in std_logic;
Z: out std_logic );
end ANDGATE;
architecture MYARCH of ANDGATE is
begin
Z <= A and B;
end MYARCH;
A
B
Z
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Entity Declarations- I
• Entity declarations are used to describe the interface to agiven block/ component (i.e. its inputs and outputs)
entity LINE is
port ( DIALIN,HANDSET,CLOCK,
N_RESET: in std_logic;
LINEOUT: out std_logic );
end LINE;
Specifies that dialin, handset, etc.are input signals of a single bit
Specifies that lineout is anoutput signal of a single bit
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Entity Declarations- II
• Previous examples only interested in single bit input andoutputs- what about busses ?
entity KEYBDIN is
port (KEYBD: in std_logic_vector(3 downto 0);
CLOCK,N_RESET: in std_logic;
DATAOUT:out std_logic_vector(3 downto 0);
DATAVALID: out std_logic);
end KEYBINF ;
Specifies that dataout is anoutput signal of multiple bits(i.e. a vector) in the range3..0
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Entity Declarations- III
• Now, let’s try an example…...entity DIALLING is
port (DIGIT: in std_logic_vector(3 downto 0);
CLOCK,N_RESET,DMODE, DIAL: in std_logic;
TONECOL, TONEROW:out std_logic_vector(4 downto 0);
PULSEDATA: out std_logic);
end DIALLING ;
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Internal Architectures- Intro• We can partition the internal architectures which make up
a system into 2 categories
• Combinatorial (Asynchronous)– No notion of internal state
– Just a bunch of gates connected together
– If we change an input from 0=>1 then output changes after sometime (propagation delay)
• Synchronous– We have a notion of state
– Contains gates + Flip-Flops
– We have to clock the system before changes take place
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Simple Combinatorial Architectures- I
• Back to our simple AND gate example..
• Reserved VHDL keywords are in bold, lower case
architecture MYARCH of ANDGATE is
begin
Z <= A and B;
end MYARCH;
The architecture name(can be anything)
The corresponding entityfor this architecture
Note that Z, A, Bcome from the entitydeclaration
<= is the assignmentoperator
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Simple Combinatorial Architectures- II
• Gate level functions provided in VHDL
Boolean Equation VHDL Coding Operation
Z1= A1�B1 z1 <= a1 AND b1;
Z2= A2 + B2
Z3= A3 � B3
Z4= A4
Z5= (A5�B5)
Z6= (A6+B6)
z2 <= a2 OR b2;
z3 <= a3 XOR b3;
z4 <= NOT a4;
AND
OR
Exclusive OR
NOT
z5 <= a5 NAND b5;z5 <= NOT(a5 AND b5);
z6 <= a6 NOR b6;z6 <= NOT(a6 OR b6);
NAND
NOR
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Simple Comb’l Architectures- III
• Now let’s try an example…..
A
B
C
D
ZZ <= (A and B) or (C nor D)
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Signal Representation- I
• The problem– We have to represent physical signals (logic 1, 0, highimpedance etc.) in a non-physical system
– What about a bus where several signal drivers are connectedtogether ?- what’s the result etc. (in simulation)
USB Interface
RAM
EPROM Co
ntr
olle
rCommon Data Bus
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Signal Representation- II
• The solution– A package called ‘std_logic’ exists which permits representation
of signals- see entity examples before
– A resolution table defines values during simulation
– Commonly used values and example:
D[7]
D[7]
‘Z’
‘1’
‘1’
Logic 0
Logic 1
High Impedance
‘0’
‘1’
‘Z’
Value Representation
Plus ‘U’, ‘X’, ‘-’, ‘W’, ‘L’, ‘H’
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Working with Single Bit Values
• Single bit values are declared as std_logic– Example: clk : std_logic
• The signal is manipulated like a single character type in aconventional programming language– Example: clk <= ‘0’;
clk <= ‘1’;
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Working with Multiple Bit Values
• Multiple bit values (a.k.a. Busses) are declared asstd_logic_vector– Example: abus : std_logic_vector(3 downto 0)
• Individual bits in the bus can be manipulated in a similarmanner to arrays in a conventional language– Example: abus <= “0000”;
abus (0) <= ‘0’;
abus (1 downto 0) <= “00”;
Note use of double quotes forstd_logic_vector assignment
Note use of single quotes forstd_logic assignment
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Processes and Architectures- Intro
• Previous examples for basic illustration only– Any ‘real’ system requires use of sequential/ concurrent
instructions
• VHDL provides for these two distinct domains
• Sequential– Instructions are executed in a set sequence
– These are held within a process
• Concurrent– A group of instructions which happen simultaneously
– Can have a number of processes that are ‘executed’ concurrently
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Processes and Architectures- Example
• So, architecture definition contains one (or more)processes
architecture behavior of mydesign is
begin
end behavior;
P1 : process( )
end process;
P2 : process( )
end process;
P1 and P2 processes runconcurrently
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VHDL Processes- I
• A VHDL process is simply a set of instructions which areexecuted in the order that they appear
• A process looks like this:
process (a,b) begin -- instruction 1 -- instruction 2
end process;
This part in brackets is calledthe sensitivity list
Instruction 1 is executed, theninstruction 2 and so on
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VHDL Processes- II
• The sensitivity list contains a list of all the signals towhich the process is sensitive– i.e. the process will be ‘executed’ only upon any change in the
signals contained within the sensitivity list
• The sensitivity list for a process can include any mix ofthe following– Input signals defined in the entity
– Common signals within the architecture
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Inter-Process Communication
• Processes communicate between each other with commonsignals in the architecture– Any (but only 1) process can modify the a signal
• Common signals are declared in the architecture beforethe start of the main body, i.e.:
signal signal_name : std_logic/ std_logic_vector
architecture behavior of mydesign is
begin
end behavior;Signals declared within thearchitecture
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VHDL- Example Source File
• The following is the complete syntax of a typical VHDLsource file
architecture behavior of mydesign is
begin
end behavior;
P1 : process( )
Pn : process( )
<signal declarations>
entity mydesign is
end mydesign;Entity Declaration
Main architecture(with at least 1 process)
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Architectures - styles
• Structural
• Dataflow
• Behavioural
• Hierarchical
• Still waiting for the ultimate silicon compiler !
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Summary
• Provided an overview of key design issues and how tostructure and organise designs using– Hierarchy, Regularity, Reuse
• Provided an introduction to the basics of VHDL forimplementation– Entity descriptions
– Architectures
– Simple combinatorial functions
– Signal representation (0, 1, Z)
– Processes
– Signals (assignment and declaration)
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