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Time-Division Multiplexing of Digital Signals Siemens

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Contents

1 Basic Methods of Multiplexing 3

2 Synchronization between Transmitting End and Receiving End 9

2.1 Recovery of Frame Alignment 12

2.2 Loss of Frame Alignment 123 Definition of Plesiochronous Digital Signals 13

4 Clock Alignment of Plesiochronous Signals 21

5 Basic Pulse Frame Structure 25

6 Realization of the Positive Justification Method 29

6.1 The Elastic Store (Multiplex-Side) 30

6.2 The Elastic Store (Demultiplex-Side) 34

6.3 Jitter caused by Multiplexers 36

Time-Division Multiplexing of DigitalSignals

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Siemens Time-Division Multiplexing of Digital Signals

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1 Basic Methods of Multiplexing

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For the generation of the sum signal out of the individual separate signals thefollowing two methods may be used:

Code word interleavingWith this method code words of the individual separate signals (i.e. bit combinationshaving some kind of relation between each other) are arranged one after the other ina time sequence. Such is the case for the generation of a 2-Mbit/s-signal, where the8 bit binary words of the coded PCM-voice channels are transmitted sequentially in a

125 ms cycle.

This figure shows the code word interleaving of two separate signals with a wordlength of four bits.

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0 1 1 1 0 1 0 11

0 1 1 0 1 0 1 011

05 1 10 10 01 11 10 01 01

Code word interleaving

Fig. 1

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Bit-by-bit interleaving

This method is used for all systems beyond the 2 Mbit/s hierarchy. Here a cyclic

transmission sequence is applied, where only one bit of each separate signal istransmitted. This means that the signal of a certain multiplexer input appears only inevery fourth bit of the sum signal.

The figure shows the bit-by-bit interleaving of two separate signals.

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1

0 1 1 0 1 0 1 111

05 1 11 10 00 11 01 11 10

Bit-by-bit interleaving

1 1 0 0 1 1 1 0 1

Fig. 2

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TT2510EU01AL_018

Two basic cases can be distinguished with multiplexing:

1. the original signals are synchronous, i.e. their clocks are exactly the same. Thisis valid for a PCM30 system, where the clocks of the individual 64-kbit/s-signals

and the 2 Mbit/s-clock are derived from a central system clock. In this case themultiplexing process is restricted to a simple parallel-to-serial conversion of the 8bit code words.

2. the original signals are not synchronous, i.e. their clocks come from differentsources. This is valid for the multiplexing of output signals, originating fromvarious PCM30 systems their clocks being generated in each system in anautonomous way. Here it is necessary to take appropriate measures in order tocompensate the occurring clock differences.

This case will be dealt with in the following chapters.

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TT2510EU01AL_019

2 Synchronization between Transmitting Endand Receiving End

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For each type of multiplexing it has to be ensured that the sum signal can beresolved into the individual original signals (demultiplexing process). The receiver ofthe sum signal thus has to know which bits are assigned to the individual

subsystems. To allow for this, a fixed bit combination, the so-called frame alignmentword (FAW) is inserted by the transmitting system in periodically recurring intervalsinto the sum signal.

If the receiver detects the frame alignment word in the received signal it is possible toperform the assignment of the following bits to the subsystems by means of theregenerated receiving clock (see also chapter 6).

The time intervals between the beginning of a FAW and the beginning of thefollowing FAW are called pulse frames.

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X

F

A

W

Y

F

A

W

F

A

W

F

A

W

a b a b b

frame N frame N+1 frame N+2

a) continous searching of the FAS position

b) periodical check of the FAW positionFAW Frame alignment word

X Bit combination pretending the FAW

Y any bit combination one frame length after X

a) continuous searching of the FAS positionb) periodical check of the FAW positionFAW Frame alignment wordX Bit combination pretending the FAWY any bit combination one frame length after X

Fig. 3

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TT2510EU01AL_0112

2.1 Recovery of Frame AlignmentDuring recovery of frame alignment (e.g. during initial commissioning of a system) thereceiver continuously examines the incoming signal upon occurrence of the FAW. Ifthis FAW is detected for the first time, the receiver expects a renewed occurrenceonly after the specified pulse frame period has elapsed (counting of the receivingsignal clocks). In this case the process will be repeated; the synchronization isestablished. Otherwise, the system takes the continuous searching up again. Thisprocedure ensures that a synchronization to a bit combination, which accidentally hasthe same content as the FAW, is excluded.

2.2 Loss of Frame AlignmentOnly if the FAW does not appear in the expected positions for several consecutivetimes (e.g. four) the frame alignment is supposed to be lost. This guarantees that incase of transmission errors the system does not perform an immediatedesynchronization.For each faulty frame alignment word a pulse is produced, which can be used for theestimation of the bit error rate (see also chapter 6, in-service measurement of biterror rates).

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3 Definition of Plesiochronous Digital Signals

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Supposed a data source (S) transmits a digital signal with a bitrate fS to a data drain(D). The data drain decides with the aid of an internally generated clock frequency fR

whether the incoming signal is zero or one in the moment of the clock pulse. The two

clock signals fS and fR are thus generated in different places and although they dohave the same nominal frequency, they will always differ from each other to a certainextent.

Definition:

Data signals are termed plesiochronous if their clock rates have the same nominalvalue, but may differ from each other within certain tolerance ranges.

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TT2510EU01AL_0115

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S D

data signal with

bitrate fS

read in data

with clock rate fR

Fig. 4

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TT2510EU01AL_0116

The effects of these clock deviations are represented in the two figures below:

Sampling clock fR > transmission clock fS

Two sampling instants are within one bit interval of the transmitting signal. The datadrain (D) interprets this situation as double transmission of bit a5.

double bit transmission

fS

a1 a2 a3 a4 a5 a6 a7

D

a1 a2 a3 a4 a5 a6 a7a5

fR

Fig. 5

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TT2510EU01AL_0117

Sampling clock fR < transmission clock fS

One transmitted bit is between two sampling instants. Bit b5 not detected by the datadrain (D).

no bit transmission

fS

b1 b2 b3 b4 b5 b6 b7

D

b1 b2 b3 b4 b6 b7

fR

Fig. 6

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TT2510EU01AL_0118

Plesiochronism during Multiplexing Process

The multiplexing process may be represented with the aid of the following figure.

A rotating pointer samples the feeder links (tributaries) for the separate signals with afrequency which is four times higher than the nominal bitrate fS (fR = 4 X fS), i.e. eachdigital signal is sampled with a nominal fS. As both, the digital signal sources(S1...S4) as well as the sampling frequency (fR) are generated by different clocksources, the result is a plesichronous state of operation for every feeder link.

Example:

The signal sources (S1...S4) are PCM30 devices transmitting with their individualtransmission clock a 2 Mbit/s-signal with clock tolerances to the inputs of a 2/8multiplexer.

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TT2510EU01AL_0119

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S1

S2

S3

S4

fSDf1

fSDf

2

fSDf3

fSDf4

D

fRDf

fR

= 4x fS

Fig. 7

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TT2510EU01AL_0120

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TT2510EU01AL_0121

4 Clock Alignment of Plesiochronous Signals

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TT2510EU01AL_0122

During multiplexing of plesiochronous digital signals the so-called positive justificationmethod is applied, which is based on the following principles:

l a bitrate for each subsystem is provided in the multiplex signal, which is somewhat

higher than the subsystems nominal bitrate. This means that the transmissioncapacity is systematically higher than actually needed.

l the difference between the bitrate of the subsystem and the multiplex bitrate persystem is compensated for each channel by the justification bitrate, which doesnot contain any information and serves only for the compensation mentionedabove.

l the justification bitrate is thus always adjusted to the difference between the bitrateof the subsystem and the multiplex system and thereby compensates for eachchannel the tolerance between the tributary signal bitrates and multiplex signalbitrates.

Example:

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TT2510EU01AL_0123

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S1

S2

S3

S4

fS1

fS2

fS3

fS4

D

4 x fR

+

+

+

+

fR - fS1

fR

fR

- fS2

fR

fR

- fS3

fR

fR - fS4

fR

Fig. 8

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TT2510EU01AL_0124

l The signal sources S1..S4 emit signals with a nominal value of 2048 kbit/s

l The sampling pointer rotates with a frequency of fR = 2052 kHz, i.e. thetransmission capacity per channel is 4 kbit/s higher than the nominal bitrate of

the subsystem.

l Supposed the signal sources transmit the following actual bitrates:

S1 : f S1 = 2048.1 kbit/s

S2 : f S2 = 2048.05 kbit/s

S3 : f S3 = 2048.0 kbit/s

S4 : f S4 = 2047.9 kbit/s

This results in the following justification bitrates:

for channel 1 : 2052 kbit/s - 2048.10 kbit/s = 3.90 kbit/s

channel 2 : 2052 kbit/s - 2048.05 kbit/s = 3.95 kbit/s



Thus, the resulting signals at the rotating pointers sampling points are synchronous.The multiplexing procedure can be performed without the former discussed problemsof omission or double sampling of individual bits.

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5 Basic Pulse Frame Structure

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How is a variable justification bitrate realized

The signals of higher hierarchy levels are transmitted within a predetermined framestructure, the same as for the 2 Mbit/s signal of the first hierarchy level. This frame

begins with a frame alignment word of fixed length and content in order to allow onthe demultiplex side of the system an allocation of the following bit-interleavedtributary bits to the appropriate channels. In addition, the frames of theplesiochronous hierarchy contain one bit position per individual signal, which is eitherused for the transmission of a tributary bit, or not used at all. This bit position is called

justification bit. By alternate use/non-use of this bit position, the transmission capacityfor the individual signals may be varied to some extent.

This process is called positive pulse justification; thus, the non-use of the justificationbit position corresponds to an increase in the justification bitrate (= decrease in thetransmission capacity), whereas the use of the justification bit position has the

opposite effect.

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FAW TB 1...4JS

1

JS

2

JS

3

JS

4TB 1...4

JB

1

JB

2

JB

3

JB

4TB 1...4

FAW Frame alignment wordJS1..4 Justification service bit position for channels 1..4JB1..4 Justification bit position for channels 1..4TB1..4 Tributary bits for channels 1..4; here the tributary signals are transmitted

bit-by-bit interleaved

Fig. 9

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The receiving end of such signals requires an information on how the justification bitposition has been used (non-information bit or tributary bit). To allow for this, thereare justification service bits arranged before the justification bits in the time

sequence. The content of the justification service bits indicates how the followingjustification bit position has to be interpreted. If, for example, the content of thejustification service bit for channel 3 is a binary one, the receiver ignores the followingjustification bit positions of channel 3. The other way round (JS3 = 0), the positionJB3 is interpreted as tributary bit.

Example:

The frame structure in a 8 Mbit/s pulse frame:

frame duration: 100.38 ms

overall number of bits in blocks TB1:200 bit, TB2:208 bit, TB3:208 bit, TB4:204 bit or208 bit.

This results is an actual bitrate/channel

of: sMbits

bitBR

T/04224,2

438.100

820=

=

m

This is the bitrate /channel if the justification bit position is always unused.

If every justification bit position is used for a tributary bit of the separate signal thefollowing actual bitrate/channel is calculated:

sMbits

bit

BRT /05220,2438.100

824=

=

m

By alternate use/non-use of the justification bit position in the frames the transmissioncapacity for the individual channels in this examples may be varied within a range of9.962 kbit/s.

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6 Realization of the Positive JustificationMethod

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6.1 The Elastic Store (Multiplex-Side)How can the justification process be realized?

An elastic store consists of a number of 1 bit memory cells (typ. 12) which can bewritten in and read out independently of each other (i.e. at the same time it ispossible to write in one cell, while another is read out). The incoming separate signal

with its own clock is written in the cells 1...8, 1...8 etc. in a cyclic way. The store isread out with a clock, generated in the multiplexer; a clock which is systematicallyhigher than the bitrate of the separate signal. The difference between write addressand read address is monitored by an address comparator. It goes without saying thatthe write address always has to be ahead of the read address. Due to the greaterread out velocity the read address continually approaches the write address. If thedifference between the two becomes < 3 memory cells, the comparator releases asignal.

Then the following procedures are started:

If the justification service bit position in the frame is reached, the bit is set to one.

On reaching the justification bit position, the read address is maintained for one clockperiod and the actual memory cell is read out once more. This is the justification bit

which is ignored at the receiving end. By maintaining the read address during oneclock cycle the difference between the addresses increases and the whole procedureis repeated in the same way. Thus, the plesiochronous clock rate of the channel ismatched to the multiplex bitrate.

Between the initiation of the justification process (comparison of addresses) and itsexecution there may be an interval of max. 1 frame period, within which the readaddress approaches the write address more and more. That is why the justificationprocess is initiated already when the address spacing is smaller than 3, in order toensure a reserve against memory overflow, e.g. an empty memory.

Each channel is assigned an elastic store. As the read out clock for all channelscome from the same clock supply (in the multiplexer), the output bitrates of the elasticstores are synchronous. The actual multiplexing procedure is thereby continued toa simple parallel-to-serial conversion of the output signals of the elastic stores for thefour separate signals.

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TR

AC

TG

ch 2 . . 4

GAP

T2

T1

ch

2 . . 4

P/S

D2

LOGIC

D1

JS

TR : Timing regenerator input signal (= write in timing)AC : Address comparatorTG : Timing generation of read out t iming channels 1..4GAP : Timing gap for justification procedureJS : Insertion of justification service bitLOGIC : Control of the justification service bit and of the timing gapP/S : Parallel-to-serial converter D1 : Tributary input data with independent of the system clock

D2 : Stuffed output data, synchronous to the system clockT1 : Retrieved clock from tributary input data for write inT2 : Read out clock from central clock supply

Fig. 10 Principle of an elastic store

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ES JS

ch

2 ... 4

LOG TG

CTRCTR

AC

TR

ch 2 ... 4

T1 T2

D2

D1

P/S

TR : Timing regenerator input signalCTR : Counter for the generation of write in/read out addressES : Elastic store

AC : Address comparatorJS : Insertion of justification service bitLOG : Logic circuit - controls the insertion of the justification service bits, removes one clock period

depending on the output signal of the ACTG : Generation of timing signals for the complete multiplexer sideD1 : Plesiochronous tributaryD2 : Stuffed tributary, synchronized to system clockT1 : Recovered clock from tributary input for write in

T2 : Read out clock, derived from central clock supplyFig. 11 Block diagram of an elastic store

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Realization of the positive justification method

positive justification method : f2 > f1

Input

signalf1

Output of

the elastic

store

f2

Multiplex

signal

Justification bit (non-information bit)

Fig. 12

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Example (see also fig.12):

l the bitrate of the input signal shall be f1 = 2048 kbit/s.

l the pulse frame of the multiplex signal shall be 100,38 ms and contains 1justification bit per channel

l the read out timing rate shall be 2052 kbit/s.

The reading pointer would overpass the writing pointer (2052 kHz-2048 kHz =

4 kHz) 4000 times per second. That is why on average one justification bit is

inserted every 250 ms (1/4 kHz = 250 ms). For a pulse frame of 100,38 ms, this

means that one justification is effected on average in every 2,5th frame (250 ms/

100,38 ms) (2 in 5 frames).

lthe bitrate of the input signal shall now be T1 = 2047,90 kbit/s.Now the justification must be effected every 243,90 ms, i.e. in every 2,4 pulseframe.

l the bitrate of the incoming signal shall be T1 = 2048,10 kbit/s.

A justification is required every 256,40 ms, i.e. in every 2,56 frame.

6.2 The Elastic Store (Demultiplex-Side)The task of the demultiplexer is to distribute the sum signal in the right sequence tothe output of the separate signals. Therefore, the incoming multiplex signal is dividedinto 4 separate signals by means of parallel-to-serial conversion. By control of theframe alignment signal the 4 separate signals can be assigned to the right channels.Besides, the justification service bits and justification bits can be identified (bycounting the bits transmitted since the beginning of the frame). By means of thisinformation the justification process is canceled, i.e. all bits which do not come fromthe original signal are removed from the separate signals.

Thus, a signal with timing gaps instead of the removed bit positions is generated. In

order to guarantee a continuous signal at the outputs, elastic stores are used on thedemux-side to smooth the signal.

For this, the incoming datas signal is written into the store with the gap timing andread out of the store with a continuous timing which corresponds to the averagevalue of the gap timing; thus the signal is forwarded in a smoothed condition to theoutgoing subsystem interface.

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ES

CTR CTR

data signal

with gaps

data signal

continuous

CTR

gap timing continuous timing

phiU

ES - Elastic store

CTR - Counter VCO - Voltage controlled oscillatorphi/U - Phase comparator

Fig. 13 Principle of an elastic store (demultiplex-side)

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A continuous timing is generated from the gap timing by means of a phase-lockedloop (PLL). For this, a voltage-controlled oscillator is synchronized to the gap timingfrequency. If the critical frequency of the control loop is selected sufficiently low (low-

pass filter) it is ensured that the voltage-controlled oscillator adjusts itself to theaverage value of the gap timing frequency.

6.3 Jitter caused by MultiplexersThe gap in the write clock of the elastic store result in phase shifts on the input-sideof the PLLs phase comparator, which are converted to voltage shifts. These voltageshifts are smoothed by the low pass filter of the PLL, but they can never be smoothed

perfectly.

That is why the smoothed clock of the control voltage will vary accordingly also at theoutput of the PLL circuit, i.e. jitter is generated. The jitter in the output signal dependson the system. The highest jitter frequency is determined by the limit frequency valueof the PLL low-pass filter.

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