Page 1 of 17 US ATLAS HL-LHC Upgrade BASIS of ESTIMATE (BoE) Date of Est: 04/25/2018 Prepared by: Hong Ma, Hucheng Chen, Mitch Newcomer Responsible Inst: BNL, UPenn Docdb #: HL-LHC-doc-55 WBS number: 6.4.5 including 6.4.5.1 (BNL), 6.4.5.2 (UPenn) WBS Title: LAr Analog Front-End (PA/Shaper) ASIC WBS Dictionary Definition: This BOE covers the design, prototyping, production, and testing of the analog front end (preamplifier plus shaper, PA/Shaper) ASICs for the LAr HL-LHC frontend board (FEB2). This ASIC amplifies and shapes the analog signal from the liquid argon (LAr) calorimeter, and is a critical element of the FEB2 readout scheme. The work covered by this BOE will be performed by a collaboration of Brookhaven National Lab (BNL) and the University of Pennsylvania (UPenn), and includes the design, prototyping, and production of an 8- channel PA/shaper ASIC in the 65nm or 130nm CMOS technology available from Taiwan Semiconductor Manufacturing Company Limited (TSMC). UPenn is responsible for the design of the calibration and related components of the ASIC. BNL is responsible for the overall design and testing system, in collaboration with French collaborators at IN2P3 LAL/Omega. Tests of the prototypes and production ASICs will be carried out by both groups. Irradiation tests will be performed to verify that the radiation tolerance of the ASICs meets the specifications for operations at the HL-HLC. In the production phase, production test benches will be built and used to perform production QA/QC on 50% of PA/shaper ASICs at BNL; the other 50% will be carried out by French collaborators. The full LAr readout system requires 1524 FEB2s with 128 channels each. The total required number of fully qualified production ASICs is 1524*128/8=24384. Estimate Type (check all that apply – see BOE Report for estimate type by activity): _x_ Existing Purchase Order or Work Complete ___ Engineering Build-up _x_ Extrapolation from Actuals _x_ Analogy ___ Expert Opinion Supporting Documents (including but not limited to):
WBS number: 6.4.5 including 6.4.5.1 (BNL), 6.4.5.2 (UPenn)
WBS Title: LAr Analog Front-End (PA/Shaper) ASIC
WBS Dictionary Definition: This BOE covers the design, prototyping, production, and testing of the analog front end (preamplifier plus shaper, PA/Shaper) ASICs for the LAr HL-LHC frontend board (FEB2). This ASIC amplifies and shapes the analog signal from the liquid argon (LAr) calorimeter, and is a critical element of the FEB2 readout scheme. The work covered by this BOE will be performed by a collaboration of Brookhaven National Lab (BNL) and the University of Pennsylvania (UPenn), and includes the design, prototyping, and production of an 8-channel PA/shaper ASIC in the 65nm or 130nm CMOS technology available from Taiwan Semiconductor Manufacturing Company Limited (TSMC). UPenn is responsible for the design of the calibration and related components of the ASIC. BNL is responsible for the overall design and testing system, in collaboration with French collaborators at IN2P3 LAL/Omega. Tests of the prototypes and production ASICs will be carried out by both groups. Irradiation tests will be performed to verify that the radiation tolerance of the ASICs meets the specifications for operations at the HL-HLC. In the production phase, production test benches will be built and used to perform production QA/QC on 50% of PA/shaper ASICs at BNL; the other 50% will be carried out by French collaborators. The full LAr readout system requires 1524 FEB2s with 128 channels each. The total required number of fully qualified production ASICs is 1524*128/8=24384. Estimate Type (check all that apply – see BOE Report for estimate type by activity): _x_ Existing Purchase Order or Work Complete ___ Engineering Build-up _x_ Extrapolation from Actuals _x_ Analogy ___ Expert Opinion Supporting Documents (including but not limited to):
Page 2 of 17
Details of the Base Estimate (explanation of the Work) This BOE covers development of an analog front end (PA/shaper) ASIC in TSMC 65nm or 130nm CMOS technology, from prototype design to final production test. The PA/shaper ASIC reads out 8 LAr channels, and a total of 24384 fully qualified production PA/shaper ASICs will be required to instrument 1524 FEB2 boards. The design and production of FEB2s are part of the NSF scope of the US ATLAS HL-LHC Upgrade Project (WBS 6.04.02). Taking into account 103 spare FEB2, and ~6% spare ASICs as was done in the original LAr construction, a total of 27600 fully qualified production ASICs are needed. Assuming a production yield of ~70%, a total of 40000 ASICs will be produced (See Table 1). 50% or 20000 ASICs will go through QA/QC procedure at BNL, the other 50% will be carried out by French collaborators.
Table 1. Numbers of the PA/Shaper ASIC at different stage
Number of qualified ASICs needed to instrument 1524 FEB2 on detector 24384 Number of qualified ASICs including spares 27600 Yield Factor ~0.70 Total number of ASICs produced 40000 Total number of ASICs tested at BNL 20000
Three pre-prototypes and one prototype are expected to be designed, produced and tested (including irradiation tests) from FY17 to FY21 before the production starts in FY21. The multiple stages of prototyping are necessary to ensure the performance, as well as incorporating additional features as the design matures. The timing of the completion of these prototypes, including the tests, corresponds to the ATLAS LAr HL-LHC upgrade milestones of PA/shaper ASIC down-select, ATLAS Preliminary Design Review (PDR), ATLAS Final Design Review (FDR) and ATLAS Production Readiness Review (PRR). Pre-prototype2, Pre-prototype3 and prototype ASICs will be used on FEB2 prototypes to develop the FEB2 design and to verify the system level performance, before launching production. In the production stage (FY21-FY23), 50% of the produced chips (20000) will go through production QA/QC procedures at BNL, and only qualified chips will be used on production FEB2 boards. The delivery of 13800 fully qualified production PA/shaper ASICs to the site where FEB2 boards are assembled is the final step of this WBS. The overall design of the ASIC will be carried out at BNL, in collaboration with UPenn and French collaboration institutes IN2P3 LAL/Omega. The design and production of the test system for each prototype and the final production will also be carried out by BNL, with test systems made available to all collaboration institutes. To facilitate the production test of 40,000 chips, multi-chip test stands, one at BNL and one at IN2P3 LAL, will be built. Cost Estimate
Page 3 of 17
The cost estimate for this work is summarized in the table below. The M&S costs are estimated based on current pricing information about the CMOS process from TSMC, packaging, and past vendor quotes for off-the-shelf components and test boards, while the manpower and travel estimates are based on recent experience with similar projects at both UPenn and BNL. The cost summary is presented in the table below, and more details are provided following the table.
Cost estimate for 6.04.05 6.04.05 PA Shaper 21,414 432,000 47,500
6.04.05.01.01 / BNL LAr FE ASIC Pre-prototype1 Design 580
ENG 580
6.04.05.01.02 / BNL LAr FE ASIC Pre-prototype1 Test 645 12,500 5,000
ENG 645 MAT
12,500
TRAVD
5,000
6.04.05.01.03 / BNL LAr FE ASIC Pre-prototype2 Design 2,310 45,000 2,500
ENG 2,310 EQUIP
40,000
MAT
5,000 TRAVD
2,500
6.04.05.01.04 / BNL LAr FE ASIC Pre-prototype2 Test 1,050 15,000 5,000
ENG 1,050 MAT
15,000
TRAVD
5,000
6.04.05.01.05 / BNL LAr FE ASIC Pre-prototype3 Design 1,740 40,000 5,000
ENG 1,740 EQUIP
35,000
MAT
5,000 TRAVD
5,000
6.04.05.01.06 / BNL LAr FE ASIC Pre-prototype3 Test 944 15,000 5,000
ENG 944 MAT
15,000
TRAVD
5,000
6.04.05.01.07 / BNL LAr FE ASIC Prototype Design 1,740 112,000 5,000
ENG 1,740
Page 4 of 17
EQUIP
102,000 MAT
10,000
TRAVD
5,000
6.04.05.01.08 / BNL LAr FE ASIC Prototype Test 1,240 25,000 5,000
ENG 1,240 EQUIP
20,000
MAT
5,000 TRAVD
5,000
6.04.05.01.09 / BNL LAr FE ASIC Production Design 1,760 85,000 5,000
ENG 1,760 EQUIP
85,000
TRAVD
5,000
6.04.05.01.10 / BNL LAr FE ASIC Production Test 4,315 80,000 7,500
ENG 1,830 MAT
80,000
TRAVD
7,500 TECH 2,485
6.04.05.02.01 / PENN LAr FE ASIC Pre-prototype1 Test 370 2,500
ENG 370 MAT
2,500
6.04.05.02.02 / PENN LAr FE ASIC Pre-prototype2 Design 410
2,500
ENG 410 TRAVD
2,500
6.04.05.02.04 / PENN LAr FE ASIC Pre-prototype3 Design 468
ENG 468
6.04.05.02.06 / PENN LAr FE ASIC Prototype Design 450
ENG 450
6.04.05.02.08 / PENN LAr FE ASIC Production Design 576
M&S Costs BNL The PA/shaper prototype ASIC production cost is based on the actual cost of preprototype1 (see Attachment 1) for this process. We assume a chip area of 25 mm2 for the 8-channel PA/shaper chip, based on the design for preprototype1. In each of the pre-prototype stages and the prototype stage, we anticipate one iterated ASIC design to be submitted each year via a multi-project wafer (MPW) run. For preprototype1, the cost for the MPW run in 65nm was $98688 (Attachment 1), with R&D fund committed before the start of the project. The cost for the future prototypes is based on 130nm shared with the French collaborators, based on a quote by CERN Foundry Service (Attachment 7). Based on the experience with the recently submitted preprototype1, the cost for packaging and for production of the associated test jigs for performance and also irradiation testing is estimated (Attachment 2 and 3). Each MPW run will be followed by a comprehensive chip evaluation test, aimed at studying the chip performance and discovering any potential issues and feed back to the next iteration of the chip design. For the prototype ASIC, about 600 prototype PA/shaper chips will be ordered, to have sufficient quantities to be able to populate the 20 FEB2 prototypes that would be produced, including 14 to be used in the FE system crate test performed as a critical milestone before the FEB2 PRR. This system test will provide important information before the production ASIC design is finalized. Irradiation tests will also be performed to verify the radiation tolerance of the ASIC. All of these will be necessary before the PRR of the PA/shaper ASIC. The cost of ordering this quantity via an MPW run is estimated to be $102k. Because the number of chips to be tested is larger, and the test jigs for production QA/QC will have to operate reliably and capable of testing multiple chips simultaneously, the cost for production of the required test jigs and for performing the tests is estimated to be higher than those for the pre-prototypes. The PA/shaper ASIC production run will be done through a combined submission with the other LAr ASICs (ADC) if the final design is in TSMC 65nm CMOS technology. The NRE and wafer charges are included in the ADC cost. Therefore, the production M&S costs in this WBS (in FY21-FY23) cover only the PA/shaper ASIC packaging and the production test stand. The packaging cost is estimated based on a recent quotation from MOSIS (Attachment 2), for packaging a chip developed for a neutrino experiment in a 80-pin LQFP package, namely $20k NRE for tooling and then $7500 to package 5000 chips. With these numbers, packaging 40000 chips would cost $80k (including the NRE cost). We budget $85k for packaging costs. For preprototypes, based on the cost for the first set of test PCBs (Attachments 3, 4, 5), we estimate an M&S cost of $10k for 3 sets of test boards, and $5k for evaluation and radiation tests. The test setup for the prototype ASIC will have will be more complex than what is designed now, to guarantee reliable operation with sockets and be capable of testing multiple chips simultaneously. It is expected the cost of prototype test jig is ~$20k, which is factor of two of pre-prototype test jig cost. $5k is budgeted for evaluation and radiation tests. The cost of the initial setup for production testing is estimated to be the same as that for prototype, but additional cost of $7500 for each of the 8 batches is included to account for replacing socket test boards and shipping. Therefore, $80k is allocated for production and maintenance of the required test jig to do the large volume testing over 1.5 years.
Page 6 of 17
UPenn The M&S costs for the various ASIC submissions are listed under BNL, which will submit the relevant orders. UPenn is responsible for independent evaluation of prototype ASICs with test jigs provided by BNL. Labor Costs BNL The labor required is dominated by ASIC design and evaluation testing, including the design of test stands, software and firmware development in the design and prototype phases of the PA/shaper ASIC. A test setup will also be designed and used to conduct irradiation tests of the PA/shaper ASIC. During the production phase, the work to be done is mostly debugging and measurements. For the ASIC development effort at BNL, it is estimated that 1.5 FTE per year (1 FTE for ASIC design and 0.5 FTE for testing during the prototyping stage, and 0.5 FTE engineer and 1 FTE technician during the production testing phase) are needed from FY18 through FY23. UPenn The manpower required for the UPenn contribution to the PA/shaper development effort is estimated based on more than 25 years experience for large scale HEP experiments and UPenn has been participating in the design of the upgrade electronics for the ATLAS LAr FE electronics since 2007. There has been close collaboration between BNL and UPenn in the R&D phase of this deliverable. A front-end ASIC in SiGe process, LAPAS, has been designed in 2009 by collaboration of UPenn and BNL. The UPenn manpower is estimated to be about 0.25 FTE per design and prototyping cycle through the R&D phase.
The above estimate for the combined BNL and UPenn effort is consistent with the previous experience with the development of MicroBooNE analog frontend ASIC. Each of the MicroBooNE ASIC has 16 channels, operating at liquid argon temperature. It was designed through 5 revisions, with an effort of 2.5 FTE (1 FTE ASIC design, 1.5 FTE testing) each year for 4 years (2009-2012). We consider the complexity of this deliverable to be similar to that of the MicroBooNE ASIC. 1000 MicroBooNE ASICs were produced. They were tested by 2 FTEs working for 3 months in 2013. Given the higher number of ASICs for this deliverable, a higher rate of testing is needed, which is accomplished by two sites, BNL and IN2P3 LAL with test stands for multiple ASICs at a time. Uncosted Labor There is no uncosted labor in this WBS. Travel Costs BNL
Page 7 of 17
For each design and test cycle, 3-5 trips to ATLAS meetings are expected, each costing about $2500, according to the current travel cost (see Attachment 6).
UPenn 1 trip to ATLAS meetings is expected costing about $2500 according to current travel cost.
Assumptions: An assumption for this collaborative effort is that the TSMC CMOS process will provide sufficient radiation tolerance and that the analog performance of the process is sufficient to meet the design goals of the upgraded ATLAS LAr calorimeter readout (See Risk RD-06-04-05-004), and that CMOS design is chosen by the ATLAS LAr HL-LHC Upgrade project (See Risk RD-06-04-05-003). Currently another design of the ATLAS HL-LHC LAr frontend analog readout ASIC is being developed by the IN2P3 LAL/OMEGA collaboration in France in 130nm CMOS technology. A common testing system for the French design and US design is being developed at BNL, which is being used to evaluate the performance of both ASICs in 2018. The collaboration being formed between BNL and IN2P3 LAL/Omega is expected to split the effort, independent of the final technology chosen. BNL and UPenn will collaborate with IN2P3 LAL/Omega on the development effort through the final prototype stage, and BNL and IN2P3 LAL will each be responsible for QA/QC testing of 50% of the production ASICs. Schedule Design, production and testing cycles:
Preprototype1: FY17-Q2 to FY18-Q1 Preprototype2: FY17-Q4 to FY19-Q2 Preprototype3: FY19-Q2 to FY20-Q3 Prototype: FY20-Q1 to FY21-Q3 Production: FY21-Q4 to FY23-Q4
ATLAS Milestones: Mar 2018: ATLAS LAr Frontend Analog Down-select May 2019: ATLAS LAr Frontend ASIC PDR May 2020: Preprototype3 available for FEB2 Slice Test May 2020: ATLAS LAr Frontend ASIC FDR May 2021: Prototype available for FEB2 Prototype Jul 2021: ATLAS LAr Frontend ASIC PRR Jul 2022: First batch of production ASIC for FEB2 Oct 2023: Completion of production testing.
Page 8 of 17
Risk Analysis:
In risk registry Comments: In case the CMOS technology can not deliver the performance, another alternative is to consider a design using the SiGe process. A preliminary design of a PA/shaper in SiGe has already been developed by UPenn working with BNL Instrumentation Division, so the new effort would already have a good starting point. Attachments: ● Attachment 1: MOSIS Quotation for submission of preprototype1 ● Attachment 2: MOSIS Quotation on ASIC Packaging ● Attachment 3: Actual cost of PCBs for FETB V1.0 and HLC1 TB ● Attachment 4: Component Costs for HLC1 TB ● Attachment 5: Component Costs for FETB V1.0 ● Attachment 6: Cost of A Typical One-week Trip to CERN ● Attachment 7: Cost of TSMC 130nm CMOS by CERN Foundry Service
Page 9 of 17
Attachment 1: MOSIS Quotation for preprototype1
MOSIS Quotation for production of 100 preprototype1 ASICs, additional 200 ASICs and packaging for 100 ASICs.
Page 10 of 17
Attachment 2: MOSIS Quotation on ASIC Packaging
Page 11 of 17
Attachment 3: Actual cost of PCBs for FETB V1.0 and HLC1 TB
Note:
• HLC1 is the preprototype1 Preamp/Shaper ASIC. • FETB is the common test board for Preamp/Shaper, used by both the US and French
ASIC prototypes.
Page 12 of 17
Attachment 4: Component Costs for HLC1 TB
Page 13 of 17
Attachment 5: Component Costs for FETB V1.0
Page 14 of 17
Page 15 of 17
Attachment 6: Cost of A Typical One-week Trip to CERN Air Fare: ~$1600, see flight reservation below. Lodging: 6 nights at CERN Foyer, 58CHF x 6 ~ $350, see CERN hostel reservation below. Per Diem: $450 Local Transportation: $100 Total: $2500
Reservation 1. Flight reservation from NYC to GVA
Page 16 of 17
Hostel reservation at CERN
Page 17 of 17
Attachment 7: Cost of TSMC 130nm CMOS by CERN Foundry Service
