05_Internal Memory New

8/18/2019 05_Internal Memory New

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William Stallings

Computer Organization

and Architecture

8th Edition

Chapter 5

Memori Internal


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Jenis-jenis Memori Semiondutor

Tipe Memori Kategori Penghapusan Mekanisme Tulis Votalitas

Random-access

memory (RAM)Baca Tulis

Secara Elektrik,

Tingkatan byteSecara Elektrik Volatil

Read-only

memory (ROM)

Baca Memori saja Tidak Mungkin

Mask

Non-volatil

Programmable

ROM (PROM)

Secara Eletrik

Erasable PROM

(EPROM)

Baca memori umumnya

Sinar UV, tingkatan

keping

Electrically Erasable

PROM (EEPROM)

Secara Elektrik, tingkatan

byte

Flash memorySecara Elektronik, tingkat

blok


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Semiconductor Memor!

• RAM

—Jenis memori

—Baca/Tulis

—Volatil

—Penyimpanan Sementara—Statis atau Dinamis


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Memor! Cell Operation


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"!namic #AM

• Bits disimpan sebagai muatan dalam apasitor

• Data yang disimpan men!adi bocor

• "si ulang secara berala yang menyegaranuntu penyimpanan data

• #onstrusi seder$ana

• %ebi$ ecil per bit

• %ebi$ mura$

• Perlu penyegaran siruit

• %ambat• Main memory

• Pada dasarnya analog

• Tingat biaya menentuan nilai


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"!namic #AM Structure


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"#AM Operation

• Saluran alamat diati&an etia nilai bit dari sel ini aan dibaca atauditulis

— Transistor bertinda sebagai suatu tombol yang tertutup 'membiaranarus mengalir( !ia tegangan berlau untu baris alamat dan terbua'tida ada arus mengalir( !ia tida ada tegangan yang berada padabaris alamat)

• Tulis

— Suatu sinyal berlau untu baris bit* +ig$ &or , lo- &or .

— #emudian sinyal diapliasian e baris alamat

* Muatan ditrans&er e apasitor

• Baca

— Baris alamat terpili$

* Transisitor dinyalaan dan muatan tersimpan pada apasitor aandiambil e baris bit dan ampli&ier yang sensiti&) Ampli&ier yangsensiti& bandingan tegangan apasitor dengan penilaian danpenentuan acuan sel berisi logia , atau logia .)


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#AM Statis

• Baris alamat digunaan untu membua atau menutup

tombol• Tida ada penyegaran yang diperluan untu

memperta$anan data

• #onstrusi yang lebi$ omples

• %ebi$ besar per bit

• lebi$ ma$al

• Tida perlu mere&res$ siruit

• 0epat

• 0ac$e

• Digital• 1lip1lop


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Stating #AM Structure


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Static #AM Operation

• Transistor arrangement gi2es stable logicstate

• State ,—0, $ig$3 04 lo-

—T, T5 o&&3 T4 T6 on

• State .—04 $ig$3 0, lo-

—T4 T6 o&&3 T, T5 on

• Address line transistors T7 T8 is s-itc$• 9rite * apply 2alue to B : compliment to

B

• Read * 2alue is on line B


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S#AM $ "#AM

• #eduaduanya Volatil

—Po-er $arus disediaan secara terus menerusepada memori untu memeli$ara nilainilai bit)

• Dynamic cell

—%ebi$ Seder$ana3 %ebi$ ecil—%ebi$ padat

—%ebi$ mura$

—Membutu$an penyegaran

—;nit memori yang lebi$ besar• Static

—%ebi$ cepat

—0ac$e


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#ead Onl! Memor! %#OM&

• Pola data permanen

—


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'!pes o( #OM

• 9ritten during manu&acture

—Very e>pensi2e &or small runs

• Programmable 'once(

—PR=M

—


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Organisation in detail

• A ,8Mbit c$ip can be organised as ,M o&,8 bit -ords

• A bit per c$ip system $as ,8 lots o& ,Mbitc$ip -it$ bit , o& eac$ -ord in c$ip , and

so on• A ,8Mbit c$ip can be organised as a 4.5C

> 4.5C > 5bit array

—Reduces number o& address pins

* Multiple> ro- address and column address

* ,, pins to address '4,,4.5C(

* Adding one more pin doubles range o& 2alues so >5capacity


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#e(reshing

• Re&res$ circuit included on c$ip

• Disable c$ip

• 0ount t$roug$ ro-s

• Read : 9rite bac

• Taes time

• Slo-s do-n apparent per&ormance


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'!pical )* M+ "#AM %,M ,&


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.acaging


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/5*0!te Module

Organisation


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)M0!te Module Organisation


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Interlea$ed Memor!

• 0ollection o& DRAM c$ips

• Erouped into memory ban

• Bans independently ser2ice read or -ritere?uests

• # bans can ser2ice re?uestssimultaneously


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Error Correction

• +ard 1ailure

—Permanent de&ect

• So&t rror

—Random3 nondestructi2e

—


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Error Correcting Code 1unction


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Ad$anced "#AM Organization

• Basic DRAM same since &irst RAM c$ips

• n$anced DRAM

—0ontains small SRAM as -ell

—SRAM $olds last line read 'c)&) 0ac$eF(

• 0ac$e DRAM—%arger SRAM component

—;se as cac$e or serial bu&&er


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S!nchronous "#AM %S"#AM&

• Access is sync$roniGed -it$ an e>ternal cloc

• Address is presented to RAM

• RAM &inds data '0P; -aits in con2entional DRAM(

• Since SDRAM mo2es data in time -it$ systemcloc3 0P; no-s -$en data -ill be ready

• 0P; does not $a2e to -ait3 it can do somet$ingelse

• Burst mode allo-s SDRAM to set up stream o&data and &ire it out in bloc

• DDRSDRAM sends data t-ice per cloc cycle'leading : trailing edge(


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S"#AM


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S"#AM #ead 'iming


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#AM02S

• Adopted by "ntel &or Pentium : "tanium

• Main competitor to SDRAM

• Vertical pacage * all pins on one side

• Data e>c$ange o2er 4C -ires H cm long

• Bus addresses up to 64. RDRAM c$ips at,)8Ebps

• Async$ronous bloc protocol

—5C.ns access time—T$en ,)8 Ebps


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#AM02S "iagram


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""# S"#AM

• SDRAM can only send data once per cloc

• Doubledatarate SDRAM can send datat-ice per cloc cycle

—Rising edge and &alling edge


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""# S"#AM

#ead 'iming


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Simpli(ied "#AM #ead 'iming


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Cache "#AM

• Mitsubis$i

• "ntegrates small SRAM cac$e ',8 b( ontogeneric DRAM c$ip

• ;sed as true cac$e

—85bit lines—&&ecti2e &or ordinary random access

• To support serial access o& bloc o& data

—)g) re&res$ bitmapped screen

* 0DRAM can pre&etc$ data &rom DRAM into SRAMbu&&er

* Subse?uent accesses solely to SRAM


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#eading

• T$e RAM Euide

• RDRAM

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