Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 1)
Operands & Addressing Modes
Dr Philip [email protected]
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 2)
Addressing modes
addr is address field of instruction Immediate addr is operand Register addr is register number in CPU – operand := [ addr ]
Direct addr is address in primary (main) memory – operand := [ addr ]
Indirect addr is register number (or memory address) – operand_address := [ addr ]
operand [ operand_address ]
Indexed addr is base address, index is a register – operand := [ addr + [ index ] ]
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 3)
Instructions
Two Operand InstructionsLabel: OPCODE Destination, Source ; Comments
Single Operand InstructionsLabel: OPCODE Operand ; Comments
Zero Operands InstructionsLabel: OPCODE ; Comments
Label is a user-defined identifier that is defined by the address of the instruction or item of data that follows.
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 4)
Operands (Addressing Modes)
Register Operandse.g. EAX, DX, AL, SI, BP, DS
Immediate Operands (Constants)e.g. 23, 67H, 101010xB, ‘R’, ‘ON’
Memory Operands[ BaseReg + Scale * IndexReg + Displacement ]e.g. [24], [BP], [ESI+2], [BP + 8 * DI + 16]
Source and Destination operands cannot both be a memory operand.Note: Some instructions use particular registers implicitly.
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 5)
DirectivesMost assemblers allow “global” variables to be allocated and definedsymbolically with a data definition directive, e.g.
MaxElem DW ? ; allocates a wordUsers DB 3 ; allocates a byte with initial value 3Total DD ? ; allocates a doubleword
Message DB “hello” ; allocates 5 bytes with text value helloSequence DW 1, 2, 3 ; allocates 3 words with values 1, 2 and 3List DW 50 DUP (0); allocates 50 words initialised to 0
Most assemblers also allow constant values to be defined symbolically:
Age EQU 22MyPointer EQU 1000
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 6)
Examples
Label Instruction Comment
MOV AH, CL ; AH := CL
ADD AX, [BX] ; AX := AX + Memory [DS:BX]
MOV AX, [BP+4] ; AX := Memory[SS:BP+4]
ADD AX, ES:[BX] ; AX := AX + Memory [ES:BX]
SUB EAX, 45 ; EAX := EAX - 45
MOV BYTE PTR [BX] , 45 ; Memory [DS:BX] := 45
ADD CH, [22] ; CH := CH + Memory [DS:22]
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 7)
More Examples
Label Instruction Comment
CMP EAX, ECX ; Compare operands and Set; EFLAGS register
JE forlabel ; if FLAGS.ZF = 1 then ; EIP := forlabel
forlabel: NEG AX ; AX := -AX
CALL print ; Call procedure print
RET ; Return from procedure
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 8)
Register Operand
Register
Operand found in the specified register
MOV AX, DXMOV AH, BLMOV SP, BPMOV DS, AXMOV EDI, ESI
MOV ES, DS ; DisallowedMOV CS, AX ; Disallowed
Depending on the instruction and processor, the operands can be located in any of the General Purpose Registers, Base and Index Registers, Segment Registers, FLAGS RegisterSome instructions such as IMUL and IDIV implicitly use operands contained in a pair of registers, e.g. in AX and DX.In most cases Dest & Source operands must be of the same size Seg. Reg to Seg. Reg moves are not allowed. Cannot move to CS either.
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 9)
Immediate (Constant) Operand
Constant
Operand is an immediate (constant) value
MOV AX, 22MOV AX, 16HMOV AX, 10110xBMOV EBX, 12345678HMOV BX, AgeMOV AL, ‘A’MOV AX, ‘MP’
Immediate values are encoded directly into the instruction.
Not normally applicable for Destination Operand
Doubleword constants on Pentium only
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 10)
Memory OperandsSpecify an address offset (effective address) using expressions of the form (different parts of expression are optional):
[ Base Register + Scale * Index Register + Displacement ]
1) Base Register (EAX, EBX, ECX, EDX, ESP, EBP, EDI, ESI)(only BX or BP on 8086)
2) Index Register (EAX, EBX, ECX, EDX, EBP, EDI, ESI)(only SI or DI on 8086)
Scale 2 or 4 or 8 (Pentium only)
3) Displacement (constant value)
Size of operand is normally inferred from Instruction or 2nd operand if register. We can explicitly prefix operand with BYTE PTR or WORD PTRor DWORD PTR.
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 11)
Default SegmentsType of Default Default Selection RuleReference Segment
Data Data (DS) All data references, exceptstack references & string instructiondestination references
Stack Stack (SS) All stack pushes & pops (via ESP) References which use EBPas Base Register
String Dest Extra (ES) Destination operand of stringinstructions.
Instructions Code (CS) All instruction fetches
Default Segments can usually be overridden e.g. ES:[EBP+2]
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 12)
Displacement (Direct Addressing)
[ Displacement ]
Specified constant value (called the displacement) gives offset.
MOV AX, [22]MOV AX, ES:[22]MOV [16H] , AXMOV BYTE PTR [22] , 98MOV EBX, [12345678H]
MOV CX, UsersMOV [MyPointer], AH
Displacements are encoded directly into the instruction.
Allows global variables with fixed offset values to be addressed directly.
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 13)
Example 1: MOV AX, [22]
Data Segment(e.g. DS * 16) 0
...2
AX-637
Instruction22
+22
-63722
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 14)
Example 2: MOV AX, ES:[22]
Extra Segment(e.g. ES * 16) 0
...2
AX
+738
+738
22
+22
Instruction22
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 15)
Example 3: MOV BYTE PTR [22], 98
Data Segment(e.g. DS * 16) 0
...2
MOV WORD PTR [26], 99
Instruction98
98
999926
2422
+22
Instruction22
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 16)
Base (Register Indirect)
[ Base ]
Contents of specified Base Register gives offset.
MOV AX, [BX]MOV [BP], ALMOV AX, [DI]MOV [SI] , AHMOV EBX, [ESI]MOV [EAX], ECX
Pentium: EAX, EBX, ECX, EDX,ESP, EBP, EDI, ESI
8086: BX, BP, DI, SI
Since the value in the Base Register can be updated, it can be used to dynamically address (point to) variables in memory, e.g. array elements, linked lists, trees.
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 17)
Example 1: MOV AX, [BX]
Data Segment0
...2
AX
-100
-100
BX66
66
+66
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 18)
Example 2: MOV [BP], AL
Stack Segment(e.g. SS * 16) 0
...2
AL55
BP12
5512
+12
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 19)
Base + Displacement (Register Relative)
[ Base + Displacement ] or Displacement [ Base ]
Sum of specified Base Register and Displacement gives offset. Displacement can be negative.
MOV AX, [BX+4]MOV [BP+2] , DHMOV AX, [DI–6]MOV DL, [SI+Age]MOV AH, [EAX+12]MOV List [BX] , CXMOV DX, List [BP–2]
Pentium: EAX, EBX, ECX, EDX,ESP, EBP, EDI, ESI
8086: BX, BP, DI, SICan be used to access record fields, e.g. Base Register = start of record, Displacement = position of field.Can be used to access array elements, e.g. Displacement = start of array, Base Register = position of elementCan be used to access parameters & local variables.
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 20)
Example 1: MOV AX, [BX+4]
Data Segment0
...2
AX2244
BX12 BX points to Start
of a Record with fields X, Y & Z
+4 selects field Z
12 XY
2244
+12
16
+4
Instruction4
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 21)
Example 2: MOV AX, [BX+4]
Data Segment02
AX-99
BX12
6
1012
A[0]A[1]A[2]A[3]A[4]A[5]-99
1416
8+12
4
+4Instruction
+4
+4 points to start of an Array
BX holds “index” toarray element
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 22)
Base + Index (Based Indexed)
[ Base + Index ] or [ Base ] [ Index ]
Sum of specified Base Register and Index Register gives offset
MOV CX, [BX + DI]MOV [EAX + EBX] , ECXMOV CH, [BP] [SI]MOV [BX] [SI] , SPMOV CL, [EDX] [ EDI]MOV [EAX] [EBX] , ECXMOV [BP + DI] , CX
Pentium: EAX, EBX, ECX, EDX,ESP, EBP, EDI, ESI
8086: Base Reg = BX, BPIndex Reg = DI, SI
Can be used to access array elements, e.g. Base Register = start of array, Index Register = position of element.
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 23)
Example: MOV AX, [BX+DI]
Data Segment0
...2
AX-27
+6
BX12
Start of Array12 A[0]
A[1]14
-2716 A[2]18
+12
DI6
DI is index toarray element
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 24)
Base + Index + Displacement (Based Relative Index)
[ Base + Index + Displacement]
Sum of specified Base Register and Index Register and Displacement gives offsetAlt Syntax:
Disp1 [Base] [Index+Disp2]Displacement = Disp1+Disp2
MOV AX, [BP+DI+10]MOV DH, [BX][DI-6]MOV AX, List [BX][DI]MOV List [BP][DI–64], DXMOV EAX, List [EBX][ECX+2]
Pentium: EAX, EBX, ECX, EDX, EBP, EDI, ESI
8086: Base Reg= BX, BPIndex Reg = DI, SI
Also known as Relative Based Index
Can be used to access local (stack) arrays, arrays of records, 2D arrays.
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 25)
Example: MOV AX, [BP+DI+10]
Stack Segment0
AX+67
A[0]22
+6726
A[1]
28A[2]
24
DI6
+6
12...
BP12
+12
BP+10 points to start of array on stack
DI holds “position” of array element
+10
Instruction+10
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 26)
(Scale*Index) + Displacement (Scaled Index)
[ Scale * Index + Displacement]
Product of Index Register and a constant scaling factor (2, 4 or 8) added to specified Displacement to give offset.
MOV EAX, [4 * ECX + 4]MOV List [2 * EBX], CXMOV List [2 * EBX+32], DXMOV AX, [2 * EDI+Age]
Only Pentium
Supports efficient access to array elements when the element size is 2, 4 or 8 bytes, e.g. Displacement = offset to beginning of array. Index Register = position of desired element, Scale = element size in bytes
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 27)
Example: MOV AX, ES:[2*ECX+4]
Extra Segment02
AX-99
ECX6
6
1012
A[0]4A[1]A[2]A[3]A[4]A[5]-99
1416
8+(2*6)
+4Instruction
+4
+4 points to start of a Array
ECX holds position ofarray element
Elements = 2 bytes
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 28)
Base + (Scale * Index) + Displacement
[ Base + Scale * Index + Displacement]
Product of Index Register and a constant scaling factor (2, 4 or 8) added to specified Base Register and Displacement to give offset.
MOV EAX, [EBX][4*ECX]MOV [EAX][2*EBX] , CXMOV AX, [EBP][2*EDI+Age]MOV List[EAX][2*EBX+32], DX
Known as Based Scaled Index
Only Pentium
Supports efficient access to local arrays on the stack when the element size is 2, 4 or 8 bytes.
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 29)
Example: MOV EAX, [EBX+4*EDX+10]
Data Segment0
...
EAX12349908H
EDX2
12
EBX12
+12
EBX points to start of record
EBX+10 points to start of array within record
EDX holds “position” of array element.
Elements = 4 bytes
+10
Instruction+10
A[0]22
A[1]26
A[0]
28A[1]
24
1234H9908H30
32
+(4*2)
Computer Architecture (P. Leong) Pentium Arch. - Operands & Addressing Modes (page 30)
Think about
1. Why zero, single and two operand instructions occur in the 8086 instruction set.
2. The difference between a directive and an assembly language statement
3. The difference between all of the addressing modes4. How high level language statements like a = b[5]+c are
translated to assembly language and what addressing modes are used
5. The machine organisation required to handle the addressing modes