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IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 8, NO. 3, AUGUST 2012 511

Multi-DSP and -FPGA-Based Fully DigitalControl System for Cascaded Multilevel Converters

Used in FACTS ApplicationsTevhid Atalik, Student Member, IEEE, Mustafa Deniz, Student Member, IEEE, Erkan Ko,

Cem zgur Gerek, Student Member, IEEE, Burhan Gltekin, Student Member, IEEE,Muammer Ermis, Member, IEEE, and Isik adrc, Member, IEEE

AbstractIn this paper, a fully digital controller based onmultiple digital signal processor (DSP) and field-programmablegate array (FPGA) boards has been proposed for parallel-oper-ated cascaded multilevel converters (CMC) used in flexible ACtransmission system (FACTS) applications. The proposed systemis composed of a DSP-based master controller in combinationwith a multiple number of slave DSP boards, FPGA boards,

microcontrollers, a programmable logic controller (PLC), anindustrial computer, and their peripherals in interaction. Inter-communication of these digital controllers is achieved mainlythrough fiber-optic links, via synchronous serial data link wher-ever a high-speed, full duplex communication is needed, and viaasynchronous serial communication interface wherever relativelyslow communication speed is required. The proposed fully-dig-ital control system has been implemented on a sample 11-levelCMC-based 154-kV, 50-MVAr transmission type staticsynchronous compensator (T-STATCOM). Field test results haveshown that the proposed fully digital control system provides goodtransient response and steady-state characteristics for the oveallsystem including protection and monitoring functions.

Index TermsCascaded multilevel converter (CMC), digitalcontroller, digital signal processor (DSP), field-programmable gatearray (FPGA), transmission type static synchronous compensator(T-STATCOM).

I. INTRODUCTION

I NCREASING need for high-power converters in powerelectronics applications, such as flexible ac transmissionsystems (FACTS), has brought on the development of complexconverter configurations and sophisticated control schemes.High-voltage and high-power converters employing multilevel

Manuscript received November 30, 2011; revised January 21, 2012; acceptedFebruary 28, 2012. Date of publication April 09, 2012; date of current versionJuly 23, 2012. Paper no. TII-11-937.

T. Atalik, M. Deniz, and E. Ko are with the Power ElectronicsDepartment, Tubitak UZAY Institute, 06800 Ankara, Turkey (e-mail:[email protected]; [email protected]; [email protected]).

C. . Gerek, B. Gltekin, and M. Ermis are with the Electrical andElectronics Engineering Department, Middle East Technical University,06531 Ankara, Turkey (e-mail: [email protected]; [email protected]; [email protected]).

I. adirci is with the Electronics Engineering Department, Hacettepe Univer-sity, 06800 Ankara, Turkey (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TII.2012.2194160

converter topologies are being increasingly used in the trans-mission and distribution systems, where the high number ofswitching devices and dc link stages make necessary the useof parallel processing techniques in the control loops. This canonly be implemented by digital control techniques via advanceddigital signal processors (DSPs) and field-programmable gate

arrays (FPGA) used in combination for fast calculation andaccurate timing of the switching signals of multiple powersemiconductors [1][14].

The state-of-the-art FPGA technologies and their contribu-tion to industrial control applications have been reviewed in theliterature [1] and [2]. Various FPGA-based implementations ofdigital control algorithms for power electronics converters havebeen presented in [3][6]. On the other hand, a DSP-based im-plementation of a three-phase, four-wire distribution-type staticsynchronous compensator (D-STATCOM) for voltage regula-tion and power quality improvement has been described in [7].A dSPACE DSP, which is a real-time control system based on afloating-point processor and a slave DSP has been used to imple-

ment the control algorithm of the D-STATCOM equipped witha single three-leg voltage source converter (VSC) in the labo-ratory. Furthermore, PC-DSP-based unified control system de-sign for FACTS devices has been described in [8]. Basic op-eration principles of a current source converter (CSC)-basedSTATCOM with DSP-controlled space vector PWM have beenstudied in [9] and verified by laboratory tests.

Digital controller platforms for multilevel power electronicsconverters are typically based on a single high-performanceDSP and a powerful FPGA [10], [11]. An integrated solu-tion with a single floating-point DSP and an FPGA has beenproposed for grid-connected converters applied to distributedpower generation systems [12]. The design process in [12]adopts a modular approach, utilizing again a DSP and an FPGA,as verified on a 150-kVA experimental setup. A STATCOMbased on the emitter turn-off thyristor (ETO) has been im-plemented in the laboratory on a three-level, single H-bridgeper-phase VSC topology via a single DSP-FPGA-based controlsystem [13]. In [14] and [15], the design and implementationof a real-time digital simulator for a VSC-based D-STATCOMpower system has been presented.

The implementation of digital control systems only for singleVSC- or CSC-based two-level or multilevel converters havebeen reported in the literature. In other words, a digital controlscheme based on multi-DSP and -FPGA and developed for par-

allel-operated multilevel converters used in FACTS applications1551-3203/$31.00 2012 IEEE

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512 IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, VOL. 8, NO. 3, AUGUST 2012

has not been reported yet in the literature. In this paper, a fullydigital control system based on multiple DSPs, FPGAs and

controllers in interaction has been proposed for more than oneparallel-operated Cascaded Multilevel Converters (CMC) usedin FACTS applications. The proposed digital controller systemhas been implemented on a 154-kV, 50-MVAr transmissionSTATCOM (T-STATCOM) system consisting of five CMCsoperating in parallel for either reactive power compensation orterminal voltage regulation purposes. The performance of theimplemented system has been verified by extensive field testsconducted in the transmission substation where T-STATCOMhas been installed.

II. OPERATION PRINCIPLES OF CMCS IN FACTS APPLICATIONS

A CMC-based T-STATCOM as a FACTS device can be oper-ated in one or more than one of the following modes connectedto the transmission system:

1) reactive power compensation;2) terminal voltage regulation;

3) power system stability improvement such as inter-area os-cillation damping.

This paper deals only with modes defined in 1) and 2).Fig. 1 shows parallel operated CMCs. They are connected

to the high-voltage (HV) or extra high-voltage (EHV) bus of thetransmission system via a medium voltage (MV) to HV or EHVcoupling transformer. To suppress high-frequency harmoniccomponents of the CMCs output voltage waveform and tomaintain a good current sharing among paralleled CMCs, eachCMC is connected to the MV side of the coupling transformerthrough a series filtering reactor. Before putting the systeminto service, dc link capacitors of CMCs are charged in apre-programmed manner by the pre-charge resistor in Fig. 1.

In a star-connected CMC, number of H-bridges are con-nected in series in each phase as shown in Fig. 2. series-con-nected H-bridgesgive stepsin line-to-neutral voltagewaveforms and steps in line-to-line voltage wave-forms, where is the number of levels from positive peak tonegative peak of the waveform under consideration. The voltageand current waveforms on the supply side, at the ac side of theCMC and at its dc side are marked on the schematic diagramof the T-STATCOM in Fig. 3. The series reactor betweenthe supply and the CMC is a combination of series filter reactor

and the leakage reactance of the coupling transformer.

A. Active and Reactive Power Control

Active and reactive powers flowing to the CMC are approxi-mated, respectively, by

(1)

(2)

as proven in [16] where

fundamental voltage component at the point ofcommon coupling (PCC) referred to CMC side;

fundamental component of the CMC ac voltage;

Fig. 1. Simplified single line diagram of a T-STATCOM with m number ofparalleled CMCs.

total series reactance including leakage reactanceof the coupling transformer referred to the CMCside and equivalent reactance of input filterreactors;

power angle between and ;active and reactive power inputs to the CMC.

Sample waveforms for the line-to-neutral supply voltage,CMCs 11-level ac voltage and their fundamental componentsare as given in Fig. 4.

The two CMC voltages in Fig. 4, one for capacitive opera-tion and the other for inductive operation, have different peakvalues for their fundamental components although the peaks ofthe staircase voltages are the same. The amplitude of the fun-damental component is adjusted by the pulse width modulation(PWM) technique. This is because should be smaller thanfor inductive operation of CMC while should be greater than

for capacitive operation, as can be understood from (2). Fur-thermore, and waveforms should be in the same phase for

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ATALIK et al.: MULTI-DSP AND -FPGA-BASED FULLY-DIGITAL CONTROL SYSTEM FOR CMCs 513

Fig. 2. CMC having number of series-connected H-bridges in each phase.

Fig. 3. Schematic diagram of a CMC-based T-STATCOM.

Fig. 4. Sample line-to-neutral voltage waveforms at the supply side and CMCside (theoretical).

a lossless CMC. However, in practice, the CMC losses shouldbe supplied from the source by allowing the required amountof active power flow to the CMC. Active power flow is directlyproportional to power angle in (1).

Since CMC losses are very low in comparison with its MVArrating, gets quite a low value during operation in the steady

Fig. 5. Exaggerated diagrams for and in and control. (a) Definitionsof and . (b) Phasor diagram for capacitive operation.

state, that is, is lower than 1 . Load angle and phase angleare illustrated in Fig. 5 in an exaggerated manner. is mag-

nitude-wise less than 90 in the steady state, but very close toeither 90 or 90 depending upon the operation mode of theT-STATCOM, respectively, capacitive or inductive. As can be

understood from Fig. 5, should lag behind , that is, isalways positive for operation in the steady state.

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Fig. 6. 11-level line-to-neutral voltage waveform [16].

B. Waveform Synthesizing

The three-phase voltage waveforms created by each CMCwill be approximated to pure sine waves at a supply frequencyby superimposing rectangular waves, as illustrated in Fig. 6,where is the number of H-bridges connected in series in eachphase. The voltage waveform in Fig. 6 has odd quarter sym-

metry. Each rectangular wave can be produced by any one ofthe H-bridges. The widths of these rectangular pulses aredetermined by the frequencies of low-order harmonics to beeliminated, and the magnitude of the fundamental componentof the voltage required for reactive power to be generated bythe T-STATCOM not only for the reactive power compensationmode, but also for the terminal voltage regulation mode.

Harmonic elimination in three-phase ac voltage waveformsis achieved according to the selective harmonic eliminationmethod (SHEM) [17][19]. H-bridges in each phase providesus degrees of freedom. One of them is allocated for thefundamental component, while the remaining for the

low-order harmonics to be eliminated. As an example, fifth,seventh, 11th, and 13th low-order harmonics can be eliminatedfor . Although line-to-neutral voltage waveform hasthird-harmonic voltage component and its integer multiples,these harmonics will not be present in the line-to-line voltagewaveforms when CMC performs balanced-voltage operation.A similar conclusion can be drawn also for even harmonics inthe steady state owing to odd quarter symmetry.

The optimum angles in Fig. 6 are calculatedoffline by using a hybrid algorithm. The hybrid algorithm isa combination of the genetic algorithm [20] and [21] and thegradient-based method. These calculations are repeated several

times for different modulation indices and then stored in alookup table (LUT), as described in [16].

TABLE IMAXIMUM AND MINIMUM VALUES OF AND PI PARAMETERS

The magnitude of the CMC fundamental output voltage canbe controlled by adjusting modulation index , as given in

(3)

where , is the set value of fun-damental line-to-line rms output voltage of each CMC,denotes the maximum value of fundamental line-to-line rmsvoltage that can be produced by one of the HBs in any CMC,and is the total mean dc link voltages of each phase of CMC[16].

Maximum and minimum values of are dictated by rated ,, and in (2) for the design value of . It is worth noting

that the maximum value of corresponds to rated in capac-itive mode while the minimum value of to rated in induc-tive mode. The resolution of control depends on the numberof steps between maximum and minimum values of . As can

be understood from (2), the number of steps in the stepwise ad-justment of is directly proportional to for a pre-specifiedresolution in control.

When one or more than one CMC/s is/are disconnected fromthe FACTS device having parallel CMCs, maximum and min-imum values of will be changed. This is because equivalentseries reactance in Fig. 3 depends upon the number of par-allel CMCs in service. This will also affect the optimum valuesof PI controllers parameters for the reactive power compensa-tion and the terminal voltage regulation modes.

As an example, for the T-STATCOM system with, minimum and maximum values of , together with PI con-

troller parameters ( and ) for reactivepower compensationmode as a function of the number of active CMCs, (out of mnumber of parallel CMCs) are as given in Table I.

C. Equalization of DC Link Capacitor Voltages

The major drawback of multilevel converters is the voltageequalization problem of dc link capacitors [16][29]. The meanvalue of total dc link voltage of each CMC is given by

(4)

in terms of supply voltage at PCC referred to the CMC side,where is the rms line-to-line voltage at PCC.

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Fig. 7. Some operation modes of an H-bridge.

Since each CMC is composed of HBs in each phase, themean dc link voltage of each HB is given by

(5)

is kept constant by control as given in (1) at its designvalue; however, is to be kept nearly constant at the valuegiven by (5) by a proper voltage-equalization method. Conven-tional selective swapping (CSS) [23], [24] or modified selectiveswapping (MSS) [16] methods can be used for this purpose. Thefully digital control system described in this paper permits theimplementation of both CSS and MSS methods.

In order to be able to apply the SSM, charging/dischargingstates and instantaneous voltages of dc link capacitors should becontinuously monitored by the controlsystem. If the current into

converter and the voltage are both positive or negative, the inputpower to the HB converter is positive and, hence, the associateddc link capacitor is going to be charged. On the other hand, ifone of these quantities is positive while the other is negative,the input power to HB is negative and, hence, the associated dclink capacitor is going to be discharged [16]. Thus, in order todetermine which HB/s are going to be interchanged at each levelchange in CSS method and at each pre-specified time period inthe MSS method, the values of individual instantaneous dc linkcapacitor voltages, polarity of the voltage and direction of thecurrent should be measured by the control system. Charging,discharging, and bypass states of a typical dc link capacitor areas illustrated in Fig. 7.

If the selective swapping algorithm or any other method suchas those in [19] and [21] were not employed in the operation

of each CMC, the effective switching frequency (the numberof turn-on in 1 s) would be kept at an absolute minimum ofsupply frequency (50 Hz) at the expense of drastic peak-to-peakvoltage fluctuations around design value of . This may resultin a failure in either power semiconductors or dc link capacitorsin a short time period.

The performance of fully digital control system in the imple-mentation of MSS method will be illustrated in Section IV of thepaper. The objectives and major functions of the digital controlsystem in view of the operation principles of CMC in FACTSapplications, possible control system topologies, and detaileddescription of the chosen control system topology will be de-scribed in Section III.

III. DIGITAL IMPLEMENTATION OF CONTROL SYSTEM

CMCs used in FACTS applications are being custom-de-signed to meet the needs of the power system to which theyare connected. They should be kept in service continuouslywith the minimum number of failures and, hence, interruptions

during their economic life. Furthermore, to meet the varyingrequirements of the power system in the moderate and longterms, flexibility and modularity should also be taken intoaccount in their design. Therefore, the objectives in the designof the control system are set out as follows:

improved reliability; redundancy; ease in implementation; EMI immunity.The major functions of the control system are as given here:

1) waveform synthesizing;2) closed-loop control;3) protection;4) built-in monitoring;5) remote monitoring and control.For a FACTS device which is composed of parallel oper-

ated CMCs and cascaded H-bridges in each CMC phase, oneof the following topologies may be considered in the design andimplementation of its digital control system.

1) A single central control system may be used. A powerfuland advanced FPGA board can be used for relatively lowvalue of and . The major drawbacks of this controlsystem topology are: 1) lower reliability; 2) lack of re-dundancy and flexibility; and 3) complexity of the em-bedded software. Therefore, this option is avoided in the

design and implementation of a control systemfor a sampleFACTS application.2) A DSP-based central controller may be used in combina-

tion with FPGA boards. The central controller needs apowerful and advanced DSP chip. The FPGA board foreach CMC should be equipped with analog-to-digital con-verter (ADC) chips in order to be able to protect powersemiconductors and dc link capacitors of each CMC. Thisdesign approach avoids the major drawback of the controlsystem topology given above.

3) A DSP-based master controller may be used in combina-tion with pairs of FPGA and slave DSP boards. Thistopology eliminates the need for several numbers of ADC

chips since DSP chips have their own internal ADCs.Since it is more difficult to develop embedded software

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on an FPGA platform than the equivalent DSP board,some proper parts of the FPGA software in the abovetopology are developed on the slave DSPs. Thereby, thiscontrol system topology provides ease and time saving inthe development of the overall control system software incomparison with the second control system topology.

In summary, only the second and third control systemtopologies are found to be viable solutions for the digitalcontrol system of a CMC used in FACTS applications. Theirhardware costs are nearly the same but much lower than 1%of the overall system cost. However, research and developmentcosts of the associated software are considerable in the overallsystem cost. If, in the second topology, each FPGA wereprogrammed according to usual use of FPGA ICs, then thesoftware development cost would be at least several tens oftimes higher than that of the third topology. In order to reduceit, a DSP core can be embedded inside each FPGA IC to servefunctions of slave DSP chips in the third topology. In spite ofthis countermeasure against very high development costs, the

software development for the second topology is still muchmore complex and a time-consuming task in comparison withthat of the third topology. Therefore, in the sample FACTSapplication, the third control system topology is preferred. Itsblock diagram representation is given in Fig. 8.

A. Control System Architecture

In the sample FACTS application, the number of paralleledCMCs is five and the number of series connectedH-bridges in each phase of the CMC is also five . Thissystem can control the reactive power produced in the rangefrom 50 to 50 MVAr in a continuous manner. This systemcreates 11-level line-to-neutral voltage waveform and21-level line-to-line voltage waveform at 10.5-kV line-to-line,50 Hz.

Technical specifications and the type numbers of IC boardswhich are used in the sample FACTS application are given inTable II. If the number of series HBs in each phase of a CMCis greater than six , either a more advanced version ofFPGA board in Table II or three of the same FPGA, one for eachphase of each CMC, are to be used. On the other hand, if morethan five CMCs are going to be operated in parallel inthe same FACTS device, a Master DSP Expansion Board can beused between the master DSP and slave DSPs in Fig. 8 and theCommunication Interface Board is to be improved.

B. Communication System

Major components of the control system in Fig. 8 intercom-municate mainly through fiber optic cables for EMC. The elec-trical isolation between the control system and m number ofCMCs is also achieved by fiber optics. On the other hand, ex-ternal subsystems such as conventional protection relays, cir-cuit-breakers (CBs), battery-monitoring unit, PLC and indus-trial computers need copper-wire-based communication bus anddigital I/O bus. Fiber-optic communication buses, fiber-opticdigital I/O buses, copper-wire-based communication buses, andcopper-wire-based digital I/O buses are marked, respectively, byred, blue, brown, and green colored lines in Fig. 8.

Digital communication rate is largely determined by theneeds of the application. In the sample system, all necessary

calculations are completed within a 40- s time period. These17 pieces of word data, including modulation indices, phaseangles, line current directions, dc link capacitor referencevoltage, PI coefficients, and check-sum words should be sent toFPGA boards by the slave DSP Boards as quickly as possiblesuch as in a 20- s time period. This leads to a time delayof s s s in control action. However, thecommunication speed between the slave DSP board and theFPGA board is limited by the baud rate of the chosen DSPboard, which is 10 Mb/s.

To be on the safe side, the baud rate is chosen to be 9.375 Mb/swhich is 1/16 of the DSP clock frequency (150 MHz). Thischoice is consistent with the communication limit of the chosenfiber-optic receiver (HFBR-2528) and the transmitter (HFBR-1528). This choice gives 29 s 40 s time delay in controlaction which is found to be quite satisfactory in the field tests.

The communication need between master DSP and PLCis much slower than the one between slave DSP and FPGAboards. The chosen communication speeds for the sample ap-

plication are as marked on Fig. 8. The Synchronous Serial DataLink, which is named SPI (Serial Peripheral Interface) has beenchosen wherever a high-speed, full-duplex communication isneeded between the two devices. However, 210-ns maximumpropagation delay in the fiber-optic links of the sample appli-cation causes communication error at the input of the slavedevice. To compensate for this error, SPI communication hasbeen applied in two half-duplex links between the slave DSPand FPGA pairs in Fig. 8. Since the amount of data that will betransmitted from 3xn HBs (dc link capacitor voltages, heatsinktemperatures, pressure valve status of dc link capacitors, andoperation status of discharge circuits) to the associated FPGABoard in each CMC is low and hence the required communi-

cation speed is relatively slow, half-duplex asynchronous-typeserial communication interface (SCI) has been used betweenDC_VM Boards and the associated FPGA board as marked onFig. 8.

Owing to similar reasons, the SCI communication bus hasalso been preferred between the master DSP Board and slaveDSP Boards, but in full-duplex form.

C. Master DSP Board

The master DSP board contains two DSP chips: one for themajor control functions and serial communication with PLC andtwo slave DSP boards, while the other for under/over frequency

protection and communication with three remaining slave DSPboards. The number of DSP chips can be increased by one forevery additional three CMCs. The major functions of the masterDSP board are as described here.

1) Upon the receipt of the start command from the PLC or re-mote start command via the industrial computer, the masterDSP board sends a command to Slave DSP Boards to startthe first phase of the dc link capacitors pre-charge pe-riod. In this pre-charge phase, dc link capacitors of HBsare charged in a controlled manner to a peak voltage of

via the pre-charge resistor in Fig. 1 and theanti-parallel diodes of IGBTs. After the receipt of signalssent by Slave DSP Boards and showing the successful com-

pletion of the first pre-charge phase, the master DSP sendsa signal to all slave DSPs to initiate the second phase of

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Fig. 8. Block diagram representation of multi-DSP and -FPGA based fully digital control system for CMCs.

the pre-charge period. This is because the dc link capacitor

voltages obtained in the first phase are lower than the refer-ence value of capacitor voltages for normal operation in the

steady state ( 1900 V for the sample application). DC

link capacitors will then be charged to their reference valuein groups sequentially through switching of the IGBTs by

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Fig. 9. Master DSP board. (a) Generation of and by master DSP board. (b) View of the master DSP board.

TABLE IITECHNICAL SPECIFICATIONS OF IC BOARDS IN FIG. 9

the cooperative operation of slave DSP and FPGA boards.After the successful completion of the second pre-chargephase, the master DSP sends a command to PLC to bypassthe pre-charge resistor.

2) Operation mode of the FACTS device is set by the operatorand kept active by the master DSP board. These modes are:1) reactive power compensation and 2) terminal voltageregulation. In the case of mode 1), the set value of the re-active power that will be generated by the FACTS de-vice is calculated by the master DSP from the sampled data

(25 kS/s per channel) of the line-to-neutral voltages at PCC, supply side line currents ,

Fig. 10. Reactive power control by the master DSP.

and l ine c urrents o f FACTS device as s hownin Fig. 9. Reactive power consumption of the load side

is calculated from

(6)

by the master DSP, where and are the reac-tive powers on the supply and FACTS device sides,respectively.

Since for unity power factor (pf) opera-tion, then the master DSP board calculates modulation in-dices for parallel-operated CMCsby using the digitally implemented proportional-integral(PI) controller in Fig. 10. These modulation index valuesare then sent to slave DSP boards.If there are more than two feeders at the bus to whichthe T-STATCOM is connected, the definition of the loadside becomes a critical issue in the design. This makesnecessary the separation of feeders by simultaneous reac-tive power measurements into two groups having inductivepower factors and capacitive power factors at any pre-spec-ified short time period. in (6) should therefore be

taken as the sum of either inductive reactive power de-mands or capacitive reactive power demands of the group

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Fig. 11. PLL generation by slave DSP.

of feeders in any pre-specified time period. This will be de-termined by the master DSP board and subject to changefrom one period to the next period. However, this was notthe case for the sample application. Source and load sides

were fixed in view of the active power flow.However, in terminal voltage regulation mode [mode-2)],the master DSP board calculates modulation index valuesto bring the voltage at PCC to its reference value

set by the operator. The terminal voltage regulationmode requires a new set of PI controller parameters (and ) in Fig. 10. Since the T-STATCOMis a nearly sym-metrical VAr generating device, in the system sizing study,the T-STATCOM may be combined with conventional cir-cuit-breaker switched shunt-capacitor banks and/or shunt-reactor banks.This would allow an increase in not only the terminalvoltage regulation capability, but also the reactive powercompensation capability of the T-STATCOM. The masterDSP board would determine which conventional shunt de-vice is to be connected to or disconnected from the busbarat any time in addition to the control of T-STATCOM.It is worth noting that the number of switchings for theconventional shunt devices cannot be more than a fewtimes per day.

3) The master DSP board also continuously refreshes thenumber of active CMCs, out off installed CMCunits. The modulation index values that will be sent toslave DSP boards of active CMCs will then be automati-cally updated by the controller in Fig. 10 implemented on

the master DSP board. Maximum and minimum values ofas a function of are stored in the program memoryof the master DSP board which were already described inSection II and Table I.

4) The master DSP board also carries out some protective ac-tions on both FACTS device and CMC unit bases in aninteractive manner together with PLC, slave DSPs, andFPGAs. These functions will be described later in thissection.

5) Upon the receipt of a stop command from the operator, themaster DSP board communicates with FPGAs via slaveDSPs to turn off IGBTs. The FACTS device then stays inthe stand-by mode. If a stop signal arising from a fault or a

component failure is received from the PLC or slave DSPboards, the master DSP board sends a command to the PLC

to open the main CB of the FACTS device. The master DSPboard does not open the main CB in the case where the faultin one of the CMC units is successfully cleared by openingonly the CB of the faulty CMC according to the decision

made by the associated slave DSP board. For permanentfaults and inspection-maintenance purposes, the dc link ca-pacitors are discharged by the chopper circuit on DC_PDBoards in Fig. 8 under the control of FPGA Boards. Themaster DSP board receives the discharge command fromthe PLC and sends it to FPGA boards via the slave DSPboards.

6) The master DSP board continuously checks the validity offiber-optic links connected to the PLC and the slave DSPboards.

D. Slave DSP Board

Each slave DSP board contains two DSP chips: one for thecontrol purposes whilst the other for protection purposes. Themajor functions of the Slave DSP Board are described here.

1) Since each CMC should be synchronized with the supplyvoltage at PCC during its operation, the necessaryphase-locked loop (PLL) signal is generated individu-ally by each slave DSP board. The option of a singlePLL signal that will be generated by the master DSP iseliminated in order to avoid the undesirable delay in thecommunication between master and slave DSPs. Eachslave DSP board generates three PLL signals one for eachline-to-neutral voltage. Fig. 11 shows the block diagram

representation of the digital PLL implementation. To ap-proximate the performance of the digital implementationto that of an equivalent analog PLL circuit, the supplyvoltage waveform has been continuously sampled at a rateof 25 kS/s and the sine table in Fig. 11 is composed of2048 1 array over one complete cycle.

2) In order to equalize dc link capacitor voltages, the se-lective swapping algorithm can be used as explained inSection II-C. This makes necessary the determination ofthe direction of the CMC line currents. For this purpose,slave DSP boards sample the corresponding line currentwaveforms at a rate of 25 kS/s, calibrate the associated acsignal and make decision whether the current is greater

than zero at each sampling instant. Each slave DSP boardthen sends a pulse train (1 for positive and 0 for negative

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Fig. 12. FPGA and DC_VM boards. (a) Generation of firing signals by FPGA. (b) View of FPGA board. (c) View of DC_VM board.

current values) via SPI communication link to the associ-ated FPGA board.

3) Each slave DSP board computes active and reactivepowers, and and rms values of ac quantities, and

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for the associated CMC and sends these signals to theindustrial computer in Fig. 8 for monitoring purposes.

4) According to the calculated 20-ms and 1-s averaged rmsvalues of , the slave DSP board carries out over/undervoltage and unbalanced protection functions for its CMCunit. However, the overcurrent protection is carried out onthe basis of both the instantaneous and rms values of CMCline currents. The slave DSP board is also equipped with ananalog overcurrent protection circuit for further reliability.If digital over/under voltage or unbalance protection algo-rithm detects a signal exceeding the pre-specified limits, analarm signal will be generated and sent to the master DSP.This signal is also sent to FPGA to turn off IGBTs. On theother hand, if the digital overcurrent algorithm detects asignal exceeding pre-specified limits, a trip signal will begenerated and sent to both the master DSP and the asso-ciated FPGA. The master DSP will then send a trip signalto the CB of the associated CMC via the PLC while theFPGA board turns off the IGBTs of the related CMC.

5) Each slave DSP board continuously checks the validity offiber-optic links connected to the associated FPGA boardand the master DSP.

E. FPGA Board

Each FPGA board is composed of an FPGA chip, a multi-plexer circuit, fiber-optic transmitters/receivers, and other pe-ripheral devices. The major functions of a FPGA Board can besummarized as follows.

1) CMC losses are compensated by allowing active powerflow from the supply to the FACTS device. Active powerflow is controlled by load angle in Fig. 5 (Section II-A).To control the value of , the FPGA board first comparestotal dc link voltage of each CMC with its referencevalue, then processes the error signal with a PI controlleras shown in Fig. 12. This means that the ac voltage wave-form synthesized by the FPGA should be shifted bywith respect to supply voltage at PCC. Therefore, thePLL signal sent by the related slave DSP board should beshifted by angle during the implementation of the activepower control by the FPGA board. To improve the wave-form synthesizing task, the discrete PLL signal is approxi-mated to a continuous signal by applying linear interpola-tion technique.

2) Since low-order harmonics can be eliminated by

n number of optimum angles in Fig. 6, ac-cording to SHEM, these angles are calculated off-line byusing a hybrid algorithm as a function of M and then storedin the memory of the FPGA in an LUT ( matrix or

204 1 vectors). A part of the LUT for the sample ap-plication is given in Table III. The FPGA board extractsoptimum angles from the LUT one time for each 40- s pe-riod by using the modulation index sent by the associatedslave DSP and implement them by using the shifted PLLsignal.

3) The dc link capacitor voltages should be equalized byusing selective swapping method during the operation ofthe CMC. This will be achieved by the FPGA board by

using current direction signal (1/0) sent by the associ-ated slave DSP board, and the individual instantaneous

TABLE IIISWITCHING ANGLES GENERATED BY THE HYBRID ALGORITHM FOR

SOME MODULATION INDEX VALUES

dc link capacitor voltages as shown inFig. 12(a). For this purpose, the FPGA board also de-termines the voltage level from to in Fig. 6 byusing a shifted PLL signal whenever a selective swapping

is needed. The dc link capacitor voltages are measured,converted to digital signals and then sent to the FPGAboard via SCI communication link by the DC_VM Boardsin Fig. 8.

4) Upon the request of the master DSP board via the slaveDSP, the FPGA board creates the necessary turn-on andturn-off signals for IGBTs to charge the dc link capaci-tors successfully both in the first and the second phases ofthe pre-charging period. FPGA also monitors dc link ca-pacitor voltages and informs the slave DSP and hence themaster DSP about the termination of both phases of thepre-charging period.

5) Upon the request of the PLC via master and slave DSP

boards, FPGA sends a command to DC_PD Boards inFig. 8 to discharge dc link capacitors in a controlledmanner. FPGA also informs the PLC via slave and masterDSP boards of the completeness of the discharge process.Each DC_PD board is composed of power stage of achopper circuit supplying controlled power to an externaldischarge resistor and an analog protection circuit. DC_PDboard receives controlled duty ratio signals from FPGAin order to keep the power dissipation of the dischargeresistor constant during the discharge period.

6) FPGA board also carries out some protection functionssuch as short circuit of IGBTs, over temperature, over

voltage protections, and so on, as will be described laterin this section.7) Validity check of fiber-optic links connected to

DC_VM/DC_PD Boards, and IGBT gate drivers inFig. 8 is achieved by the associated FPGA board. TheFPGA board also checks the validity of the fiber-opticlinks to the associated slave DSP board.

F. Programmable Logic Controller

The Programmable Logic Controller (PLC) in Fig. 8 achievescontrol actions according to the signals received from MasterDSP Board and external subsystems via digital/analog I/Os anddata acquisition and state monitoring actions received from the

same system elements via serial communication channels. Themajor operational features of the PLC are as described below:

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Fig. 13. Sample screen from the HMI software which shows the single-line diagram of the sample FACTS device.

1) The PLC carries out data acquisition, state monitoring andfault diagnosis actions according to the signals taken fromthe Master DSP Board and external subsystems.

2) The operation state of the FACTS device (on/off opera-tion of circuit-breakers and the load-break switch) is com-manded by the PLC according not only to the protectionsignals received from the de-ionized water cooling systembut also to on/off or protective signals received from othersystem elements.

3) The PLC carries out closed-loop, stepwise control of in-

terior temperature of CMCs container by sending on/offsignals to air ventilation fans.

4) Remote control signals are actuated by the PLC.5) Some of the fault/failure signals are received from other

control system elements and then classified by the PLC forthe activation of automatic re-closing system. The de-ion-ized water cooling system is therefore turned on by thePLC before re-closing action of the main CB to providecooling service for power semiconductors. The classifiedand unclassified fault/failure data are also sent to the in-dustrial computer in Fig. 8 for monitoring purpose.

G. Remote Control and Monitoring

The remote control and monitoring system is composedof an industrial computer, ADSL/GPRS/3G modem, digital

power meters, and wireless access points if necessary. Theindustrial computer is used not only for local but also for re-mote visual monitoring purpose. Two different custom-designapplications are running on the industrial computer and areutilizing a common database. These are bi-directional com-munication software and Human Machine Interface (HMI)software.

The communication software collects the data receivedfrom the control system and external subsystem at a rateof one second and logs in the database. Whenever the HMI

software changes some values of a table in the database, theupdated data are sent to the required control system element/sor external subsystem/s by the communication software.

The HMI software visualizes the data arrays on an LCDscreen upon the request of the system operator. Nine mainscreens, five subscreens for each CMC and seven subscreensfor the alarms are found to be quite satisfactory for local/re-mote monitoring of all parts of the sample FACTS device. Asample screen is shown in Fig. 13.

The system operator can create on/off signals and changethe settings of the control system via the HMI software. Thecommunication between the FACTS device and the remote

control and monitoring computer can be achieved through aVirtual Private Network (VPN) for secure remote connection.

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TABLE IVPROTECTION TYPES AND ACTIONS

TABLE VCROSSCHECK MECHANISMS

H. Protection Functions

The overall system (FACTS device) and individual CMCsshould be equipped with their own protection facilities. Theprotection functions are implemented in a redundant mannerby employing both conventional relaying and custom designedfacilities. It is clear that custom-designed protection facilitiespre-programmed on DSPs, FPGAs, and PLC respond againstfaults and failures more rapidly than conventional protection re-lays. Some faults or failures are detected directly or indirectly bymore than one digital controller and the controller responds toclear the fault according to the first observe first act principle.

Types of faults, protection circuits, and their action are givenin Table IV for different variables such as ac and dc currents and

voltages, frequency, and temperature. In general, protection ofthe overall system components are held by conventional relayswhile external subsystems and their components by the PLC.The most critical protection functions for CMCs and HBs whichneed rapid response are carried out by DSPs and FPGAs.

The status (alive or dead) of DSPs, FPGAs, DC_VM boards,PLC, and communication links are detected by the neighboringdigital controllers periodically during the operation of theFACTS device. These crosscheck mechanisms for redundantcontrol and protection are as summarized in Table V. Theprotection action that will be held by one of the live digitalcontrollers whenever it detects a dead neighboring device or

loss of communication link is also marked in the last column ofTable V. Since each DSP board contains two DSP chips, one

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Fig. 14. Line-to-neutral voltage and current waveforms (Field data). a) At PCC (154 kV line-to-line). (b) At 10.5-kV line-to-line on the coupling transformer sideof the filtering reactor. (c) At 10.5-kV line-to-line on the CMC side of the filtering reactor using MSS method with 400 s.

for control and one for protection, they are marked by masterDSP/C, master DSP/P, slave DSP/C, and slave DSP/P inTable V.

IV. FIELD PERFORMANCE OF SAMPLE FACTS APPLICATION

The performance of the fully digital control system describedin Section III is tested in the field on a sample T-STATCOMsystem . The general view of 10.5-kV CMC-based154-kV, 50-MVAr T-STATCOM system is shown in [16, Fig.2d]. It is connected to a 154-kV PCC via 50/62.5-MVA, 10.5/154-kV step-up coupling transformer. The voltage and currentwaveforms at the PCC and ac side of the CMCs are given inFig. 14, while the T-STATCOM is generating 50 MVAr at thePCC (nearly 40 MVAr 60 MVAr on the converter side).These waveforms have shown the success of digital implemen-tation of the control system as well as the and control,waveform synthesizing, SHEM, selective swapping, and PLL

techniques employed in the design and implementation of theoverall system.

Fig. 14(c) shows line-to-neutral voltage waveforms createdby one of the CMCs for rated in both the inductive and capac-itive operation modes. Line-current waveforms of each CMCwould be as given in Fig. 14(b). Spikes superimposed on stair-

case voltage waveforms arise in the form of either an overshootor undershoot at swapping instants. Their magnitudes may be, , or as explained in [16]. These voltage wave-

forms show the success of digital implementation of waveformsynthesizing and MSS methods employed in the sample FACTSapplication. A comparison of line-to-neutral voltage waveformsin Fig. 14 shows that voltage harmonics present in the ac volt-ages of CMCs are successfully filtered out primarily by the se-ries filter reactors and secondarily by the leakage reactance ofthe coupling transformer.

A good current sharing has been obtained between paralleloperated CMCs primarily by the digital control system and sec-ondarily by the series filter reactors. This is because, the dig-

ital control system sends nearly the same modulation index ( )values to CMCs and satisfactorily keeps all of the dc link ca-

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TABLE VICURRENT AND MVAR SHARING AMONG ACTIVE CMCS (CMC CURRENTS AND REACTIVE POWERS ARE MEASURED ON

THE 10.5-kV SIDE AND TOTAL QUANTITIES ARE MEASURED ON 154-kV SIDE OF THE COUPLING TRANSFORMER)

Fig. 15. Variations in mean dc link voltages of a CMC (field data).

Fig. 16. The 10.5-kV side field data for transition from (a) full inductive to full capacitive and (b) full capacitive to full inductive. The 154-kV side field data fortransition from (c) full inductive to full capacitive and (d) full capacitive to full inductive (Field data).

pacitor mean voltages at required values with minimum devi-ations by successful implementation of load-angle controland MSS method. can be varied in discrete steps of 0.01. Ifthe control system calculates an value less than or larger thanthe step size, such as 3.524, some of the CMCs receive

while the others receive in order to minimize the

steady-state error in total produced by the T-STATCOM. Fur-thermore, the same series filter reactor 2.5 mH

hasbeen used for allCMCs. Reactive powerand true rms currentsharings among five parallel-operated CMCs are as shown inFig. 13. The test is repeated for four, three, and two parallel-op-erated CMCs and sample results for nearly the maximum capac-itive output power for each CMC (which is the worst case) areas given in Table VI.

The variations in dc link capacitor voltages in onephase of any CMC are recorded. A typical record (120- s sam-

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pled data) averaged over 20 ms is as shown in Fig. 15(a). Themean voltage variations of the dc link capacitors only in the firstH-bridges in phase-A, -B, and -C of the same CMC are alsorecorded as shown in Fig. 15(b). These results show that the dig-ital implementation of active power (P) controller and the MSSmethod yield perfect equalization of dc link capacitor voltages.

In order to test the performance of the T-STATCOM in tran-sient state, of the T-STATCOM is suddenly changed to givea variation in reactive power from 50 to 50 MVAr and thenfrom 50 to 50 MVAr at PCC.

The reactive power variations in Fig. 16 (20-ms averageddata) show the response of T-STATCOM against step changes in

. Reactive power settles to its set value in 80100-ms timeperiod without making an overshoot or undershoot, resulting inan over-damped system.

The performance of the digitally implemented controllerand the associated PI settings are found to be satisfactory intransmission system applications for reactive power compensa-tion or terminal voltage regulation modes. On the other hand,

much faster response could be obtained in the transient-stateby adjustment of the PI parameters so as to obtain a criticallydamped system response. The drawback of this approach wouldbe the requirement of power semiconductors with higher cur-rent and voltage ratings in order to keep the operating point inthe safe operating area of the chosen power semiconductors inthe transient state.

V. CONCLUSION

This research work deals with the design and implementationof a multi-DSP and -FPGA-based fully digital control systemfor CMCs used in FACTS applications.

The proposed system is composed of a DSP-based mastercontroller in combination with a multiple number of slave DSPboards, FPGA boards, controllers, a PLC, an industrial com-puter, and their peripherals in interaction. Since the proposedcontrol system is a general one, the design principles are ap-plicable to parallel-operated CMCs, each of which havingseries HBs.

The proposed controller topology provides improved reli-ability, redundancy, modularity, ease in implementation, andEMI immunity. By separating tasks between several DSPs andFPGAs, time is saved in the development of the necessary soft-ware. The digital control system also protects the most criticalelements of the FACTS device according to the principle of

first observe first act.The performance of the implemented system has been veri-

fied by extensive field tests conducted in the transmission sub-station where T-STATCOM has been installed. Field test re-sults have shown that the proposed fully digital control systemprovides good transient response and steady-state characteris-tics for the overall system, including protection and monitoringfunctions.

In this work, digital implementation of the PLL assumesnearly constant grid frequency and the over/under frequencyprotection feature acts whenever the frequency exceeds the50 Hz 0.5 Hz range. For interconnected systems havingrecurrent frequency oscillations, it is recommended to develop

and implement an adaptive PLL algorithm in order to avoid anypossible disconnection of the FACTS device from the grid.

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Electron., 2009, pp. 36603665.[8] L. Zhang,Z. Yang, S. Chen, andM. L. Crow, A PC-DSP-based unified

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[12] E. J. Bueno, A. Hernandez, F. J. Rodriguez, C. Giron, R. Mateos,and S. Cobreces, A DSP- and FPGA-based industrial control withhigh-speed communication interfaces for grid converters applied todistributed power generation systems, IEEE Trans. Ind. Electron.,vol. 56, no. 3, pp. 654669, Mar. 2009.

[13] C. Han, Z. Yang, B. Chen, W. Song, A. Q. Huang, A.-A. Edris, M.Ingram, and S. Atcitty, System integration and demonstration of a 4.5MVA STATCOMbased on emitter turn-off (ETO)thyristorand cascademultilevel converter, in Proc. 31st Annu. IEEE Conf. Ind. Electron.Soc., 2005, pp. 16.

[14] R. Godboleand S. Bhattacharya,Designand development of a flexiblemulti-purpose controller hardware system for power electronics andother industrial applications, in Proc. IEEE Ind. Applic. Soc. Annu.

Meeting, 2008, pp. 16.[15] V. Dinavahi, R. Iravani, and R. Bonert, Design of a real-time digital

simulator for a D-STATCOM system, IEEE Trans. Ind. Electron., vol.51, no. 5, pp. 10011008, Oct. 2004.

[16] B. Gltekin, C. . Gerek, T. Atalik, M. Deniz, N. Bier, M. Ermis, N.Kse, C. Ermis, E. Ko, I. adirci, A. Aik, Y. Akkaya, H. Toygar, andS. Bideci, Design and implementation of a 154 kV, 50 MVAr trans-mission STATCOM based on 21-level cascaded multilevel converter,

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[17] J.-S. Lai and F. Z. Peng, Multilevel converters-A new breed of powerconverters, IEEE Trans. Ind. Applicat., vol. 32, no. 3, pp. 509517,May/Jun. 1996.

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[23] S. Sirisukprasert, J.-S. Lai, and A. Q. Huang, Modeling, analysis andcontrol of cascaded multilevel converter based STATCOM, in IEEEPower Eng. Soc. General Meeting Conf. Rec., vol. 4, pp. 25612568.

[24] S. Sirisukprasert, Modeling and control of a cascaded-multilevel con-verter-based STATCOM, Ph.D. dissertation, Dept. Elect. and Comp.Eng., Virginia Tech. Univ., Blacksburg, VA, Feb. 2004.

[25] K. V. Patil, R. M. Mathur, J. Jiang, and S. H. Hosseini, Distributionsystem compensation using a new binary multilevel voltage source in-verter, IEEE Trans. Power Del., vol. 14, no. 2, pp. 459464, .

[26] L. M. Tolbert, F. Z. Peng, andT. G. Habetler,Multilevelconvertersforlarge electric drives, IEEE Trans. Ind. App., vol. 35, no. 1, pp. 3644,Jan./Feb. 1999.

[27] J. D. Ainsworth, M. Davies, P. J. Fitz, K. E. Owen, and D. E. Trainer,Static VAr compensator (STATCOM) based on single-phasechain cir-cuit converters, Proc. Inst. Electr. Eng.Gen. Transm. Distrib., vol.145, no. 4, Jul. 1998.

[28] D. J. Hanson, C. Horwill, B. D. Gemmel, and D. R. Monkhouse, ASTATCOM based relocatable SVC project in the UK for nationalgrid, in IEEE Power Eng. Soc. Winter Meeting Conf. Rec. , vol. 1, pp.532537.

[29] J. A. Barrena, L. Marroyo, M. A. R. Vidal, and J. R. T. Apraiz, In-dividual voltage balancing strategy for PWM cascaded H-bridge con-verter based STATCOM, IEEE Trans. Ind. Electron., vol. 55, no. 1,pp. 2129, Jan. 2008.

Tevhid Atalik (S10) received the B.Sc. degree inelectronics engineering from Uludag University,Bursa, Turkey, in 2003, and the M.Sc. degree in elec-trical and electronics engineering from HacettepeUniversity, Ankara, in 2007. He is currently workingtoward the Ph.D. degree in electrical engineering atBaskent University, Ankara.

He is a Senior Researcher with the Power Elec-tronics Department, Space Technologies ResearchInstitute, Scientific and Technological ResearchCouncil of Turkey (TUBITAK), Ankara, Turkey. His

areas of research include analog and digital control circuit design, instrumen-tation and power quality.

Mr. Atalik received the Outstanding Paper Award from the Metal IndustryCommittee of the IEEE Industry Applications Society in 2009.

Mustafa Deniz (S10) received the B.Sc. and M.Sc.degrees in electrical and electronics engineeringfrom the Middle East Technical University, Ankara,Turkey, in 2006 and 2009, respectively, where heis currently working toward the Ph.D. degree onthe design and implementation of grid-connectedphotovoltaic systems.

He is a Senior Researcher with the Power Elec-tronics Department, Space Technologies ResearchInstitute, Scientific and Technical Research Councilof Turkey (TUBITAK), Ankara, Turkey. His current

areas of research include digital control of power converters, photovoltaicinverters, and motor drives.

Erkan Ko received the B.Sc. and M.Sc. degreesin electrical and electronics engineering from theMiddle East Technical University, Ankara, Turkey,in 2005 and 2010, respectively.

He was with ELIMKO, Ankara, Turkey, as aSystem Engineer between 2005 and 2006. He iscurrently a Senior Researcher with the Power Elec-tronics Department, Space Technologies ResearchInstitute, Scientific and Technological ResearchCouncil of Turkey (TUBITAK), Ankara, Turkey.His areas of research include renewable energy, and

supervisory control and data acquisition systems.

Cem zgur Gerek (S04) received the B.Sc. andM.Sc. degrees in electrical and electronics engi-neering from the Middle East Technical University(METU), Ankara, Turkey, respectively in 2004 and2007, where he is currently working toward thePh.D. degree on control issues of T-STATCOMsystems.

He was a Research Assistant with the Electrical

and Electronics Engineering Department, METU,between 2004 and 2006. He is currently a SeniorResearcher with the Power Electronics Department,

Space Technologies Research Institute, Scientific and Technological ResearchCouncil of Turkey (TUBITAK), Ankara, Turkey. His areas of research includeFACTS devices, reactive power compensation systems, and power qualityissues.

Burhan Gultekin (S03) received the B.Sc. andM.Sc. degrees in electrical and electronics engi-neering from the Middle East Technical University,Ankara, Turkey, respectively in 2000 and 2003,where he is currently working towards the Ph.D.degree.

He is with the Power Electronics Department,Space Technologies Research Institute, Scientificand Technological Research Council of Turkey(TUBITAK), as a Chief Senior Researcher andcurrently as the Head of the Power Electronics

Department. His areas of research are reactive power compensation systems,system design and. protection, and power quality issues.

Mr. Gultekin received the Outstanding Paper Award from the Metal In-dustry Committee of the IEEE Industry Applications Society in 2009.

Muammer Ermis (M99) received the B.Sc., M.Sc.,and Ph.D. degrees in electrical engineering from theMiddle East Technical University (METU), Ankara,Turkey, in 1972, 1976, and 1982, respectively, andthe M.B.A. degree in production management from

Ankara Academy of Commercial and Economic Sci-ences, Ankara, Turkey, in 1974.

He is currently a Professor of electrical engi-neering with METU. His current research interest iselectric power quality.

Dr. Ermis received the The Overseas Premiumpaper award from the Institution of Electrical Engineers, U.K., in 1992, andthe 2000 Committee Prize Paper Award from the Power Systems EngineeringCommittee of the IEEE Industry Applications Society. He wasalso therecipientof the 2003 IEEE PES Chapter Outstanding Engineer Award. He received theOutstanding Paper Award from the Metal Industry Committee of the IEEEIndustry Applications Society in 2009.

Isik adirci (M98) received the B.Sc., M.Sc.,

and Ph.D. degrees in electrical and electronicsengineering from the Middle East Technical Uni-versity, Ankara, Turkey, in 1987, 1988, and 1994,respectively.

She is currently a Professor of electrical engi-neering with Hacettepe University, Ankara, Turkey.Her areas of interest include power quality, electricmotor drives, and switch-mode power supplies.

Dr. adirci was a recipient of the Committee PrizePaper Award from the Power Systems Engineering

Committee of the IEEE Industry Applications Society in 2000, the IEEE In-dustry Applications Magazine Prize Paper Award, Third Prize, in 2007, and theOutstanding Paper Award from the Metals Industry Committee of the IEEE In-dustry Applications Society in 2009.

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