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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 2, FEBRUARY 2014 569

Dual Three-Phase Indirect Matrix Converter With

Carrier-Based PWM MethodTuyen D. Nguyen, Member, IEEE, and Hong-Hee Lee, Senior Member, IEEE

AbstractThis paper proposes an indirect matrix converter(IMC) topology with dual three-phase outputs and its effectivecarrier-based pulse width modulation (PWM) method. The pro-posed IMC topology can independently supply ac power for twothree-phase loads from a single three-phase ac power source. Thisconverterconsistsof a rectifier stage used in traditional three-phaseIMC and a five-leg inverter. Besides a proposed IMC topology, thecarrier-based PWM method suitable for this converter is also in-troduced. The proposed PWM method is easily implemented byusing only one symmetrical triangular carrier signal to generatethe PWM signals for a rectifier and five-leg inverter. ProposedIMC topology features the advantages of conventional three-phaseIMC, such as sinusoidal input/output current waveforms, control-

lable input power factor, and simple commutation at the rectifierstage. Analysis, simulation, and experimental results are providedto demonstrate the advantages of the proposed IMC topology withdual three-phase outputs and to validate the effectiveness of theapplied modulation strategy.

Index TermsCarrier-based pulse width modulation (PWM),direct matrix converter (DMC), dual inverters, five-leg inverter,indirect matrix converter (IMC), space vector PWM (SVPWM).

I. INTRODUCTION

T

HE three-phase to three-phase ac/ac matrix converters

(MCs) are originally presented in [1]. MCs allow direct

ac/ac power conversion without the dc energy storage compo-

nent. They haverecently received considerableattention as an al-

ternative to the conventional ac/ac converter, which is composed

of rectifier/dc-link capacitor/inverter structures. MCs have many

advantages such as sinusoidal input and output current wave-

forms, unity power factor at the input side, increased power

density, and inherent four-quadrant operation. In addition, MCs

are highly reliable and durable due to the lack of a dc-link

electrolytic capacitor for energy storage [2].

MCs are classified into two types: direct matrix convert-

ers (DMC) and indirect matrix converters (IMC). The DMC

is a one stage ac/ac direct converter, where three-phase input

Manuscript received September 6, 2012; revised November 26, 2012, January15, 2013, and February 7, 2013; accepted March 12, 2013. Date of currentversion August 20, 2013. This work was supported by the National ResearchFoundation of Korea (NRF) grant funded by the Korea government (MEST)under Grant 2010-0025483. Recommended for publication by Associate EditorJ. R. Rodriguez.

T. D. Nguyen is with the Faculty of Electrical and Electronics Engineering,Ho Chi Minh City University of Technology, Ho Chi Minh City, Vietnam(e-mail: [email protected]).

H.-H. Lee is with the School of Electrical Engineering, University of Ulsan,Ulsan 680-749, Korea (e-mail: [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2013.2255067

Fig. 1. DMC topology.

Fig. 2. IMC topology.

voltages are directly connected to three-phase output loads

through nine bidirectional switches as shown in Fig. 1 [3], [4].

On the other hand, the IMC topology is based on the ac/dc/ac

power conversion with no intermediate capacitor. The IMC com-

prises two stages such as rectifier stage and inverter stage, which

are illustrated in Fig. 2 [5][13]. DMC and IMC provide the

same input/output performance, maximum voltage transfer ra-

tio, and number of power switches. However, the IMC topology

provides a soft switching commutation that is not applicable inDMC. Furthermore, the IMC needs the simpler clamp circuit

for overvoltage protection as compared to the DMC.

IMC topology has recently been widely discussed and many

researchers have developed the various IMC topologies suitable

for specific applications. Kolar et al. [14][16] concentrated

to modify the rectifier stage structure with the reduced power

devices by utilizing the zero current commutation. In part of

the inverter stage, some novel IMC topologies have recently

been proposed such as the hybrid IMC [17], [18] and Z-sourceIMC [19], [20] to increase the output voltage transfer ratio, the

four-leg IMC for unbalanced loads [21], and the multilevel IMC

to improve the output voltage quality [22], [23].

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570 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 29, NO. 2, FEBRUARY 2014

Fig. 3. Dual three-phaseoutputIMC topology based on theparallelconnectionof two three-leg inverters.

Fig. 4. Dual three-phase output IMC topology based on the nine-switchinverter.

On the other hand, the IMC with dual three-phase outputs

is also introduced in order to reduce the total cost and sys-

tem volume [24], [25]. Dual ac-drive systems from conven-

tional voltage source inverter (VSI) have been studied for spe-

cial industrial applications such as electric vehicles, railway

traction system, steel processing, textile manufacturing, and

winders [26][33]. However, they have the same drawbacks as-

sociated with the rectifier/dc-link capacitor/inverter conversionsystem. Dual three-phase outputs IMC topology consists of an

input stage and two output stages with a pair of conventional

three-leg inverters, as shown in Fig. 3. The drawback of this

topology is the large number of power switches in the inverter

stage, 12 power switches are used in the inverter stage. Another

approach to the IMC topology is proposed in [34] for indepen-

dent control of two three-phase loads with fewer reduced power

switches. This topology is based on the traditional IMC, but the

inverter stage is replaced by a nine-switch inverter as shown in

Fig. 4. Even if this topology works with reduced numbers of

power switches, the switch capacity in the nine-switch inverter

stage is doubled.

Fig. 5. Proposed dual three-phase output IMC topology.

In order to overcome the disadvantages in the previous IMC

topologies as shown in Figs. 3 and 4, this paper proposes the

IMC topology composed from a five-leg inverter connected to

a rectifier stage to generate dual three-phase outputs effectivelyby using a common leg supplying both of two loads, which

is shown in Fig. 5. As shown in Fig. 5, two phases of each

load are supplied independently from four legs of the inverter

stage while each remaining phase for the two loads is connected

to the same leg. The proposed IMC topology can reduce two

power switches, in comparison to the conventional IMC topol-

ogy shown in Fig. 3, and can halve the switch capacity compared

to the IMC topology with nine-switch inverter stage shown in

Fig. 4 except the switches in leg C due to the common current

path for both the currents of load 1 and load 2. Moreover, the

number of power switch in the proposed topology can be re-

duced by three in the case of unidirectional power flow from thepower supply to the loads.

Besides interest in the IMC topology for particular applica-

tions, modulation methods to effectively drive IMC have also

been investigated in recent technical publications. The space

vector PWM (SVPWM) method has been generally used to

control IMC because it has a good performance such as a lower

current harmonic and higher modulation index [5][10]. How-

ever, this method needs many calculations and lookup tables

to generate the switching pattern. On one hand, the carrier-

based PWM method has been presented for three to three phase

IMC [35], [36]. However, the carrier signal used for the rectifier

stage is different from that of the inverter stage. The carrier sig-

nal used for the rectifier stage is a symmetrical triangular signalwith constant frequency, while the carrier signal with different

slope in the rising and falling edge is used for the inverter stage.

Furthermore, these slopes of the carrier signal are changed in

every sampling period due to the variation of the dc-link voltage.

In this paper, in order to overcome the limitation of the SVPWM

and the conventional carrier-based PWM method, we introduce

the carrier-based PWM method for the proposed IMC topology,

which uses only one symmetrical triangular carrier signal with

constant frequency and magnitude to generate PWM signals

for all switches of both the rectifier and five-leg inverter stage.

The proposed carrier-based PWM method can be implemented

easily by using only one up/down counter, which is available

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NGUYEN AND LEE: DUAL THREE-PHASE INDIRECT MATRIX CONVERTER WITH CARRIER-BASED PWM METHOD 571

in most of digital signal processors. The proposed modulation

method is established based on space vector analysis.

This paper is organized as follows: the operational principles

and the SVPWM for the proposed IMC topology are introduced

in Section II. Section III describes the proposed carrier-based

PWM method, which is based on the space vector analysis in

Section II. Simulations studies and experiments on two three-

phase inductive loads are implemented and provided in Sections

IV and V, respectively, to demonstrate that two three-phase loads

are fed independently from single three-phase power supply.

Finally, Section VI offers some conclusions.

II. OPERATIONALPRINCIPLES OF THEPROPOSED IMC

TOPOLOGYWITHDUALTHREE-PHASEOUTPUTS

In order to explain the operational principles of the proposed

IMC topology, we use the space vector theory, which is a well-

known technique commonly adopted in the previous technical

literatures. As shown in Fig. 5, the proposed topology comprises

a rectifier stage connected to a five-leg inverter stage. The tar-

get of the rectifier stages is to generate the maximum dc output

voltage at the dc-link bus as well as to produce the sinusoidal

input current waveforms. The desired output voltages with vari-

able frequency for two loads can be obtained by controlling the

five-leg inverter stage. The rectifier stage is controlled based on

the reference input current vector, and the five-leg inverter stage

is controlled based on two reference output voltage vectors of

two loads. The two stages are controlled separately and both

switching patterns of the two stages are synthesized together.

A. Rectifier Stage Control

The rectifier stage is connected to a three-phase power supplywith constant amplitude and frequency. It is assumed that three-

phase input voltages are balanced as follows:

va =Vicos (it)

vb =Vicos (it 2/3)vc =Vicos (it+2/3) (1)

whereVi and i are the amplitude and angular frequency of theinput phase voltage, respectively.

We can describe the input current vector and input voltage

vector as follows:

ii =23ia +ibej2/3 +icej4/3

= Iiej i (2)

vi =2

3

va + vbe

j2/3 +vcej4/3

= Vie

ji (3)

where i and i are current and voltage phase angles,respectively.

Fig. 6 shows the space vector diagram of the rectifier stage.

Each active current vector represents the switching condition

between the input phase voltage and the dc-link bus. For exam-

ple, the current vector Iab represents the input phase a andb are connected to the positive pole and the negative pole ofdc-link bus, respectively. The zero vector means that the input

voltage is not applied to dc-link bus. Assume that the reference

Fig. 6. Space vector diagram and the generation of reference input currentvector in the rectifier stage.

input current vector is located in sector1(/6 i /6)and lags behind the input voltage vector with the angle . Theduty cycle of the active vectors for the rectifier stage Iab and Iacare determined as follows:

d =misin (/6 (i )) (4)d =misin (i +/6) (5)

wheremi is the rectifier stage modulation index.Because the zero vectors are not used to synthesis the refer-

ence input current vector, the duty ratio d and dfor two active

vectorsIab andIac are recalculated as follows:

dx = dd+d

=cos(i 2/3 )

cos(i ) (6)

dy = dd+d

=cos(i 4/3 )

cos(i ) . (7)

The dc-link voltage has two values,vba with the duty cycledx , andvca with the duty cycle dy . Thus, the average value ofthe dc-link voltage in one sampling period is

Vdc =dx(va vb) +dy (va vc) =3

2

Vicos(i )

cos .

(8)

From (8), the minimum value of theVdc is

Vdc(min)=3

2Vicos . (9)

Depending on the position of the reference input current vec-

tor, suitable active vectors are chosen to generate the dc-link

voltage. By similar analysis, Table I summarizes the switching

state of all power switches, the corresponding dc-link voltage

and its average value according to the input current sector. In the

odd sector, the upper switch of the positive input phase voltage

is in the ON state at any time, and two lower switches of two

negative input phase voltages are modulated. In the other case

(i.e., in the even sector), the lower switch of the negative input

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TABLE IMODULATEDSWITCHES ANDDC-LINKVOLTAGEACCORDING TO THE INPUTCURRENTSECTOR

Fig. 7. Generation of reference output voltage for (a) Load 1. (b) Load 2.

phase voltage is in the ON state, and two upper switches of two

positive input phase voltages are modulated.

B. Five-Leg Inverter Stage Control

The SVPWM techniques have been widely used in inverter

control due to the lower current harmonic and higher modulation

index. The purpose of the SVPWM technique is to generate the

reference output voltage vector by conjoining the switching

states corresponding to the active and zero vectors. Fig. 7(a)

and (b) illustrates the active vectors, the zero vectors, and the

position of the reference output voltage vector in the case of

load 1 and load 2, respectively. The eight space vectors are used

in the SVPWM technique, whereV1V6 are active vectors, andV0 and V7 are zero vectors. Each vector is denoted by the setof switching functions: [SA SB SC] in the case of load 1, and

[SE SD SC] in the case of load 2. The switching function of the

upper switch in each leg is defined as

SX =

1 ifSX is ON state0 ifSX is OFF state

X = A E. (10)

It is assumed that the reference output phase voltages of the

load 1 are

vA1 =Vo1 cos (o1 t+o1 )

vB 1 =Vo1 cos (o1t+o1 2/3)

vC1 =Vo1 cos (o1t+o1 + 2/3) (11)

and the reference output phase voltages of the load 2 are

vA2 =Vo2 cos (o2t+o2 )

vB 2 =Vo2cos (o2t+o2 2/3)vC2 =Vo2cos (o2t+o2 + 2/3) (12)

where Vo1 , o1 , and o1 are the amplitude, angular fre-quency, and initial phase of the output phase voltage of load 1,

respectively.

Vo2 ,o2 ,and o2 are the amplitude, angular frequency, andinitial phase of the output phase voltage of load 2, respectively.

We can describe the reference output voltage vectors of two

loads as follows:

vo1 = 2

3

vA1 + vB1 e

j2/3 +vC1 ej4/3

= Vo1e

jo1 (13)

vo2 = 2

3

vA2 + vB2 e

j2/3 +vC2 ej4/3

= Vo2e

jo2 (14)

where o 1and o2 are the angles between each reference outputvoltage vector and the basic active vector V1 as shown in Fig. 7.

Without loss of generality, the reference output voltage vec-

tors of load 1 and load 2 are assumed to be located in sector

1 (0o1/3) and sector 2 (/3o22/3), respectively.From Fig. 7(a) and (b), the reference output voltage vector of

the two loads can be synthesized as follows:

vo1 =T1(1) V1 + T2(1) V2 (15)

vo2 =T2(2) V2 + T3(2) V3 . (16)

Therefore, the application time of active vectors and zero

vectors of load 1 are written as

T1(1)=

3Vo1Vdc

Tssin (/3 o1 ) (17)

T2(1)=

3Vo1Vdc

Tssin (o1 ) (18)

T7(1)=T0(1) =

1

2Ts T1(1) T2(1) (19)

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Fig. 8. Switching pattern of load 1 when the reference output voltage vectoris in sector 1.

Fig. 9. Switching pattern of load 2 when the reference output voltage vectoris in sector 2.

and those of load 2 are written as

T2(2) =

3Vo2Vdc

Tssin(2/3 o2 ) (20)

T3(2) =

3Vo2VD C

Tssin (o2 /3) (21)

T7(2) =T0(2) = 1

2Ts T2(2) T3(2) . (22)

The symmetric arrangement of two active vectors and two

zero vectors of load 1 and load 2 are shown in Figs. 8 and 9,

respectively. Also, the sequence and the application time of all

upper switches are shown individually for each output load.

Two loads share the common legC.Therefore, the two upper

switches of phasesC1 andC2 have the same application time.Hence, the application time for zero vectorsV0 andV7 of twoloads should be changed, while the application time for active

vectors is unchanged to ensure that the magnitude of two ref-

erence output voltages are kept constant. The application time

of all upper switches of the five-leg inverter in one samplingperiod is determined as follows:

TA =T7(1)+ T2(1)+ T1(1)+ T7(2)Ts2

(23)

TB =T7(1)+ T2(1)+ T7(2)Ts2

(24)

TC =T7(1)+ T7(2)Ts2

(25)

TD =T7(2)+ T2(2)+ T7(1)+ T3(2)Ts2

(26)

TE =T7(2)+ T2(2)+ T7(1)Ts

2 . (27)

Fig. 10. Switching pattern for the five-leg inverter stage.

Fig. 10 shows the symmetric switching scheme of the five-leg

inverter stage when two phases of two loads are connected to

the same point at leg C. It can be seen that the distribution of

application time for active vectors of each load is unchanged.

The distribution of application time for zero vectors V0 andV7of each load is changed; however, the amount of application

time of zero vectors is kept constant.

C. Maximum Voltage Transfer Ratio

The application time of all switches in the five-leg inverter

stage has to be positive. Therefore, we can obtain (28) from

(17)(27)

Vo1 + Vo2Vdc

3. (28)

If we defineq1 andq2 as the voltage transfer ratio of load 1and load 2, respectively, then the voltage transfer ratios become

q1 = Vo1Vi

(29)

q2 =Vo2Vi

. (30)

From (9) and (28), there is the constraint of output voltages

for two loads such as

q1 + q2

3

2 cos . (31)

From (31), we can see the maximum voltage transfer ratio,

0.866, is obtained under the unity power factor constraint (= 0). However, the maximum voltage transfer ratio becomes

smaller by the factor cosfor nonunity input power factor.

D. Switching Patterns and the Safe Commutation

In one sampling period the dc-link voltage has two values,

which depend on the switching state of the rectifier stage. There-

fore, the five-leg inverter is fed by two positive line-to-line input

voltages. In order to obtain the balanced output voltages within

a sampling period, the switching pattern of the converter has to

mix the switching states of the rectifier stage and the five-leg

inverter stage.

Considering one half of sampling periodTs/2, the values ofthe dc-link voltage are twoline-to-line input voltagesvab and vac

with the durationTbn = dxTs /2 andTcn = dy Ts /2, respectively.

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Fig. 13. (a) Sequence and timing of effective switches in the rectifier stage.(b) Modulation signals and symmetrical carrier signals to generate PWMs forthe rectifier stage.

and Scn are

Tap = Ts2

; Tbn =dx Ts2

; Tcn =dy Ts2 . (37)

Fig. 13(b) shows two modulation signals vap and vbn , andthe triangular carrier signalvt . The gating pulses for the switchSap and Sbn are obtained from the intersection between themodulation signalsvap andvbn and the carrier signal. The gatepulse for switchScn is complementary to that of switchSbn .

As shown in Fig. 13(b), the symmetrical triangular carrier

signal can be described by

vt =

4

Tst 1

Vi, 0 t Ts2 (38)

where vt and Vi are the instantaneous and peak value of thecarrier signal, respectively.

Therefore, the modulation signals for the rectifier stage are

easily obtained from (37) and (38)

vap =Vi ; vbn = (2dx 1) Vi . (39)All remaining switches (San , Sbp , Scp )are OFF state. There-

fore, the modulation signals, which are used to generate gating

pulses for these switches, are determined as follows:

van = Vi ; vbp = Vi ; vcp = Vi . (40)

B. Carrier-Based PWM for Five-Leg InverterFig. 14(a) shows the sequence and the application time of all

upper switches in the five-leg inverter stage. In one half sam-

pling period, the switching period of each switch is divided into

two parts with unequal values. For example, the application time

of the upper switch of leg A(TA/2) is separated into two valuesTA(ab ) andTA (ac ) ,which are determined in (32). The durationtimeTA(ab ) has to be applied to the switchSA when the dc-linkvoltage is vab ; otherwise, the duration time TA (ac ) has to beapplied when the dc-link voltage is vac . Unlike in the case ofthe rectifier stage (where the switching frequency is equal to the

carrier signal frequency), the switching frequency in the five-

leg inverter stage is twice that of the carrier signal. Therefore,

Fig. 14. (a) Switching pattern of the five-leg inverter stage. (b) Waveforms oftwo modulation signals and carrier signal. (c) PWM waveforms for switchSA .

we cannot use one modulation signal that is compared with the

carrier signal to generate a gate signal in the inverter stage. In or-

der to elucidate the proposed carrier-based PWM in the inverter

stage, we consider how to generate the gate signal for the switch

SA . To create the gate signal for switch SA , two modulationsignals are needed. Fig. 14(b) shows two modulations signals

vA (upper) andvA (lower), and the carrier signal. The PWM0 andPWM1 are the results of comparing two modulation signals with

the carrier signal. As shown in Fig. 14(c), the switching pattern

of switchSA is obtained by

SA =PWM0 PWM1 +PWM0 PWM1. (41)

We then have to determine the instantaneous value of two

modulation signals. The time intervalsTA(upper) andTA (lower)in Fig. 14(b) are calculated as follows:

TA(upper) =Ts

2 TA(ac ) =

Ts2 1

2

T7(1) +T1(1) +T2(1) +T7(2)Ts

2 dy (42)

TA (lower)=TA(ab ) = 1

2

T7(1) +T1(1) +T2(1) +T7(2)

Ts2

dx . (43)

By substituting TA(upper) and TA(lower) from (42) and (43)into (38) for variablet, two modulation signals vA (upper) andvA (lower)are obtained as follows:

vA (upper) =Vi

2dy

vA1 + vC2 + voffset1+ voffset2Vdc

+dx

(44)

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vA(lower) =Vi

2dx


dy

(45)

where voffset1 and voffset2 are two offset voltages, which arewritten as

voffset1 = 0.5vA1 0.5vC1 (46)voffset1 = 0.5vB 2 0.5vC2 . (47)

Likewise, the couple of modulation signals, which are used

to generate PWM signals for the remaining upper switches SX(X=B E), are obtained as follows:vB (upper) =Vi

2dy

vB 1 + vC2 + voffset1+ voffset2Vdc

+dx

(48)

vB (lower)=Vi

2dx

vB1 + vC2 + voffset1+ voffset2Vdc

dy

(49)

vC(upper) =Vi

2dy

vC1 + vC2 + voffset1+ voffset2Vdc

+dx

(50)

vC(lower)=Vi

2dx

vC1 + vC2 + voffset1+ voffset2Vdc

dy

(51)

vD (upper) =Vi

2dy

vB 2 + vC1 + voffset1+ voffset2Vdc

+dx

(52)

vD (lower)=Vi

2dx

vB2 + vC1 + voffset1+ voffset2Vdc

dy

(53)

vE(upper) =Vi

2dy


+dx

(54)

vE(lower)=Vi

2dx


dy

.

(55)

Equations (44)(55) are established under the assumptionthat the reference output voltages of loads 1 and 2 are located

in sectors 1 and 2, respectively. However, these results are valid

for all the other sectors when two offset voltages are chosen as

voffset1= 0.5 (vmax 1 + vmin 1 ) (56)voffset2= 0.5 (vmax 2 + vmin 2 ) (57)

where

vmax 1 = max (vA1 , vB1 , vC1 ) ; vmin 1

= min (vA1 , vB1 , vC1 ) (58)

vmax 2 = max (vA2 , vB2 , vC2 ) ; vmin 2

= min (vA2 , vB2 , vC2 ) . (59)

Fig. 15. Couple modulation signalsvA ( u p p e r )an dvA (lower) to generate thegate signal for switch SA (a)f1 = f2 =50 Hz. (b)f1 =50 Hz,f2 =100 Hz.

Fig. 16. Block diagram of the proposed carrier-based PWM method.

Fig. 15 shows the waveforms of the normalized modulation

signalsvA (upper) andvA (lower) at the output frequencies:f1 =f2 = 50 Hz and f1 = 50 Hz, f2 = 100 Hz, where f1 andf2 are output frequencies of load 1 and load 2, respectively.In case of the conventional VSI, the modulation signals have

sinusoidal waveforms because they have the only information

about the reference output voltage. However, the modulation

signals in the inverter stage contain the information about both

input voltage and reference output voltage in (44) and (45), sothat they cannot be sinusoidal as shown in Fig. 15.

The principle of the proposed carrier-based PWM method

explained up to now is shown in Fig. 16, which shows how to

generate gating signals for six bidirectional switches in the rec-

tifier stage and ten unidirectional switches in the inverter stage.

All required functions are easily implemented without a lookup

table or complex calculations, and there is no need to coordinate

the switching state of the rectifier and five-leg inverter stages.

The performance of the proposed modulation is the same as that

of the SVPWM including the zero current commutation of the

rectifier stage because the proposed carrier-based PWM method

is derived based on the mathematical analysis with SVPWM.

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Fig. 17. Simulation waveforms of input voltage/current and output currentsunder in-phase CF mode.

Fig. 18. Simulation waveforms of input voltage/current and currents underCF mode with the phase shift 45.

IV. SIMULATIONRESULTS

The proposed IMC topology with dual three-phase outputs

shown in Fig. 5 has been simulated using Psim 9.0 software. Inthis simulation, the proposed IMC is evaluated using two three-

phaseRL loads. The simulation parameters are as follows:

1) three-phase power supply: the input line-to-line voltage is

200 V and the input frequency is 60 Hz;

2) LCinput filter:L= 1.4 mH,C= 27F;3) the carrier signal frequency is 10 kHz(Ts = 100s);4) threephaseRL load 1:R= 10,L=5 mH;5) threephaseRL load 2:R= 12,L=5 mH.The performance of the proposed dual three-phase output

IMC with the carrier based-PWM modulation method is eval-

uated for two cases to determine whether it has similar perfor-

mance as two independent three-phase IMCs: common output

terminal frequency (CF mode) and different output terminalfrequency (DF mode). For each case, the desired output fre-

quencies (f1 , f2 )and the voltage transfer ratios (q1 , q2 )are setas follows: in CF mode,f1 =50 Hz,q1 =0.3 for load 1, andthef2 =50 Hz,q2 =0.5 for load 2; in DF mode, f1 =50 Hz,q1 =0.3 for load 1, and the f2 =100 Hz,q2 =0.5 for load 2,and open-loop control is applied.

Figs. 17 and 18 show the simulation results in CF mode

obtained by adjusting the current phase between two output

loads. Fig. 17 shows input voltage(va )/current(ia)and outputcurrents of two loads in CF mode, when the output currents

of two loads,iA1 andiA2 are set in-phase. Both the input and

output current are sinusoidal waveforms. Due to the LC filter,

Fig. 19. Simulation waveforms of input voltage/current and output currentsunder DF mode.

Fig. 20. Simulated waveforms of input voltage/current and output currents atdifferent load step: The load condition 1 changes from q1 = 0.25,f1 = 50 Hztoq1 = 0.5,f1 = 100 Hz and the load condition 2 changes fromq2 = 0.5,f2= 100 Hz toq2 =0.25,f2 = 50 Hz.

there is a displacement angle between the input current and input

voltage.

In order to verify that the output phase can be controlled

independently by using the proposed IMC, only current phase

commands is changed in Fig. 18 under the same conditions as

shown in Fig. 17; the current of load 1 lags behind that of load

2 by 45, while the output frequencies remain the same. Allwaveforms are the same as those shown in Fig. 17 except for

the output current phase difference, and the proposed IMC is

shown to control two output phases independently.

Fig. 19 shows the simulated waveforms of the input volt-

age/current and two output currents of two loads in DF mode.

Similar to the CF mode, the input/output currents have goodsinusoidal waveforms with the desired frequencies.

Fig. 20 shows the input voltage/current and two output cur-

rents of two loads in DFmodewhenthe load condition 1 changes

from q1= 0.25, f1= 50Hzto q1= 0.5, f1= 100 Hzand the loadcondition 2 changes fromq2 =0.5,f2 =100 Hz toq2 =0.25,f2 = 50 Hz. We can see the proposed converter maintains thesinusoidal input/output currents and good dynamic performance

even though the load condition changes suddenly.

Fig. 21 shows the transient responses of the input current and

output voltages with the closed-loop V/fcontrol. The outputvoltage reference of load 1 steps up from 20 to 30 V and the

frequency also steps up from 20 to 30 Hz. In case of the load

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Fig. 21. Simulated waveforms of input currents, output voltages of load 1 andload 2 with closed-loopV/fcontrol.

Fig. 22. THD of the input current and output voltages.

Fig. 23. Input power factor according to the voltage transfer ratioq1 andq2 .

2, the output voltage reference steps up from 30 to 60 V and

the frequency steps up from 30 to 60 Hz. It can be found that

the balanced and sinusoidal input currents and output voltages

are obtained, and the dynamic response of the output voltages

is very good.

The total harmonic distortion (THD) of the input current and

output voltages according to the output frequency variation are

shown in Fig. 22, whereq1 =0.3 andq2 =0.5; THD of inputcurrent is lower than 1.8% and THD of output voltages are

lower than 1.4%. Fig. 22 shows the proposed converter has a

good power quality. Fig. 23 shows the input power factor of

the converter according to the voltage transfer ratios for two

Fig. 24. Laboratory setup of the proposed IMC experiment: (a) Controllerboard. (b) Power circuit board.

loads. The input power factor is almost unity when the total

voltage transfer ratio(q1 +q2 )is near to the maximum voltagetransfer ratio 0.866, and the power factor characteristic of the

total voltage transfer ratio is almost the same as that of the

conventional IMC.

According to the simulated results, the proposed IMC topol-

ogy provides the sinusoidal input current on both of in-

put and output sides. Thus, the proposed carrier-based PWM

method can effectively control the proposed converter with high-

performance current at the power supply and loads.

V. EXPERIMENTAL RESULTS

To validate the proposed theory and simulated results, an ex-

perimental platform is setup in the laboratory. Fig. 24 shows

the laboratory IMC with dual three-phase outputs. The pro-

totype consists of a controller board that executes the control

program, A/D converter, the generating PWM signals, and the

power board. The controller board is developed with a high-

performance DSP TMS320F28335 by Texas Instruments and

a complex programmable logic device EPM7128LC84-15 by

Altera. The power switch IGBTs G4PF50WD have been

used to implement the power circuit in the rectifier and the

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Fig. 25. Zero-dc-link current commutation in the rectifier stage.

Fig. 26. Experimental waveforms of input voltage/current and output currentsunder in-phase CF mode.

Fig. 27. Experimental waveforms of input voltage/current and output currentsunder CF mode with phase shift 45.

inverter stage. The PWM control signals are isolated frompower

circuit by fiber optic (HFBR-1521) to protect controller board.

The frequency of the triangular carrier signal is set as 10 kHzby using the up/down counter, which is available in the DSP. It

should be noted that the experimental parameters and the case

studies are identical to those applied in the simulation.

Fig. 25 shows the dc-link current and the PWM signals for

two bidirectional switches (Sbn , Scn ) in the rectifier stage inorder to verify the current switching, and it is clear that the

commutation betweenSbn and Scn occurs at the time when thedc-link current is zero.

The experimental results shown in Figs. 2630 correspond

to the results shown through simulations shown in Figs. 1721,

and the experimental conditions and commands are exactly the

same as the corresponding conditions and commands used in

Fig. 28. Experimental waveforms of input voltage/current and output currentsunder DF mode.

Fig. 29. Experimental waveforms of input voltage/current and output currentsas the load 1 change from q1 = 0.25,f1 = 50 Hz to q1 = 0.5,f1 = 100 Hzand load 2 change fromq2 = 0.5,f2 =100 Hz toq2 = 0.25,f2 =50 Hz.

Fig. 30. Experimental waveforms ofs of input currents, output voltages ofload 1 and load 2 with closed-loop control.

simulations. In Figs. 2630, the experimental results match the

simulation results exactly: the proposed IMC has a sinusoidal

input current and provides good sinusoidal currents to two inde-

pendent loads. There is a displacement angle between the input

voltage and the input current of the power supply due to the

effect of filter.

Fig. 31 shows the experimental results of THD of the input

current, output voltages of load 1 and load 2 according to the

different output frequencies, where q1 = 0.3 and q2 = 0.5.

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Fig. 31. Experimental results of THDof the input currentand output voltages.

It can be seen that the experimentally obtained THD of the

input current is much higher than that from the simulation due

to the limitation of hardware setup and practical commutation

problem, where all of power switches andLC filter are not the

ideal devices. However, the performance of the output voltages

is comparatively excellent; the THD of output voltages of two

loads is smaller than 2.2%. From Figs. 26 to 31, we found that

the proposed dual three-phase output IMC with carrier based-

PWM modulation method has good performance and operation

similar to that of two independent three-phase IMC.

VI. CONCLUSION

This paper describes a new approach to provide dual three-

phase sources for two three-phase loads based on IMC. The

proposed IMC topology reduces the number of power devices

by two, and is useful and economical in multidrive applica-

tions. The proposed converter provides sinusoidal input/output

currents, and has all the advantages of the IMC, such as the pos-

sibility of soft switching commutation in the rectifier stage and

the simple clamp circuit for safety operation. Also, the carrier-

based PWM method (which is derived from the relationship

with SVPWM) is developed to control the proposed converter

effectively to overcome the complexity of the SVPWM method.

The algorithm uses only one carrier signal to generate the PWM

signals for all switches, including the rectifier stage and the in-

verter stage; therefore, it is easily implemented based on DSP.

In the proposed IMC, the maximum output voltage transfer ra-

tio for each inverter cannot be 0.866 simultaneously; the sum

of two voltage transfer ratios is limited within 0.866. Simu-

lation and experimental results demonstrate that the proposedIMC topology and modulation techniques provide the expected

benefits.

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Tuyen D. Nguyen (M13) was born in BinhDinh,Vietnam, in 1982. He receivedthe B.S. degreein elec-

trical engineering from Ho Chi Minh City Universityof Technology, Vietnam, in 2004, and the Ph.D. de-gree from the University of Ulsan, Ulsan, Korea in2012.

He is currently a Lecturer for the Faculty of Elec-tricaland Electronics Engineering, Ho Chi Minh CityUniversity of Technology. His research interests in-

clude power electronics, electrical machine drives,low-cost inverter, and renewable energy, especially

matrix converters.

Hong-Hee Lee (S88M91SM11) received theB.S., M.S., and Ph.D. degrees in electrical engineer-ing from Seoul National University, Seoul, Korea, in1980, 1982, and 1990, respectively.

From 1994 to 1995, he was a Visiting Professor

with Texas A&MUniversity. Since 1985, he hasbeenwith the Department of Electrical Engineering, Uni-

versity of Ulsan, Ulsan, Korea, where he is currentlya Professor in the School of Electrical Engineering.He is also the Director of the Network-based Au-tomation Research Center, which is sponsored by the

Ministry of Knowledge Economy. His research interests include power elec-tronics, network-based motor control, and renewable energy.

Dr. Lee is a Member of the Korean Institute of Power Electronics, the Ko-rean Institute of Electrical Engineers, and the Institute of Control, Robotics andSystems.

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