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06_DFT1113(Subchapter 2.3)

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Computer Organization
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2.3 BUILD SEQUENTIAL LOGIC CIRCUIT 1 CHAPTER 2 ARITHMETIC AND LOGIC (CONT)
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Page 1: 06_DFT1113(Subchapter 2.3)

2.3 BUILD SEQUENTIAL LOGIC CIRCUIT

1

CHAPTER 2ARITHMETIC AND LOGIC

(CONT)

Page 2: 06_DFT1113(Subchapter 2.3)

• Sequential logic circuit is a memory property circuit and have output that depend on the previous output(s) and current inputs

• In general, a sequential circuit is synchronised by the clock signal (pulse) – synchronised circuit

• The basic block diagram for a sequential circuit is memory device called flip-flop that consist of 2 stable operational states (outputs) Q and .

2

2.3.1 DEFINE SEQUENTIAL LOGIC CIRCUIT

Page 3: 06_DFT1113(Subchapter 2.3)

COMBINATIONAL Versus SEQUENTIAL LOGIC CIRCUIT

Combinational Logic Circuit Sequential Logic CircuitIs a circuit which output is determinedby the input

Composed of combinational circuit andhave some form of inherent memory

Are made up from basic logic NAND, NOR or NOT gates that are combined or connected together to produce more complicated switching circuits.

The current output of a sequential circuit depends not only on the current input, but also on the past history of inputs.

Have no memory, timing or feedback The memory will save information in binary which called state of a sequential circuit at that time

Example : decoders, multiplexers, fulland half adder

Output of sequential circuit not only based on input but also determined by value of present state in memory

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Page 4: 06_DFT1113(Subchapter 2.3)

2.3.2 List the types of Flip Flop

SR flip flop

ClockedSR flip flop

JK flip flop

T flip flop

D flip flop

• Logic gates orcircuit diagram

• Symbol diagram

• Truth table• Timing diagram

FP203 Computer Organisation

4

You have to know below features for each types of flip flop :-

Page 5: 06_DFT1113(Subchapter 2.3)

a) Set Reset Flip Flop ( SR FF)• A flip-flop circuit can be constructed from two NAND gates

ortwo NOR gates.

• Each flip-flop has two outputs, Q and , and two inputs, setand reset.

• 4 states:– Three stable [Set, Reset, and Keep(No Change)].– One not stable [Unused (Invalid)].

• 2 inputs, 2 outputs.• May also contain clock (CLK) signal.

Set -> put value for Q=1 Reset - > put value for Q=0Keep / Hold / Unchanged -> maintained the past value of Q

FP203 Computer Organisation

5

Page 6: 06_DFT1113(Subchapter 2.3)

Basic flip-flop circuit with NOR gates

LOGIC GATESTRUTH TABLE

SYMBOL

S QR

i) NOR GATES SR FLIP FLOP (active HIGH)

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TIMING DIAGRAM NOR GATES SR FLIP-FLOP

9

Page 8: 06_DFT1113(Subchapter 2.3)

TIMING DIAGRAM NOR GATES SR FLIP-FLOP

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ii) NAND GATES SR FLIP FLOP (active LOW)

Basic flip-flop circuit with NAND gates

LOGIC GATESTRUTH TABLE

SYMBOL

S QR

Page 10: 06_DFT1113(Subchapter 2.3)

TIMING DIAGRAM NAND GATES SR FLIP-FLOP

9

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b)Clocked SR Flip-Flop LOGIC GATES

TRUTH TABLE

11

SYMBOL

The clocked SR flip-flop consists of a basic NOR flip- flop and two AND gates. The outputs of the two AND gates remain at logic ‘0’ as long as the clock pulse (or CP) is logic ‘0’, regardless of the S and R input values. When the clock pulse goes to logic ‘1’, information from the S and R inputs passes through to the basic flip-flop. With both S= 1 and R= 1, the occurrence of a clock pulse causes both outputs to momentarily go to logic ‘0’.When the clock pulse is removed, the state of the flip-flop is indeterminate, i.e., either state may result, depending on whether the set or reset input of the flip-flop remains logic ‘1’ longer than the transition to logic ‘0’ at the end of the pulse.

SYMBOL

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TRUTH TABLE

11

TIMING DIAGRAM

*Assuming initial condition: S = 0, R = 0, Q = 0 , build a time diagrambased on sequential value below:

CLK 1, S = 0; R = 0 ; Q =

CLK 2, S = 0; R = 1 ; Q =

CLK 3, S = 1; R = 0 ; Q =

CLK 4, S = 0; R = 1 ; Q =

CLK 5, S = 1; R = 0 ; Q =

CLK 6, S = 1; R = L ; Q =

Once Q is determined, is easily found since it is simply the complement of Q.If clock is in 0, the flip flop will not change even though S and R have changes.

INPUT CLOCK OUTPUT S R Q

0 0 0 Not Changing

0 0 1 Not Changing

0 1 0 Not Changing

0 1 1 0

1 0 0 Not Changing

1 0 1 1

1 1 0 Not Changing

1 1 1 Invalid

Page 13: 06_DFT1113(Subchapter 2.3)

C) JK Flip-Flop

INPUT CLOCK OUTPUT J K Q

0 0 1 Not Changing

0 1 1 0

1 0 1 1

1 1 1 TOGGLE

TRUTH TABLE

Page 14: 06_DFT1113(Subchapter 2.3)

C) JK Flip-Flop Timing Diagram

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d) T- FLIP-FLOP

18

CLOCK T1 0 Q

1 1

TRUTH TABLE

TIMING DIAGRAM

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e) D-Flip-Flop

16

CLOCK D1 0 0

1 1

TRUTH TABLE

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2.3.6 Describe RegisterAs an example of the use of flip-flops, let us first examine one of the essential elements of the CPU: the register. As we know, a register is a digital circuit used within the CPU to store one or more bit of data.

Two basic types of register are commonly used: parallel registers and shift register.

Page 18: 06_DFT1113(Subchapter 2.3)

a) SHIFT REGISTERA shift register accepts and/or transfer information serially. Eg: Figure below shows a 4-bit shift register constructed from clocked D flip-flops. Data are input only to the leftmost flip-flop. With each clock pulse, data are shifted to the right one position, and the rightmost bit is transferred out. Shift registers can be used to interface to serial I/O devices. In addition, they can be used within the ALU to perform logical shift and rotate function.

Page 19: 06_DFT1113(Subchapter 2.3)

This figure illustrates entry of the four bits 1010 into the register, beginning with the right-most bit. The register is initially clear. The 0 is put into the data input line, making D = 0 for FF0. When the first clock pulse is applied, FF0 is RESET, thus storing the 0.

Next the second bit, which is a 1, is applied to the data input, making D = 1 for FF0 and D = 0 for FF1 because the D input of FF1 is connected to the Q0 output. When the second clock pulse occurs, the 1 on the data input is shifted into FF0 because FF0 sets, and the 0 that was in FF0 is shifted into FF1.

The third bit, a 0, is now put onto the data-input line, and a clock pulse is applied. The 0 is entered into FF0, the 1 stored in FF0 is shifted into FF1, and the 0 stored in FF1 is shifted into FF2.

The last bit, a 1, is now applied to the data input, and a clock pulse isapplied. This time the 1 is entered into FF0, the 0 stored in FF0 is shifted into FF1, the 1 stored in FF1 is shifted into FF2, and the 0 stored in FF2 is shifted into FF3. This completes the serial entry of the four bits into the shift register, where they can be stored for any length of time as long as the flip-flops have DC power.

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b) Parallel RegisterFor parallel in/parallel out shift registers, all data bits appear on the parallel outputs immediately following the simultaneous entry of the data bits. The following circuit is a four-bit parallel in/parallel out shift register constructed by D flip-flops.The D's are the parallel inputs and the Q's are the parallel outputs. Once the register is clocked, all the data at the D inputs appear at the corresponding Q outputs simultaneously.

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2.3.7 Memory organisationBuilding large memories required a different organization, one in which individual words can be addressed. A widely-usedmemory organization that meets this criterion is shown in the next figure. This example illustrates a memory with four 3-bit words. Each operation reads or writes afull 3-bit word. While the total memory capacity of 12 bits is hardly more thanour octal flip-flop, it requires fewer pins and most important, the design extendseasily to large memories.

It has eight input lines and three output lines. Three inputs are data: I0 , I1, and I2 ; two are for the address: A0 and A1 ; and three are for control: CS for Chip Select, RD for distinguishing between read and write, and OE for Output Enable. The three outputs are for data: O0, O1, and O2 . In principle this memory could be put into a 14-pin package, including power and ground versus 20 pins for the octal flip-flop.

To select this memory chip, external logic must set CS high and also set RDhigh (logical 1) for read and low (logical 0) for write. The two address lines mustbe set to indicate which of the four 3-bit words is to be read or written. For a readoperation, the data input lines are not used, but the word selected is placed on thedata output lines. For a write operation, the bits present on the data input lines areloaded into the selected memory word; the data output lines are not used.

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