11

68HC11 Timer68HC11 Timer

Chapter 10Chapter 10

22

68HC11 Timer Subsystem68HC11 Timer SubsystemSeveral timing functions:Several timing functions: Basic timingBasic timing Real time interruptsReal time interrupts Output compareOutput compare Input captureInput capture Computer Operating ProperlyComputer Operating Properly Pulse AccumulatorPulse Accumulator Pulse Width Modulation Pulse Width Modulation

Common FeaturesCommon Features Based on a central timerBased on a central timer Overflow FlagsOverflow Flags Interrupt EnablesInterrupt Enables

33

Timer System Block DiagramTimer System Block Diagram

44

Basic TimerBasic Timer

55

Basic Timer– TCNTBasic Timer– TCNT$100E$100E

16-bit free running counter (timer)16-bit free running counter (timer) Cannot be set or stopped. Cannot be set or stopped.

Fclk = system clockFclk = system clockCan be prescaled by 1,4,8, or 16Can be prescaled by 1,4,8, or 16Read only at memory address ($100E)Read only at memory address ($100E) Overflow flag is bit 7 in TFLG2 ($1025)Overflow flag is bit 7 in TFLG2 ($1025)

Can use overflow to extend counter’s rangeCan use overflow to extend counter’s range Timer Overflow Interrupt Enable Timer Overflow Interrupt Enable

Bit 7 in TMSK ($1024)Bit 7 in TMSK ($1024)

66

TCNT - $100E:$100FTCNT - $100E:$100FTimer Counter RegisterTimer Counter Register

7 6 5 4 3 2 1 0

Bits

CNT15

READ ONLY Register

CNT13 CNT12 CNT11 CNT10 CNT9 CNT8CNT14

7 6 5 4 3 2 1 0

CNT7 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0CNT6

$100E

$100F

77

PrescalerPrescaler

7 6 5 4 3 2 1 0

Bits

PR2PR1PAII 00PAOVIRTHTOI

Timer Interrupt Mask Register 2: $1024 -- TFLG2

PR1,PR0 = Timer prescale select - Timer Clock = System Clock / Prescale Factor

Pr1 Pr0 Prescale Factor 0 0 1 0 1 2 1 0 4 1 1 16

88

Timer Overflow FlagTimer Overflow Flag

7 6 5 4 3 2 1 0

Bits

00PAIF 00PAOVFRTIFTOF

Miscellaneous Timer Interrupt Flag Register 2: $1025 (TFLG2)

TOF = Timer overflow flag - 0 = No overflow 1 = Overflow

TOF is reset to 0 by writing ‘1’ to TOF

99

Timer Overflow InterruptsTimer Overflow Interrupts

7 6 5 4 3 2 1 0

Bits

PR2PR1PAII 00PAOVIRTHTOI

Timer Interrupt Mask Register 2: $1024 (TMSK2)

TOI = Timer overflow interrupt enable 0 = disable interrupt 1 = enable interrupt

1010

Basic Timer ExampleBasic Timer Example

Problem: Write an ISR to read the input from Problem: Write an ISR to read the input from PortC and write it to PortB approximately PortC and write it to PortB approximately every 1,000,000 clock cycles. Assume timer every 1,000,000 clock cycles. Assume timer prescale = 1prescale = 1

1111

Basic Timer ExampleBasic Timer ExampleMain ProgramMain Program

Configure Timer Overflow InterruptConfigure Timer Overflow Interrupt TMSK2(7) TMSK2(7) ‘1’ ‘1’

Enable Interrupts (CLI)Enable Interrupts (CLI)

RepeatRepeat

Until ForeverUntil Forever

Set Timer Overflow Interrupt VectorSet Timer Overflow Interrupt Vector ORG TOI_VECTOR ($FFDE:FFDF)ORG TOI_VECTOR ($FFDE:FFDF) FDB TO_ISRFDB TO_ISR

1212

Basic Timer ExampleBasic Timer ExampleTO_ISRTO_ISR

Disable Interrupts Disable Interrupts SEISEI

Turn-off Interrupt RequestTurn-off Interrupt Request TOF TOF ‘1’ ‘1’

CNT = CNT + 1CNT = CNT + 1IF CNT = MAX_CNT thenIF CNT = MAX_CNT then CNT = 0CNT = 0 A A PORTC PORTC PORTB PORTB A A

END IFEND IFReturn from InterruptReturn from Interrupt

1313

Basic Timer ExampleBasic Timer ExampleMAX_CNT Calculation MAX_CNT Calculation

Need to wait 1,000,000 or $F4240 clock Need to wait 1,000,000 or $F4240 clock cycles.cycles.

Interrupt is generated every 65536 or $10000 Interrupt is generated every 65536 or $10000 clock cyclesclock cyclesMax_CNT = INT(1,000,000 / 65556) = 15.258 ~ 15 = $FMax_CNT = INT(1,000,000 / 65556) = 15.258 ~ 15 = $F Note: INT($F4240/$10000) = $FNote: INT($F4240/$10000) = $F

Set MAX_CNT EQU $FSet MAX_CNT EQU $F

1414

Real Time InterruptReal Time Interrupt

1515

Real Time InterruptReal Time Interrupt

Similar to Timer Overflow Interrupt exceptSimilar to Timer Overflow Interrupt except

We have:We have: RTI Flag (RTIF) – Bit 6 in TFLG2 ($1025)RTI Flag (RTIF) – Bit 6 in TFLG2 ($1025) RTI Enable (RTII) – Bit 6 in TMSK2 ($1024)RTI Enable (RTII) – Bit 6 in TMSK2 ($1024) System Clock is first divided by $1000 then System Clock is first divided by $1000 then

divided again by the prescale bits given by divided again by the prescale bits given by RTR1 and RTR0 in PACTL ($1026)RTR1 and RTR0 in PACTL ($1026)

1616

Real Time Interrupt Real Time Interrupt EnableEnable

7 6 5 4 3 2 1 0

Bits

PR2PR1PAII 00PAOVIRTIITOI

Timer Interrupt Mask Register 2: $1024 (TMSK2)

RTII = Real Time Interrupt Enable 0 = disable interrupt 1 = enable interrupt

1717

Real Time Interrupt FlagReal Time Interrupt Flag

7 6 5 4 3 2 1 0

Bits

00PAIF 00PAOVFRTIFTOF

Miscellaneous Timer Interrupt Flag Register 2: $1025 (TFLG2)

RTIF = Real Time Interrupt flag - 1 = RTI has occurred

RTIF is reset to 0 by writing ‘1’ to RTIF

1818

Real Time InterruptReal Time InterruptPrescalePrescale

7 6 5 4 3 2 1 0

Bits

RTR0RTR1PEDGEPAMODPAEN6DDRA7 00

RTR1, RTR0= Real Time Interrupt Prescale

RTR1 RTR0 Nominal RTI rate (2MHz E-Clock) 0 0 4.096ms 0 1 8.192ms 1 0 16.384ms 1 1 32.768ms

Port A Control Register: $1026 (PACTL)

1919

TPS QuizTPS Quiz

2020

Computer Operating Computer Operating ProperlyProperly

COPCOP

2121

Computer Operating ProperlyComputer Operating ProperlyCOPCOP

Also known as a “watchdog” timerAlso known as a “watchdog” timer When enabled, your program must set the When enabled, your program must set the

COP timer and reset the COP timer COP timer and reset the COP timer priorprior to to the COP’s “time-out” delay. This time-out the COP’s “time-out” delay. This time-out delay is programmable.delay is programmable.

If the program does not set or reset the COP If the program does not set or reset the COP timer timer beforebefore the “time-out”, a COP failure the “time-out”, a COP failure interrupt is generated and the ISR assigned to interrupt is generated and the ISR assigned to the interrupt is executed. the interrupt is executed.

2222

Computer Operating ProperlyComputer Operating ProperlyCOPCOP

UsageUsage Design your program to set and reset the Design your program to set and reset the

COP before time-out.COP before time-out. If your program enters an infinite loop, the If your program enters an infinite loop, the

COP timer will “time-out” automatically COP timer will “time-out” automatically causing a COP failure interrupt. causing a COP failure interrupt.

Use the COP failure ISR to place your system Use the COP failure ISR to place your system into a “safe” mode or restart mode. into a “safe” mode or restart mode.

2323

Output CompareOutput Compare

2424

Timer Output CompareTimer Output Compare

Using the timer overflow flag or interrupt will Using the timer overflow flag or interrupt will generate a count every 65536 clock cycles.generate a count every 65536 clock cycles.

Given a 2MHz clock, this gives a sample Given a 2MHz clock, this gives a sample resolution of 32.8msresolution of 32.8ms

The timer output compare feature allows for The timer output compare feature allows for more precise timing.more precise timing.

2525

Timer Output CompareTimer Output Compare

There are five output compare registersThere are five output compare registers

Each with a separateEach with a separate Compare CounterCompare Counter Interrupt MaskInterrupt Mask Overflow FlagOverflow Flag

2626

TOC1 – TOC5 TOC1 – TOC5 Timer Output Compare RegistersTimer Output Compare Registers

7 6 5 4 3 2 1 0

Bits

OCn15

TOC1 - $1016:$1017TOC2 - $1018:$1019TOC3 - $101A:$101B

OCn13 OCn12 OCn11 OCn10 OCn9 OCn8OCn14

7 6 5 4 3 2 1 0

OCn7 OCn5 OCn4 OCn3 OCn2 OCn1 OCn0OCn6

TOC4 - $101C:$101DTOC5 - $101E:$101F

2727

Output Compare FlagsOutput Compare Flags

7 6 5 4 3 2 1 0

Bits

IC3FIC2FOC4F IC1FOC5FOC3FOC2FOC1F

Main Timer Interrupt Flag Register 1: $1023 (TFGL1 )

OC1F-OC5F = Output Compare Flags 1 = when output compare register equals TCNT 0 = reset by writing ‘1’ to bit position

2828

Output Compare InterruptsOutput Compare Interrupts

7 6 5 4 3 2 1 0

Bits

IC3IIC2IOC4I IC1IOC5IOC3IOC2IOC1I

Main Timer Interrupt Mask Register 1: $1022 (TMSK1)

OC1I-OC5I = Output Compare interrupt enable 0 = disable interrupt 1 = enable interrupt

2929

Output Compare ExampleOutput Compare Example

Problem: Write an ISR to read the input Problem: Write an ISR to read the input from PortC and write it to PortB from PortC and write it to PortB approximately every 10,000 clock cycles. approximately every 10,000 clock cycles. Assume timer prescale = 1Assume timer prescale = 1

Note: 10,000 cycles is less than one timer Note: 10,000 cycles is less than one timer overflow!!overflow!!

3030

Output Compare ExampleOutput Compare ExampleMain ProgramMain Program

AA TCNT ; Load current count TCNT ; Load current countTOC1 TOC1 A + 10000 ; Add 10000 to current count A + 10000 ; Add 10000 to current count Configure Output Compare 1 InterruptConfigure Output Compare 1 Interrupt

TMSK1(7) TMSK1(7) ‘1’ ‘1’

Enable Interrupts (CLI)Enable Interrupts (CLI)RepeatRepeatUntil ForeverUntil Forever

Set Output Compare 1 Interrupt VectorSet Output Compare 1 Interrupt Vector ORG OC1_VECTOR ($FFE8:FFE9)ORG OC1_VECTOR ($FFE8:FFE9) FDB OC1_ISRFDB OC1_ISR

3131

Output Compare ExampleOutput Compare ExampleOC1_ISROC1_ISR

Disable Interrupts Disable Interrupts SEISEI

Turn-off Interrupt RequestTurn-off Interrupt Request OC1F OC1F ‘1’ ‘1’

A A PORTC PORTCPORTB PORTB A AA A TCNT ; Load current count TCNT ; Load current countTOC1 TOC1 A+10000 ; update TOC1 for next A+10000 ; update TOC1 for next interruptinterruptReturn from InterruptReturn from Interrupt

3232

Input CaptureInput Capture

3333

Timer Input CaptureTimer Input Capture

16-bit TCIx LatchDetCkt

TCNT

clkExt Signal

When the Ext Signal is detected on pin PAx, the current value of the free running counte TCNT is latched into the timer input capture latch. This value can be read and saved to determine the time between events.

PAx

3434

Timer Input CaptureTimer Input Capture

The timer input capture feature can be used The timer input capture feature can be used to time external eventsto time external events

Three input capture registersThree input capture registers TIC1 : $1010:$1011TIC1 : $1010:$1011 TIC2 : $1012:$1013TIC2 : $1012:$1013 TIC3: $1014:$1015TIC3: $1014:$1015

Maximum time between events must be less Maximum time between events must be less than 65536 cyclesthan 65536 cycles

3535

TIC1 – TIC3 TIC1 – TIC3 Timer Input Capture RegistersTimer Input Capture Registers

7 6 5 4 3 2 1 0

Bits

ICn15

TIC1 - $1010:$1011TIC2 - $1012:$1013TIC3 - $1014:$1015

ICn13 ICn12 ICn11 ICn10 ICn9 ICn8ICn14

7 6 5 4 3 2 1 0

ICn7 ICn5 ICn4 ICn3 ICn2 ICn1 ICn0ICn6

3636

Input Compare InterruptsInput Compare Interrupts

7 6 5 4 3 2 1 0

Bits

IC3IIC2IOC4I IC1IOC5IOC3IOC2IOC1I

Main Timer Interrupt Mask Register 1: $1022 (TMSK1)

IC1I-IC3I = Input Compare interrupt enable 0 = disable interrupt 1 = enable interrupt

3737

Interrupt Capture FlagsInterrupt Capture Flags

7 6 5 4 3 2 1 0

Bits

IC3FIC2FOC4F IC1FOC5FOC3FOC2FOC1F

Main Timer Interrupt Flag Register 1: $1023 (TFGL1 )

IC1F-IC3F = Interrupt Capture Flags 1 = when selcted edge is detected 0 = reset by writing ‘1’ to bit position

3838

Timer Control Register 2Timer Control Register 2TCTL2 - $1021TCTL2 - $1021

7 6 5 4 3 2 1 0

Bits

EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A0 0

EDGnB EDGnA Configuration 0 0 Disabled 0 1 Rising Edge 1 0 Falling Edge 1 1 Either Edge

3939

Pulse AccumulatorPulse Accumulator

4040

Pulse AccumulatorPulse Accumulator

The pulse accumulator can be used as an event The pulse accumulator can be used as an event counter. That is, it can count the number of counter. That is, it can count the number of external events. external events. Note: difference to Timer Input Capture which Note: difference to Timer Input Capture which counts the counts the timetime between external events. between external events. Configuration:Configuration: PACTL ($1026) is used to configure PAPACTL ($1026) is used to configure PA PACNT ($1027) is the PA Count RegisterPACNT ($1027) is the PA Count Register

Two Modes:Two Modes: Event Counting: PA7 is External ClockEvent Counting: PA7 is External Clock Gated Time Accumulation: PA7 is enable to system Gated Time Accumulation: PA7 is enable to system

clock divided by 64clock divided by 64

4141

PACTL: $1026PACTL: $1026Port A Control RegisterPort A Control Register

7 6 5 4 3 2 1 0

Bits

RTR0RTR1PEDGEPAMODPAEN6DDRA7 00

PAEN6 = Pulse Accumulator System Enable0 = Disable (Default)

Port A is set for I/O function1 = Enable

Port A is set for Pulse Accumulator function

PAMOD= Pulse accumulator mode0 = Event counter (Default)1 = Gated time accumulation

4242

PACTL: $1026PACTL: $1026Port A Control RegisterPort A Control Register

7 6 5 4 3 2 1 0

Bits

RTR0RTR1PEDGEPAMODPAEN6DDRA7 00

PEDGE= Pulse Accumulator Edge Select0 = Falling Edge (in event mode) – Active High (in gated mode)1 = Rising Edge (in event mode) – Active Low (in gated mode)

4343

Pulse Accumulator FlagPulse Accumulator Flag

7 6 5 4 3 2 1 0

Bits

00PAIF 00PAOVFRTIFTOF

Miscellaneous Timer Interrupt Flag Register 2: $1025 (TFLG2)

PAOVF = Pulse Accumulator Overflow Flag 1 = Overflow has occurred

PAOVF is reset to 0 by writing ‘1’ to PAOVF

PAIF = Pulse Accumulator Input Edge Flag 1 = Input edge has been detected

PAIF is reset to 0 by writing ‘1’ to PAIF

4444

Pulse Accumulator Interrupts Pulse Accumulator Interrupts

7 6 5 4 3 2 1 0

Bits

PR2PR1PAII 00PAOVIRTIITOI

Timer Interrupt Mask Register 2: $1024 (TMSK2)

PAOVI = Pulse Accumulator overflow interrupt enable 0 = disable interrupt 1 = enable interrupt

PAII = Pulse Accumulator input edge interrupt enable 0 = disable interrupt 1 = enable interrupt

4545

Pulse Width ModulationPulse Width Modulation

4646

Pulse Width ModulationPulse Width Modulation

Some versions of 68HC11 have a pulse Some versions of 68HC11 have a pulse width modulation (PWM) module which width modulation (PWM) module which can be used to can be used to generategenerate periodic output periodic output waveforms with a specific period and duty waveforms with a specific period and duty cycle (i.e. the percentage of time the cycle (i.e. the percentage of time the signal is high compare to when it is low).signal is high compare to when it is low).

4747

Timer SummaryTimer SummaryTimer subsystem – most complex in 68HC11Timer subsystem – most complex in 68HC11Based on free running timerBased on free running timerTimings available:Timings available: Basic timingBasic timing Real time interruptsReal time interrupts Output compareOutput compare Input captureInput capture Computer Operating ProperlyComputer Operating Properly Pulse AccumulatorPulse Accumulator Pulse Width Modulation Pulse Width Modulation

Overflow flags and/or Interrupts are availableOverflow flags and/or Interrupts are available