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8 Bit ALU

Rahul Vyas

Gyanesh Chhipa

Jaimin Shah

Advisor: Dr.David W. Parent

05/08/2006

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Abstract

• The 8-bit ALU that our group designed can perform 8 arithmatic function and 4 logic function

• The 8s-bit ALU is made up of 2 identical 4-bit ALU, and 25 DFFs.

• We designed an 8-bit carry look ahead adder that operated at 200 MHz

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Introduction

• An ALU is the fundamental unit of any computing system.• Understanding how an ALU is designed and how it works

is essential to building any advanced logic circuits.• Using this knowledge and experience, we can move on to

designing more complex integrated circuits.• Design consists of different kinds of logic… Look ahead

carry generator, adder, Subtractor, Transfer Data, DFF, Multiplexer, Inv, and, Xor, etc

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Project Summary

• Created Schematic• Tested the schematics logic by using NCVerilog.• Finding longest path• Sizing of Wn and Wp• Layout of individual block• Checked DRC and LVS for each block• Integrated every block• Checked DRC and LVS for final layout• Verify the timing• Measure power

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Block diagram of our project

ARITHMETIC CIRCUIT

LOGICAL CIRCUIT

DFF’S

MUX

DFF’S

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Project Details

[1]SELECTION OUTPUT FUNCTION

S2 S1 S0 CIN

0 0 0 0 F=A Transfer A

0 0 0 1 F=A+1 Increment A

0 0 1 0 F=A+B Addition

0 0 1 1 F=A+B+1 Add with Carry

0 1 0 0 F=A-B-1 Substract with Borrow

0 1 0 1 F=A-B Substraction

0 1 1 0 F=A-1 Decrement A

0 1 1 1 F=A Transfer A

1 0 0 X F=AB OR

1 0 1 X F=AB XOR

1 1 0 X F=AB AND

1 1 1 X F=Ā Complement A

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Gate level schematic of our circuit

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Transistor Level Schematic

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NC VERILOG VERIFICATION

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Longest path in the circuit

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Longest Path Calculations

Note: All widths are in Cmand capacitances in fF

CELL BIT#Cg or Cin of loadCg+Cint NSN NSP N M WN Load WP Load WN (HC) WP(HC) WN WPnand2 18 2.00E-14 3.30E-14 2 1 3 2 0.00E+00 0.00E+00 9.61E-04 8.61E-04 5.20E-04 6.00E-04inv 17 1.86E-14 3.16E-14 1 1 1 1 5.06E-04 6.00E-04 4.77E-04 8.61E-04 5.06E-04 9.40E-04

nand3 16 2.43E-14 3.73E-14 3 1 5 2 5.06E-04 9.40E-04 9.77E-04 5.74E-04 5.20E-04 3.95E-04nand2 15 4.85E-14 6.15E-14 2 1 3 2 5.06E-04 9.40E-04 9.55E-04 8.51E-04 6.00E-04 6.50E-04inv 14 4.20E-14 5.50E-14 1 1 1 1 6.00E-04 6.50E-04 5.40E-04 9.72E-04 4.59E-04 8.26E-04

nand3 13 2.16E-14 3.46E-14 3 1 5 2 4.59E-04 8.26E-04 9.82E-04 5.77E-04 4.50E-04 3.50E-04nand2 12 2.69E-14 3.99E-14 2 1 3 2 4.50E-04 3.50E-04 9.57E-04 8.51E-04 4.00E-04 4.45E-04inv 11 1.42E-14 2.72E-14 1 1 1 1 4.00E-04 4.45E-04 4.74E-04 8.56E-04 3.60E-04 5.40E-04

nand3 10 3.02E-14 4.32E-14 3 1 5 2 3.60E-04 5.40E-04 9.85E-04 5.75E-04 4.00E-04 2.70E-04nand2 9 1.12E-14 2.42E-14 2 1 3 2 4.00E-04 2.70E-04 9.41E-04 8.41E-04 4.50E-04 5.00E-04inv 8 3.19E-14 4.49E-14 1 1 1 1 4.50E-04 5.00E-04 5.40E-04 9.70E-04 3.50E-04 5.80E-04

nand3 7 3.12E-14 4.42E-14 3 1 5 2 3.50E-04 5.80E-04 9.91E-04 5.78E-04 3.80E-04 2.50E-04xpart 7 2.11E-14 3.41E-14 2 2 6 2 3.80E-04 2.50E-04 5.71E-04 9.95E-04 2.30E-04 2.90E-04inv 6 1.75E-14 3.05E-14 1 1 1 1 2.30E-04 2.90E-04 5.44E-04 9.79E-04 3.00E-04 4.80E-04

nand3 5 2.62E-14 3.92E-14 3 1 5 2 3.00E-04 4.80E-04 9.97E-04 5.82E-04 3.00E-04 2.10E-04nand2 4 1.71E-14 3.01E-14 2 1 3 2 3.00E-04 2.10E-04 9.66E-04 8.59E-04 3.50E-04 3.70E-04inv 3 2.42E-14 3.72E-14 1 1 1 1 3.50E-04 3.70E-04 5.50E-04 9.89E-04 3.50E-04 5.35E-04

nand3 2 2.97E-14 4.27E-14 3 1 5 2 3.50E-04 5.35E-04 9.86E-04 5.73E-04 4.50E-04 2.80E-04inv 1 2.45E-14 3.75E-14 1 1 1 1 4.50E-04 2.80E-04 5.49E-04 9.89E-04 5.50E-04 9.00E-04

Tphl = 5ns/19 = 0.263ns

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Individual Block Layout

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Layout

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Verification

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VerificationLVS

The net lists matched

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Test Bench and Simulations

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Output Graphs

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Cost Analysis

– verifying logic: 2 weeks– verifying timing: 1 week– Layout: 1weeks– post extracted timing: 5 days

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Lessons Learned

• Aspects of design processes• Simulation and verification tools• Optimize transistor size to meet specification• Use instances• See Dr. Parent more often to understand the

concept fully.

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SummaryProject: Our 8-Bit ALU has 1520 transistors and 33 terminals. The circuit can operate up to 250MHz. Designed a 8-Bit ALU that performs eight arithmetic and

four logical functions at 200MHz frequency with setup and hold time 1ns, driving up to 30fF.

• This circuit can be used as a building block for 16/32-bit ALU.

• The Logic design can be modified to perform more functions.

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Acknowledgements

• Thanks to Professor David Parent for his Guidance And Help

• Thanks to Cadence Design Systems for the VLSI lab