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VHDL: A HARDWARE DESCRIPTION LANGUAGEVLSI Design TechniquesVLSI Design Techniques

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Nizar Abdallah

Basic StructuresBasic Structures

Basic Building BlocksBasic Building BlocksBasic Building Blocks

�� EntityEntity

�� ArchitectureArchitecture

�� ConfigurationConfiguration

�� PackagePackage

�� LibraryLibrary


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Entity Declaration (1)Entity Declaration (1)

The External Aspect of a Design UnitThe External Aspect of a Design UnitThe External Aspect of a Design Unit

entityentity entity_name entity_name isis[generic_declaration][generic_declaration][port_clause][port_clause]{ entity_declarative_item}{ entity_declarative_item}

[[beginbeginentity_statement_part]entity_statement_part]

endend [entity_name];[entity_name];


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Entity Declaration (2)Entity Declaration (2)

ExampleExampleExample

AA BBCinCin

SS CoutCout

entityentity FULL_ADDER FULL_ADDER isispor tpor t ((A, B,A, B, CinCin : : inin BITBIT ;;

S,S, CoutCout : : outout BITBIT););

endend FULL_ADDERFULL_ADDER;;FULLFULL

ADDERADDER

MODEMODE:: inin, , outout ,, inoutinout ......

DATA TYPEDATA TYPE


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Architectures (1)Architectures (1)

The Internal Aspect of a Design UnitThe Internal Aspect of a Design UnitThe Internal Aspect of a Design Unit

architecturearchitecture architecture_name architecture_name of of entity_name entity_name isis{ architecture_declarative_part}{ architecture_declarative_part}

beginbegin{ architecture_descriptive_part}{ architecture_descriptive_part}

endend [architecture_name];[architecture_name];

�� Collection of Collection of CCONCURRENT ONCURRENT Statements Executed in Statements Executed in PPARALLELARALLEL

�� Concurrent Statements Communicate through Concurrent Statements Communicate through SSIGNALSIGNALS


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A Behavioral StyleA Behavioral StyleA Behavioral Style

entityentity FULL_ADDER FULL_ADDER isispor tpor t ((A, B,A, B, CinCin : : inin BITBIT ;;

S,S, CoutCout : : outout BITBIT););endend FULL_ADDERFULL_ADDER;;architecturearchitecture DATAFLOWDATAFLOW ofof FULL_ADDER FULL_ADDER isis

signalsignal X : X : BITBIT ;;beginbegin

XX <= <= AA xorxor B;B;SS <= <= XX xorxor CinCin afterafter 1010 nsns;;CoutCout <= <= (A (A andand B) B) oror (X (X andand CinCin) ) afterafter 55 nsns;;

endend DATAFLOWDATAFLOW;;


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A Structural StyleA Structural StyleA Structural Style

architecturearchitecture STRUCTURE STRUCTURE ofof FULL_ADDER FULL_ADDER isiscomponentcomponent HALF_ADDERHALF_ADDER

por tpor t (( I1, I2I1, I2 : : inin BITBIT ;;Carry, SCarry, S : : outout BITBIT););

end componentend component ;;

componentcomponent OR_GATEOR_GATE

por tpor t (( I1, I2I1, I2 : : inin BITBIT ;;OO : : outout BITBIT););

end componentend component ;;signalsignal X1, X2, X3 : X1, X2, X3 : BITBIT ;;

DECLARATIVE

PART

DDECLARATIVEECLARATIVE

PPARTART


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A Structural StyleA Structural StyleA Structural Style

beginbeginHA1HA1 : : HALF_ADDERHALF_ADDER por t map por t map ((

I1 I1 => => A, I2 A, I2 => => B, Carry B, Carry => => X1, S X1, S => => X2);X2);HA2HA2 : : HALF_ADDERHALF_ADDER por t map por t map ((

I1 I1 => => X2, I2 X2, I2 =>=> CinCin, Carry , Carry => => X3, S X3, S => => S);S);OR1OR1 : : OR_GATEOR_GATE por t map por t map ((

I1 I1 => => X1, I2 X1, I2 => => X3, O X3, O =>=> CoutCout););endend STRUCTURE STRUCTURE ;; DESCRIPTIVE

PART

DDESCRIPTIVEESCRIPTIVE

PPARTART


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Structural Style to represent HierarchyStructural Style to represent HierarchyStructural Style to represent Hierarchy

HA1HA1HA2HA2

OR1OR1AA

BB SSCinCin

CoutCout

entityentity--architecturearchitecture




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Structure & Behavior in a Design TreeStructure & Behavior in a Design TreeStructure & Behavior in a Design Tree

StructuralStructural

BehavioralBehavioral


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entity/architecture: a One to Many Relationshipentity/architecture: a entity/architecture: a One to ManyOne to Many RelationshipRelationship

AA BBCINCIN

SS COUTCOUT

FULLFULLADDERADDER

CINCINAABB

COUTCOUT

SS

X <= A xor B; S <= X xor CIN;COUT <= (A and B) or

(X and CIN);


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Configurations (1)Configurations (1)

Specification Inside the Architecture BodySpecification Inside the Architecture BodySpecification Inside the Architecture Body

forfor instantiation_list: component_name instantiation_list: component_name use use binding_indication;binding_indication;

�� Binding a couple "Binding a couple " entityentity//architecturearchitecture" to each instance" to each instance

useuse library_name.entity_name [(architecture_name)];library_name.entity_name [(architecture_name)];


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Configurations (2)Configurations (2)

Declaration as a Separate Design UnitDeclaration as a Separate Design UnitDeclaration as a Separate Design Unit

configurationconfiguration configuration_name configuration_name of of entity_name entity_name isisforfor { architecture | component } binding_indication;{ architecture | component } binding_indication;

endend [configuration_name];[configuration_name];

�� Can be compiled separately and stored in a libraryCan be compiled separately and stored in a library

�� I t defines a configuration for a par ticular entityI t defines a configuration for a par ticular entity


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PackagesPackages

Global Design UnitGlobal Design UnitGlobal Design Unit

packagepackage package_name package_name isis{ package_declarative_item}{ package_declarative_item}

endend [package_name];[package_name];package bodypackage body package_name package_name isis

{ package_body_declarative_item}{ package_body_declarative_item}endend [package_name];[package_name];

�� Same declarations visible by a number of design entitiesSame declarations visible by a number of design entities

�� May contain subprograms, components, signals, ...May contain subprograms, components, signals, ...


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Design LibrariesDesign Libraries

�� May contain: May contain: packagespackages, , entitiesentities, , architecturesarchitectures, , configurationsconfigurations

librarylibrary library_name ;library_name ;useuse library_name.package_name.library_name.package_name.allall ;;

STDSTDSTD

IEEEIEEEIEEE

PROJECT_LIBPROJECT_LIBPROJECT_LIB

WORKWORKWORK

VHDLVHDLfilesfiles

AANNAALLYYZZEERR

SSIMULATORIMULATOR

SSYNTHESIZERYNTHESIZER


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Data Objects (1)Data Objects (1)

Three ClassesThree ClassesThree Classes

�� ConstantsConstants

�� Initialized to a specific value and Initialized to a specific value and nevernever modifiedmodifiedconstant MSB : INTEGER := 5;

�� Var iablesVar iables

�� Used to hold temporary dataUsed to hold temporary data

�� OnlyOnly used within processes & subprogramsused within processes & subprograms

variable variable DELAYDELAY : : INTEGER range INTEGER range 0 0 to to 15 := 0;15 := 0;


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Data Objects (2)Data Objects (2)

Three ClassesThree ClassesThree Classes

�� SignalsSignals

�� Used to communicate between processesUsed to communicate between processes

�� When declared in a package : When declared in a package : Global SignalsGlobal Signals

�� Also declared within entities, blocks, architecturesAlso declared within entities, blocks, architectures

�� Can be used but not defined in processes and Can be used but not defined in processes and subprogramssubprograms

signal CLK : BIT;


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Data Types (0)Data Types (0)

�� Each signal must have a data type associated with it when Each signal must have a data type associated with it when the signal is declaredthe signal is declared

�� A type defines a set of valuesA type defines a set of values

�� An assignment must always be of a value defined by that An assignment must always be of a value defined by that setset

�� Types in either sides of the assignment must matchTypes in either sides of the assignment must match

ConceptConceptConcept


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�� The first identifier is the default valueThe first identifier is the default valuetypetype COLOR COLOR is is (RED, ORANGE, YELLOW);(RED, ORANGE, YELLOW);

type type TERNARY TERNARY isis ( '1', '0', 'X' );( '1', '0', 'X' );

var iablevar iable X : COLOR;X : COLOR;

signalsignal Y : TERNARY;Y : TERNARY;

Enumeration TypesEnumeration TypesEnumeration Types


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�� The range must be specifiedThe range must be specified

�� No logical operations on integerNo logical operations on integertypetype MEMORY_SIZE MEMORY_SIZE is range is range 1 1 toto 2048;2048;

Integer TypesInteger TypesInteger Types


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�� BOOLEANBOOLEAN : (false , true): (false , true)�� BIT BIT : ( '0' , '1' ): ( '0' , '1' )�� CHARACTERCHARACTER�� INTEGER INTEGER : range : range --2 147 483 647 to +2 147 483 6472 147 483 647 to +2 147 483 647�� NATURAL NATURAL : Subtype of : Subtype of INTEGERINTEGER (Non Negative)(Non Negative)�� POSITIVE POSITIVE : Subtype of : Subtype of INTEGERINTEGER (positive)(positive)�� BIT_VECTOR BIT_VECTOR : ar ray of BIT values: ar ray of BIT values�� STRING STRING : ar ray of : ar ray of CHARACTERSCHARACTERS

�� REAL REAL : range : range --1.0E+38 to +1.0E+381.0E+38 to +1.0E+38�� TIME TIME : Physical type used for simulation: Physical type used for simulation

Predefined VHDL Data TypesIEEE 1076-1987 Standard Package

Predefined VHDL Data TypesPredefined VHDL Data TypesIEEE 1076IEEE 1076--1987 Standard Package1987 Standard Package


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�� Constrained ArrayConstrained Arraytypetype VEC_64 VEC_64 is ar ray is ar ray (0 (0 toto 63) 63) of INTEGERof INTEGER;;

var iablevar iable S : VEC_64;S : VEC_64;

var iablevar iable S1 : S1 : INTEGERINTEGER;;

S1 := S (1);S1 := S (1);

�� Unconstrained ArrayUnconstrained Arraytypetype BIT_VECTOR BIT_VECTOR is ar ray is ar ray ((POSITIVE range <>POSITIVE range <>) ) of BITof BIT;;

signalsignal S : S : BIT_VECTOR BIT_VECTOR (4(4 downtodownto 0);0);

�� MultipleMultiple DimentionalDimentional ArraysArraystypetype TWO_D TWO_D is ar ray is ar ray (0 (0 toto 7, 0 7, 0 toto 3) 3) of INTEGERof INTEGER;;

Ar ray TypesArray TypesArray Types


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�� z_bus <= c_bus;z_bus <= c_bus;

�� z_bus ( 3 z_bus ( 3 downto downto 2 ) <= “ 00” ;2 ) <= “ 00” ;

�� c_bus ( 2 to 4 ) <= z_bus ( 3c_bus ( 2 to 4 ) <= z_bus ( 3 downtodownto 1 );1 );

�� z_bus ( 0 to 1 ) <= “ 00” ;z_bus ( 0 to 1 ) <= “ 00” ;

�� z_bus <= A & B & C & D;z_bus <= A & B & C & D; -- -- concatenateconcatenate

�� z_bus <= ( A , B , C , D );z_bus <= ( A , B , C , D ); -- -- aggregatesaggregates

�� z_bus <= ( 3=>’1’ , 1 z_bus <= ( 3=>’1’ , 1 downto downto 0 => ’1’ , 2 => B ); 0 => ’1’ , 2 => B ); -- -- by nameby name

�� z_bus <= ( 3=>’1’ , 1 => ’0’ , others => B ); z_bus <= ( 3=>’1’ , 1 => ’0’ , others => B ); -- -- synthesissynthesis

Array Assignements : by POSITIONsignal z_bus : bit_vector ( 3 downto 0 );signal c_bus : bit_vector ( 1 to 4 );signal A, B, C, D : BIT;

Array Array Assignements Assignements : by POSITION: by POSITION

signalsignal z_busz_bus : bit_vector (: bit_vector ( 33 downtodownto 0 0 ););signalsignal c_busc_bus : bit_vector (: bit_vector ( 11 toto 44 ););signal A, B, C, D : BIT;signal A, B, C, D : BIT;


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Record TypesRecord TypesRecord Types

typetype DATE DATE isis

recordrecord

YEAR : YEAR : INTEGER range INTEGER range 1900 1900 toto 1999 ;1999 ;

MONTH : MONTH : INTEGER range INTEGER range 1 1 toto 12 ;12 ;

DAY : DAY : INTEGER rangeINTEGER range 1 1 to to 31 ;31 ;

end record ;end record ;

signalsignal S : DATE;S : DATE;

var iablevar iable Y : Y : INTEGER range INTEGER range 1900 1900 to to 1999 ;1999 ;

Y := S.YEAR ;Y := S.YEAR ;


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STD_LOGIC Data TypesIEEE 1164-1993 Standard Logic Package

STD_LOGIC Data TypesSTD_LOGIC Data TypesIEEE 1164IEEE 1164--1993 Standard Logic Package1993 Standard Logic Package

type STD_ULOGIC is (type STD_ULOGIC is ('U''U' ---- UninitializedUninitialized'X''X' ---- Forcing UnknownForcing Unknown'0''0' ---- Forcing LowForcing Low'1''1' ---- Forcing HighForcing High'Z''Z' ---- High ImpedanceHigh Impedance'W''W' ---- Weak UnknownWeak Unknown'L''L' ---- Weak LowWeak Low'H''H' ---- Weak HighWeak High''--'' ---- Don't CareDon't Care) ;) ; Used in SynthesisUsed in Synthesis

UnresolvedData Type

UnresolvedUnresolvedData TypeData Type


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STD_LOGIC Data TypesIEEE 1164-1993 Standard Logic Package

STD_LOGIC Data TypesSTD_LOGIC Data TypesIEEE 1164IEEE 1164--1993 Standard Logic Package1993 Standard Logic Package

�� STD_LOGIC : Resolved (Resolution Function provided)STD_LOGIC : Resolved (Resolution Function provided)

�� STD_LOGIC_VECTORSTD_LOGIC_VECTOR

�� STD_ULOGIC_VECTORSTD_ULOGIC_VECTOR

library library ieeeieee;;useuse ieeeieee.std_logic_1164..std_logic_1164.allall ;;


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Also,Also,Also,

�� FILE : Useful for RAM Values or Stimuli FilesFILE : Useful for RAM Values or Stimuli Files

�� ACCESS : L ike " pointers" in High Level LanguagesACCESS : L ike " pointers" in High Level Languages

�� TEXT : FILE of STRING (TEXTIO package)TEXT : FILE of STRING (TEXTIO package)

�� LINE : access STRING (TEXTIO package)LINE : access STRING (TEXTIO package)


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SubtypesSubtypes

�� To Insure Valid AssignmentsTo Insure Valid Assignments

�� Inher it All Operators and Subprograms from the Parent Inher it All Operators and Subprograms from the Parent TypeType

subtypesubtype DIGIT DIGIT is INTEGERis INTEGER rangerange 0 0 toto 9;9;

Subsets of Other TypesSubsets of Other TypesSubsets of Other Types


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OperatorsOperators

LLOGIC OGIC OOPERATORPERATOR

RRELATIONAL ELATIONAL OOPERATORPERATOR

AADDING DDING OOPERATORPERATOR

SSIGNIGN

MMULTIPLYING ULTIPLYING OOPERATORPERATOR

MMISCELLANEOUS ISCELLANEOUS OOPERATORPERATOR

and , or ,and , or , nandnand , nor ,, nor , xorxor

= , /= , < , <= , > , >== , /= , < , <= , > , >=

+ , + , -- , &, &

+ , + , --

* , / , mod ,* , / , mod , remrem

**** ,, absabs , not, not

Six ClassesSix ClassesSix Classes

PPRECEDENCERECEDENCE OORDERRDER


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Operands (1)Operands (1)

�� LiteralsL iterals : : 'x' , " 1100" , 752 , B" 11001" , O" 277" , X" 4C"'x' , " 1100" , 752 , B" 11001" , O" 277" , X" 4C"

�� numer ic, character , enumeration, or str ingnumer ic, character , enumeration, or str ing

�� Identifiers :Identifiers :

�� star ts with (astar ts with (a--z) followed by letters, '_' , or digitsz) followed by letters, '_' , or digits

�� Not caseNot case--sensitivesensitive

�� Some are reserved wordsSome are reserved words

�� Indexed Names : Indexed Names : S (3) , DATA (ADDR)S (3) , DATA (ADDR)


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�� Slice Names : Slice Names : var iable var iable ORGORG : : BIT_VECTOR BIT_VECTOR (7(7 downtodownto 0)0)

�� Sequence of elements of an ar ray objectSequence of elements of an ar ray object

�� Aliases : Aliases : alias alias MSBMSB : : BITBIT is is ORGORG (7)(7)

�� New name for a par t of a range of an ar rayNew name for a par t of a range of an ar ray

�� AggregatesAggregates

�� Qualified ExpressionsQualified Expressions

�� Function CallsFunction Calls

�� Type ConversionsType Conversions


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�� S'LEFT S'LEFT : Index of the leftmost element of the data type: Index of the leftmost element of the data type

�� S'RIGHT S'RIGHT : Index of the r ightmost element of the data type: Index of the r ightmost element of the data type

�� S'HIGH S'HIGH : Index of the highest element of the data type: Index of the highest element of the data type

�� S'LOW S'LOW : Index of the lowest element of the data type: Index of the lowest element of the data type

�� S'RANGE S'RANGE : Index range of the data type: Index range of the data type

�� S'REVERSE_RANGE S'REVERSE_RANGE : Reverse index range: Reverse index range

�� S'LENGTH S'LENGTH : Number of elements of an ar ray: Number of elements of an ar ray

Attr ibutes NamesA Data Attached to VHDL Objects

Attr ibutes NamesAttr ibutes NamesA Data Attached to VHDL ObjectsA Data Attached to VHDL Objects


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�� S'EVENT S'EVENT : A change value at the current simulation time: A change value at the current simulation time

�� S'STABLE S'STABLE : No change value at the current simulation time: No change value at the current simulation time

ifif (CK = 0 (CK = 0 and not and not CKCK 'STABLE'STABLE))

�� ...... ......

Attr ibutes NamesA Data Attached to VHDL Signals

Attr ibutes NamesAttr ibutes NamesA Data Attached to VHDL SignalsA Data Attached to VHDL Signals

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