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Chapter 5. Metal Oxide SiliconField-Effect Transistors (MOSFETs)
Transistor • Three terminal device
• Voltage between two terminals to control current flow in third terminal
• Versatile for many applications– Amplification
– Memory
– Logic
– voltage controlled current source
– switch
• Two popular types: – Bipolar Junction Transistor (BJT): used in power amplifier
– MOSFET: used in integrated circuits
Enhancement-type NMOS transistor•p-type material as substrate (i.e., body)•n-type material chemically bonded on body at source and drain → source and drain are electrically indistinguishable•Equivalent to having two diodes back to back → current cannot flow between source and drain•Typical dimensions:
o L = 0.1 to 3 μm,o W = 0.2 to 100 μmo tox = 2 to 50 nm
pn junction pn junction
• Four terminals shown: Source (S), Gate (G), Drain (D) and Body (B).
• Body is typically grounded (along with one of the other three terminals) and does not play any role.
• Gate is electrically insulated from the body by Silicon Oxide (SiO2)
• With no external voltages applied, normally there is no current between S and D.
• When certain voltage is applied at G, current flows from D to S. → The gate voltage controls the flow of current.
• With S and D grounded, apply positive voltage to G (vGS > 0).• Because G is electrically insulated to the body, in the channel, the gate voltage
attracts electrons from the body.• A thin layer of “induced n-type channel is formed between S and D.• Across the induced n-type channel, there is no pn junction between S and D.• The thickness of the induced n-type channel is proportional to vGS.• Now, between S and D there is continuous n-type material.• In the n-type region, there are excess electrons floating around (i.e., drift current
flowing in random directions).
Channel region
• With vGS > 0, now apply small vDS > 0.• Then, (diffusion) current starts flowing from D to S. There is no
current flowing into G, because of SiO2 insulator. • To form an induced n-type channel sufficient to support current
flow, vGS > Vt. Vt is called the threshold voltage.
• For small vDS, iD is a linear function of vDS.
• The slope is the inverse of the resistance between D and S.
• When vGS < Vt, the resistance is infinite
• Increase vDS with fixed vGS > Vt
• Voltage between G and S = vGS • Voltage between G and D = vGS - vDS
• n-channel is thickest at S, and thinnest at D.• As vDS increases, the resistance across the channel increases.
• When vGS - vDS = Vt, the channel depth at D is ≈ 0.• Channel is then, “pinched off.”• Increasing vDS beyond the point vDS = vGS - Vt has no effect on iD.• This region is called the saturation. vDSsat = vGS - Vt
• Device in saturation: region vDS ≥ vDSsat
• Device in triode region: vDS < vDSsat
The above curves exist for each fixed value of vGS.
The PMOS transistor works similarly, but with n-type body and p-type S and D.
• To establish a p-type channel between S and D for the PMOS transistor vGS < Vt where Vt < 0.
• The current flows from S to D when vDS < 0.• PMOS is not used by itself very often.
Complementary MOS (CMOS) Transistor• Combines NMOS and PMOS on single substrate• Most popular transistor for integrated circuit • Very dense structure, consumes low power.• Very powerful and versatile
Circuit Symbols for NMOS
Most popular one to use
1
small
is the internal resistance between D and S in triode mode.
: transconductance parameter, : mobility of electron in channel
DS
GS GS
DSD n GS t DS DS n GS t
vDv V
DS
n n OX n
vW Wi k v V v r k v V
L i L
r
k C
2Common value: 1.0 mA/V and 1 V n t
Wk V
L
Triode Region• vGS ≥ Vt: channel is induces between S and D.
• vDS ≤ vGS - Vt: channel is continuous (i.e., no pinch off).
Saturation Region• vGS ≥ Vt: channel is induces between S and D.
• vDS ≥ vGS - Vt: channel is pinched off.
• At the boundary of triode and saturation: vDS = vGS - Vt
21
2 D n GS t
Wi k v V
L
iD - vGS relationship in saturation
Large Signal Circuit Model NMOS in Saturation
Voltage Characteristics for NMOS Transistor
More Accurate Model• In saturation, slope in iD – vDS curve is not entirely flat.
• There is internal resistance, ro.
211
2: process parameter
D n GS t DS
Wi k v V v
L
Large Signal Model for NMOS with ro
1 11
2
constant2
: internal resistance between D and S in saturation mode
GS
nDo n GS t GS t
DS v
o
ki W Wr k v V v V
v L L
r
Circuit Symbols for PMOS
Most popular one to use
Nominal Current Directions and Voltage Polarity
Triode Region• vGS ≤ Vt: channel is induces between S and D where Vt < 0.
• vDS ≥ vGS - Vt: channel is continuous (i.e., no pinch off) where vDS < 0.
2
Or more accurately,
11
2Note: , , , < 0
D p GS t DS
D p GS t DS
GS t DS
Wi k v V v
L
Wi k v V v
Lv V v
Voltage Characteristics for PMOS Transistor
Skip All Sections for PMOS.
MOSFET Circuit with DC Inputs
2n
Assume 0.
Want to design the circuit such that
0.4 mA and 0.5 V.
Find and .
Given: 0.7 V, 100 A/V
1 m, 32 m,
o
D D
S D
t n OX
r
I V
R R
V k C
L W
2
26 6
2
Note that 0. Want to design 0.5. Thus the
transistor is in saturation mode.
1
21 32
400 10 100 102 1
0.25
0.5 since in saturation mode.
1.2 V
G D
D n OX GS t
GS t
GS t
GS t GS t
GS
V V
WI C V V
L
V V
V V
V V V V
V
1.2 ( 2.5)= = 3.25 k
0.4
2.5 0.5= = 5 k
0.4
S SSS
D
DD DD
D
V VR
I
V VR
I
2n
Example:
Assume 0.
Want to design the circuit such that 80 A.
Find and .
Given: 0.6 V, 200 A/V
0.8 m, 4 m,
o
D
D
t n OX
r
I
R V
V k C
L W
2
26 6
2
Note that . Transistor in saturation mode.
1
21 4
80 10 200 102 0.8
0.16
0.4 since in saturation mode.
1.0 V
1.0 V
3 1 = =
0.08
D G
D n OX GS t
GS t
GS t
GS t GS t
GS
G D
DD D
D
V V
WI C V V
L
V V
V V
V V V V
V
V V
V VR
I25 k
2
Example:
Want to design the circuit such that 0.1 V.
Given: 1 V, 1 mA/V
D
t n
V
WV k
L
-3
Note that 0.1 5 1 4.
Transistor in triode mode.
= 0.4 10 for small
5 0.1 = = 1.225 k
0.4
0.1 = 0.25 k
0.4
DS GS t
D n GS t DS DS
DD DD
D
DSDS
D
V V V
WI k V V V V
LV V
RI
Vr
I
MOSFET as Amplifier• Utilize saturation mode.• iD as function of vGS. • Transconductance amplifier
Often, we want amplifiers to be linear. But iD is a quadratic function of vGS. Use DC biasing technique. Shift small signal around a point that mimics linearity.
Common source amplifier
Q1 is too close to cut-off and Q2 is too close to triode boundary. We want the quiescent point to be in the middle of saturation region. For example, Q3 may be a reasonable point.
Boundary with triode region
Q3•
Quiescent point is determined by VGS and RD.
For linear amplifier, MOS's are in saturation mode.
Desire to operate at a certain - characteristics
Determine point of interest
- Set DC current
Biasing MOS Amplifier Circuit
i v
Q
I
- Set DC voltage
- Make AC signal small around point
D
DSV
Q
2
,
Biasing Scenario 1: Fix
1
2, , , and vary in temperature and by manufacturing procedure.
becomes unpredictable by simply fixing only.
GS
D n OX GS t
n OX t
D GS
V
WI C V V
LC W L V
I V
Biasing Scenario 2: Fix and add resistor in S
if is large enough.
is mostly determined by and .
is called the degeneration resistance.
G
G GS S D G GS S
GG S D D D G S
S
S
V
V V R I V V R
VV R I I I V R
R
R
Practical Methods of Biasing VG
2
Example:
Goal: 0.5 mA
Given: 1 V
1 mA/V
0
15 V
D
t
n
DD
I
V
Wk
L
V
2
2
2
1Rule of Thumb:
310 V and 5 V
15 10 = = 10 k
0.5
5 = = 10 k
0.5
1
21
0.5 12
1
2 V
2 5 7 V
D SR R DS DD
D S
DD DD
D
SS
D
D n GS t
GS t
GS t
GS
G GS S
V V V V
V V
V VR
I
VR
I
WI k V V
L
V V
V V
V
V V V
1 2
To get 7 V, select
= 8 M and = 7 MG
G G
V
R R
Biasing Scenario 3: D-G resistor
(since 0.)
GS DS DD D D G
DD GS D D
V V V R I I
V V R I
Biasing Scenario 4: Current Source
Determine to establish point. I Q
D2
1
211
1
1
Implementation of current source using second MOS (Goal: Set )
1
2
For each , solve the two equations above to get and .
DD SS GSD
D n GS t
D GS
I
V V VI
RW
I k V VL
I R V
222
2
2 22
1 1 1
2 1
1
2
Since is the same for both transistors,
/
/
If two transistors are identical, .
D n GS t
GS
D
D
D D
WI k V V
L
V
W LI
I W L
I I
MOS is in saturation mode.
MOS has been properly biased.
- characteristics is linearly approximated around
certain point.
Now apply small AC signal around
Applying AC at Point
i v
Q
Q
point.
The resulting circuit is a linear system.
DC and AC inputs can be applied separately by
superposition.
Q
2
2
2 2
2
For DC:
1
2
For total signal:
1
21 1
2 2
If is kept small,
1
2
Transco
D n GS t
D DD D D
GS GS gs
D n GS gs t
n GS t n GS t gs n gs
gs
D n GS t n GS t gs
D D d
WI k V V
LV V I R
v V v
Wi k V v V
LW W W
k V V k V V v k vL L L
v
W Wi k V V k V V v
L Li I i
nductance for small signal:
dm n GS t
gs
i Wg k V V
v L
D DD D D
DD D D d
D D d
d D d m gs D
dv m D
gs
v V i R
V R I i
V R i
v R i g v R
vA g R
v
Small Signal (or AC) Equivalent Models
λ = 0 λ ≠ 0
gm and ro are determined for each Q point.For analyzing small signal circuits, DC sources must be eliminated.
• Voltage source: short circuit• Current source: open circuit
Three Different Ways to Get
1.
2. 2
23.
To achieve a desired value, use , , and .
m
m n GS t
m D n
Dm
GS t
m GS D
g
Wg k V V
L
Wg I k
L
Ig
V V
Wg V I
L
2Example: Given 1.5 V, 0.25 mA/V , and 50 V.
Note: 1. The capacitor at the input blocks any DC through it.
2. point is set entirely by , , and 15V power supply
t n A
D G
WV k V
L
Q R R
(i.e., ).
1 3. = .
4. In small signal analysis, replace capacitors by short circuits.
DD
A
V
V
Given circuit → Small signal model
2 2 21 1 10.25 1.5 0.25 1.5
2 2 2Note that 0, and
15 10
Solve the above two equation together for and .
=1.06 mA and 4.4 V
0.25 4.4 1.5
D n GS t GS D
G GS D
D DD D D D
D D
D D
m n GS t
WI k V V V V
LI V V
V V I R I
I V
I V
Wg k V V
L
0.725 mA/V
50= 47 k
1.06
Ao
D
Vr
I
D L o
|| ||
R || R || r
0.725 10 || 10 || 47
3.3 V/V
1
1 3.3
=4.3 0.4310
2.33 M
o m gs D L o
ov m
i
i o i oi
G G i
i
G
ii
iin
i
v g v R R r
vA g
v
v v v vi
R R v
v
R
vv
vR
i
i
G
v
R
Source transform
GR
Make large such that .iG m gs
G
vR g v
R
Alternative Small Signal Models (T Models)
Separate DC and AC analysis
Discrete resistors as load
In complex ICs, MOS's are used together to
act as loads, current sources, and voltage references
as
Single Stage MOS Amplifier Circuits
well as amplifiers.
There are several popular configurations for single
stage MOS amplifier.
Basic Structure
sig sig sig sig
Source: and ( and may be from a separate source
or represent the output of precedeing amplifier stage.)
Output: ( may be an ac
Chatersistics of MOS Amplifiers
L L
v R v R
R R
sig
sig
tual resistor or represent
an input resistance of the succeeding amplifier stage.)
Circuit (or and ) independent parameters: , , , ,
Circuit (or and ) dependent parameters
L i o vo is m
L
R R R R A A G
R R
sigout 0
: , , , , ,
, L
in out v i vo v
i in oR R
R R A A G G
R R R R
Original Circuit
Equivalent Circuits
1
Very widely used.
: Large bypass capacitor to
eliminate output
associated with source .
: Large coupling capacitor
to bl
Common Source (CS) Configuration
S
C
C
I
C
sig
2
ock DC value
associated with .
: Large coupling capacitor to
block DC value associated
with .
C
D
O o d
v
C
v
v v v
sig sigsig
sig sig
out
0 (if large)
|| ||
|| || ||
|| ||
||
Gg in G gs i G
G
o m gs o D L
v m o D L vo m o D
in inv v m o D L
in in
o D
Ri R R v v v v R
R R
v g v r R R
A g r R R A g r R
R RG A g r R R
R R R R
R r R
CS Variation: Source Resistor SR
sigsig
sig
1
1 11 1
|| ||
1 1 1
||
1
Gi
G
m i i m igs i d
m S m SS S
m m
m D L m D L m Do i v vo
m S m S m S
m D LGv
G m S
Rv v
R R
g v v g vv v i i
g R g RR R
g g
g R R g R R g Rv v A A
g R g R g R
g R RRG
R R g R
1 2
G: Ground S: Input D: Output
, : Large coupling capacitors
Common Gate (CG) Configuration
C CC C
sigsig
sig sig
i1
in
1
1 1 Note: is seen only through S, i.e., not though G or D.
1
|| ||
||
inm m
ini
in m
m i
d m i
o d d D L m D L i
v m D L vo m D
Rg g
vRv v
R R g R
vi g v
R
i i i g v
v v i R R g R R v
A g R R A g R
sig
||
1m D L
v out o Dm
g R RG R R R
g R
1 2
D: Ground G: Input S: Output
Also called the source follower configuration
, : Large coupling capacitors
Common Drain (CD) Configuration
C CC C
sig sig sigsig sig
sig
||
1 ||
||
1 1 ||
||
1 ||
1 ||
in Gin G i
in G
L oo i
L om
L o ov vo
L o om m
L oGv
GL o
m
out om
R RR R v v v v
R R R R
R rv v
R rg
R r rA A
R r rg g
R rRG
R R R rg
R rg
CMOS is widely used in digital
logic circuits.
Matched NMOS ( : Driver) and
PMOS ( : Load) as signle device.
Tens of millions of CMOS's
CMOS Digital Logic Inverter
N
P
Q
Q
can be
put in a single integrated chip (IC).
Logic 0: 0 V Logic 1:
I I DD
DP DN
v v V
I I
When (logic high input), on and off
Intersection point: in triode and off
is small. logic low output (i.e., inversion)
is very small. very low power consumption
1
I DD N P
N P
O DSN
DSNn
n
v V Q Q
Q Q
v v
i
rW
kL
(part of steep slope low resistence)
DD tnn
V V
When 0 (logic low input), off and on
Intersection point: in triode and off
logic high output (i.e., inversion)
is very small. very low power consumption
1 (pa
I N P
P N
O DD
DSPp
p DD tpp
v Q Q
Q Q
v V
i
rW
k V VL
rt of steep slope, low resistence)
Two output voltages: 0 and
Static power consumption 0
and can be made very small.
: Pull-up transistor : Pull-down transistor
Hig
Salient Characteristics of CMOS Inverter
DD
DSP DSN
P N
V
r r
Q Q
h current driving capability through and
High speed operation (short charge and discharge cycle)
0 Infinite input resistance
Can drive many other inverters.
P N
G
Q Q
I
- Characteristics with Matched and pnN P n p
n p
WWi v Q Q k k
L L
15 2
81
3 28
1 3 2
8
1 3 2
8
IH DD t
IL DD t
H OH IH
DD t
L IL OL
DD t
V V V
V V V
NM V V
V V
NM V V
V V
• Next stage amplifier may present certain capacitance C.• As a result of C, vO does not change instantly.
• Thus tPHL and tPLH are observed.
• For every on-off cycle, QN and QP each consumes power equaling 0.5CVDD
2 where C is internal capacitance of transistors.• Dynamic power dissipation PD = f CVDD
2 where f is the frequency of on-off cycle (i.e., clocking frequency)