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COMP541COMP541

Memories - IMemories - I

Montek SinghMontek Singh

Feb 25, 2010Feb 25, 2010

TopicsTopics Midterm TestMidterm Test

Thursday after Spring BreakThursday after Spring Break

Lab Preview: VGA character terminalLab Preview: VGA character terminal Overview of Memory TypesOverview of Memory Types

ROMs: PROMs, FLASH, etc.ROMs: PROMs, FLASH, etc. RAMsRAMs

Random-Access Memory (RAM)Random-Access Memory (RAM) Static todayStatic today Dynamic nextDynamic next

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Lab: VGA Display Driver Lab: VGA Display Driver ArchitectureArchitecture No frame bufferNo frame buffer Character terminalCharacter terminal

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Screen Character Memory

BitmapMemory

VGA Driver

Timing Generator

RGB

HSync

VSync

From/ToCPU

Valid, VSync, HSync

bitmaps by rows

Character MemoryCharacter Memory Dual portedDual ported

Memory mappedMemory mapped CPU writesCPU writes Could read alsoCould read also

How many characters?How many characters?

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ScreenCharacterMemory

BitmapMemory

VGA Driver

Timing Generator

RGB

HSync

VSync

ToCPU

Valid, VSync, HSync

bitmaps by rows

Bitmap MemoryBitmap Memory What bitmap size?What bitmap size?

5x7 at least5x7 at least

CodesCodeshttp://www.piclist.com/techref/datafile/charsets.htmhttp://www.piclist.com/techref/datafile/charset/8x8.ht

m

Indexed by character memoryIndexed by character memory So what code to store in character memory?So what code to store in character memory?

What size should memory be?What size should memory be?

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VGA driverVGA driver Just sends hsync, vsyncJust sends hsync, vsync Track current Track current

row/columnrow/column something the Timing something the Timing

Generator should provide Generator should provide the VGA Driverthe VGA Driver

Generates colorGenerates color When validWhen valid Maybe smaller than VGAMaybe smaller than VGA

What character code? What character code? ASCII?ASCII?

How many rows and How many rows and columns?columns?

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ScreenCharacterMemory

BitmapMemory

VGA Driver

Timing Generator

RGB

HSync

VSync

ToCPU

Valid, VSync, HSync

bitmaps by rows

PossibilitiesPossibilities Code color into some bits of character?Code color into some bits of character? Other possibilitiesOther possibilities

Sprites for games?Sprites for games?Your own NintendoYour own Nintendo

Ideas?Ideas?

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RAM on FPGARAM on FPGA Ours has 28 blocks, each 18Kb (bits, not bytes!)Ours has 28 blocks, each 18Kb (bits, not bytes!)

They call it They call it block RAMblock RAM Block RAM: One or two ports, and several possible layoutsBlock RAM: One or two ports, and several possible layouts Often you’ll use it as a 16Kb RAM moduleOften you’ll use it as a 16Kb RAM module

Using from VerilogUsing from Verilog It’s a primitiveIt’s a primitive Instantiate a block (here called R1)Instantiate a block (here called R1)

RAMB16_S1 R1(RAMB16_S1 R1( .DO(out), // 1-bit Data Output.DO(out), // 1-bit Data Output .ADDR(addr), // 14-bit Address Input.ADDR(addr), // 14-bit Address Input .CLK(clk), // Clock.CLK(clk), // Clock .DI(in), // 1-bit Data Input.DI(in), // 1-bit Data Input .EN(ena), // RAM Enable Input.EN(ena), // RAM Enable Input .SSR(1’b0), // Synchronous Set/Reset Input.SSR(1’b0), // Synchronous Set/Reset Input .WE(we) // Write Enable Input.WE(we) // Write Enable Input ););

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4-Wide Block4-Wide BlockRAMB16_S4 RAMB16_S4_inst (RAMB16_S4 RAMB16_S4_inst (

.DO(DO), // 4-bit Data Output.DO(DO), // 4-bit Data Output

.ADDR(ADDR), // 12-bit Address Input.ADDR(ADDR), // 12-bit Address Input

.CLK(CLK), // Clock.CLK(CLK), // Clock

.DI(DI), // 4-bit Data Input.DI(DI), // 4-bit Data Input

.EN(EN), // RAM Enable Input.EN(EN), // RAM Enable Input

.SSR(SSR), // Synchronous Set/Reset Input.SSR(SSR), // Synchronous Set/Reset Input

.WE(WE) // Write Enable Input.WE(WE) // Write Enable Input

););

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Wider Have ParityWider Have ParityRAMB16_S18 RAMB16_S18_inst (RAMB16_S18 RAMB16_S18_inst (

.DO(DO), // 16-bit Data Output.DO(DO), // 16-bit Data Output

.DOP(DOP), // 2-bit parity Output.DOP(DOP), // 2-bit parity Output

.ADDR(ADDR), // 10-bit Address Input.ADDR(ADDR), // 10-bit Address Input

.CLK(CLK), // Clock.CLK(CLK), // Clock

.DI(DI), // 16-bit Data Input.DI(DI), // 16-bit Data Input

.DIP(DIP), // 2-bit parity Input.DIP(DIP), // 2-bit parity Input

.EN(EN), // RAM Enable Input.EN(EN), // RAM Enable Input

.SSR(SSR), // Synchronous Set/Reset Input.SSR(SSR), // Synchronous Set/Reset Input

.WE(WE) // Write Enable Input.WE(WE) // Write Enable Input

););

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Can Initialize Block RAMCan Initialize Block RAM RAMB16_S1 #(RAMB16_S1 #(

.INIT(1'b0), // Value of output RAM registers at startup.INIT(1'b0), // Value of output RAM registers at startup

.SRVAL(1'b0), // Output value upon SSR assertion.SRVAL(1'b0), // Output value upon SSR assertion

.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE.WRITE_MODE("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE

// The following INIT_xx declarations specify the initial contents of the RAM// The following INIT_xx declarations specify the initial contents of the RAM

// Address 0 to 4095// Address 0 to 4095

.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000F1F),.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000F1F),

.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000), .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),

…… .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),

.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000).INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000)

) RAMB16_S1_inst () RAMB16_S1_inst (

.DO(data), // 1-bit Data Output.DO(data), // 1-bit Data Output

.ADDR(addr), // 14-bit Address Input.ADDR(addr), // 14-bit Address Input

.CLK(clk), // Clock.CLK(clk), // Clock

.DI(DI), // 1-bit Data Input.DI(DI), // 1-bit Data Input

.EN(EN), // RAM Enable Input.EN(EN), // RAM Enable Input

.SSR(SSR), // Synchronous Set/Reset Input.SSR(SSR), // Synchronous Set/Reset Input

.WE(WE) // Write Enable Input.WE(WE) // Write Enable Input

););

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Note that addresses go right to left,top to bottom

Synthesizer Can Also InferSynthesizer Can Also Infer Careful how you specify (see XST manual).Careful how you specify (see XST manual).

module inferRAM(clk, addr, data, we);module inferRAM(clk, addr, data, we);input clk;input clk;input [8:0] addr;input [8:0] addr;// 512 locations// 512 locationsoutput [7:0] data;output [7:0] data; // by 8 bits// by 8 bitsinput we;input we;

reg [7:0] mem [511:0];reg [7:0] mem [511:0];reg [8:0] ra;reg [8:0] ra;

always @ (posedge clk)always @ (posedge clk)beginbegin

if(we)if(we)mem[addr] <= data;mem[addr] <= data;

ra <= addr;ra <= addr;endendassign data = mem[ra];assign data = mem[ra];

endmoduleendmodule

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Look at Test CodeLook at Test Code RAM testing exampleRAM testing example

I’ll post online for tomorrow’s labI’ll post online for tomorrow’s lab

Note how memory values are specifiedNote how memory values are specified Addresses go Addresses go right-to-leftright-to-left, top-to-bottom, top-to-bottom See the See the Constraints GuideConstraints Guide and and LibraryLibrary manuals in manuals in

Xilinx docsXilinx docs

Today’s lectureToday’s lecture

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Types of MemoryTypes of Memory Many dimensionsMany dimensions

Read Only vs Read/Write (or write seldom)Read Only vs Read/Write (or write seldom) Volatile vs Non-VolatileVolatile vs Non-Volatile Requires refresh or notRequires refresh or not

Look at ROM first to examine interfaceLook at ROM first to examine interface

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Non-Volatile Memory Non-Volatile Memory TechnologiesTechnologies Mask (old)Mask (old) Fuses (old)Fuses (old) Electrically erasableElectrically erasable

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Details of ROMDetails of ROM Memory that is permanentMemory that is permanent k address linesk address lines 22kk items items n bitsn bits

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Notional View of InternalsNotional View of Internals

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Programmed Truth TableProgrammed Truth Table

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Resulting ProgrammingResulting Programming

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In truth, they’re laid out in 2D (row, col)In truth, they’re laid out in 2D (row, col)

Mask ROMsMask ROMs Oldest technologyOldest technology Originally “mask” used as last step in Originally “mask” used as last step in

manufacturingmanufacturing Specify metal layer (connections)Specify metal layer (connections) Used for volume applicationsUsed for volume applications Long turnaroundLong turnaround Used for applications such as embedded systems and, Used for applications such as embedded systems and,

in the old days, boot ROMin the old days, boot ROM

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Programmable ROM (PROM)Programmable ROM (PROM) First ones had fusible linksFirst ones had fusible links High voltage would blow out linksHigh voltage would blow out links Fast to programFast to program Single useSingle use

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UV EPROMUV EPROM ErasableErasable PROM PROM Common technologies used UV light to erase Common technologies used UV light to erase

complete devicecomplete device Took about 10 minutesTook about 10 minutes

Holds state as charge in very well insulated Holds state as charge in very well insulated areas of the chipareas of the chip

Nonvolatile for several (10?) yearsNonvolatile for several (10?) years

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EEPROMEEPROM Electrically ErasableElectrically Erasable PROM PROM Similar technology to UV EPROMSimilar technology to UV EPROM Erased in blocks by higher voltageErased in blocks by higher voltage Programming is slower than readingProgramming is slower than reading Some called Some called flash memoryflash memory

Digital cameras, MP3 players, BIOSDigital cameras, MP3 players, BIOS Limited lifeLimited life Some support individual word write, some blockSome support individual word write, some block One on Xess board has 5 blocksOne on Xess board has 5 blocks Has a Has a boot blockboot block that is carefully protected that is carefully protected

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How Flash WorksHow Flash Works Special transistor with floating gateSpecial transistor with floating gate This is part of device surrounded by insulationThis is part of device surrounded by insulation

So charge placed there can stay for yearsSo charge placed there can stay for years Aside: some newer devices store multiple bits of info Aside: some newer devices store multiple bits of info

in a cellin a cell

Interested in this? If so, we can cover in more Interested in this? If so, we can cover in more detail w/ transistorsdetail w/ transistors

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Read/Write MemoriesRead/Write Memories Flash is obviously writeableFlash is obviously writeable

But not meant to be written rapidly (say at But not meant to be written rapidly (say at CPU rates)CPU rates) And often by blocks (disk replacement)And often by blocks (disk replacement)

On to RAMOn to RAM

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Random Access MemoriesRandom Access Memories So called because it takes same amount of So called because it takes same amount of

time to address any particular locationtime to address any particular location Not quite true for modern DRAMsNot quite true for modern DRAMs

First look at asynchronous static RAMFirst look at asynchronous static RAM Ones on Xilinx chip synchronousOnes on Xilinx chip synchronous

Data available at clock edges, like registersData available at clock edges, like registers One on board can be bothOne on board can be both

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Simple View of RAMSimple View of RAM Of some word size Of some word size nn Some capacity 2Some capacity 2kk

k bits of address linek bits of address line Maybe have read lineMaybe have read line

Strictly speaking may not needStrictly speaking may not need

Have a write lineHave a write line

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1K x 16 memory1K x 16 memory Variety of sizesVariety of sizes

From 1-bit wideFrom 1-bit wide

Issue is no. of pinsIssue is no. of pins

Memory size often specified Memory size often specified in bytesin bytes This would be 2KB memoryThis would be 2KB memory

10 address lines and 16 10 address lines and 16 data linesdata lines

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WritingWriting Sequence of stepsSequence of steps

Setup address linesSetup address lines Setup data linesSetup data lines Activate write line (maybe a pos edge)Activate write line (maybe a pos edge)

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ReadingReading StepsSteps

Setup address linesSetup address lines Activate read lineActivate read line Data available after specified amt of timeData available after specified amt of time

For asyncFor asyncSynchronous memories use a clockSynchronous memories use a clock

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Chip SelectChip Select Usually a line to Usually a line to enableenable the chip the chip Why?Why?

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WritingWriting

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ReadingReading

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Static vs Dynamic RAMStatic vs Dynamic RAM SRAM vs DRAMSRAM vs DRAM DRAM stores charge in capacitorDRAM stores charge in capacitor

Disappears after short period of timeDisappears after short period of time Must be refreshedMust be refreshed

SRAM easier to useSRAM easier to use Uses transistors (think of it as latch)Uses transistors (think of it as latch) FasterFaster More expensive per bitMore expensive per bit Smaller sizesSmaller sizes

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Structure of SRAMStructure of SRAM Control logicControl logic One memory One memory cell cell per bitper bit

Cell consists of one or more transistorsCell consists of one or more transistors Not really a latch made of NANDs/NORs, but logically Not really a latch made of NANDs/NORs, but logically

equivalentequivalent

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Simple OrganizationSimple Organization In reality, more complexIn reality, more complex Note that only one wordline H at a timeNote that only one wordline H at a time

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wordline311

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2:4Decoder

Address

01

00

storedbit = 0

wordline2

wordline1

wordline0

storedbit = 1

storedbit = 0

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

storedbit = 0

storedbit = 0

storedbit = 1

storedbit = 1

bitline2 bitline1 bitline0

Data2 Data1 Data0

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Bit SliceBit Slice Cells connected to form 1 Cells connected to form 1

bit positionbit position Word Select gates one Word Select gates one

latch from address lineslatch from address lines Note it selects Reads alsoNote it selects Reads also B (and B’) set by R/W, B (and B’) set by R/W,

Data In and BitSelectData In and BitSelect Funny thing here when Funny thing here when

you write. What is it?you write. What is it?

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Bit CellsBit Cells

stored bit

wordline

bitline

Example:

stored bit = 0

wordline = 1

stored bit = 1

stored bit = 0

stored bit = 1

bitline =

(a) (b)

wordline = 1

wordline = 0

wordline = 0

bitline =

bitline =

bitline =0

1

Z

Z

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Bit Slice can Become ModuleBit Slice can Become Module Basically bit slice is a X1 Basically bit slice is a X1

memorymemory NextNext

SRAM Bit CellSRAM Bit Cell

stored bit

wordline

bitline

wordline

bitline bitline

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16 X 1 RAM “Chip”16 X 1 RAM “Chip”

Now shows Now shows decoderdecoder

Row/ColumnRow/Column If RAM gets large, there is a large decoderIf RAM gets large, there is a large decoder Also run into chip layout issuesAlso run into chip layout issues Larger memories usually “2D” in a matrix Larger memories usually “2D” in a matrix

layoutlayout Next SlideNext Slide

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16 X 1 RAM as 4 X 4 Array16 X 1 RAM as 4 X 4 Array

Two decodersTwo decoders RowRow ColumnColumn

Address just Address just broken upbroken up

Not visible Not visible from outside from outside on SRAMson SRAMs

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Change to 8 X 2 RAMChange to 8 X 2 RAM Minor change in Minor change in

logiclogic Also pinoutsAlso pinouts What’s different?What’s different?

Realistic SizesRealistic Sizes Imagine 256K memory as 32K X 8Imagine 256K memory as 32K X 8 One column layout would need 15-bit decoder One column layout would need 15-bit decoder

with 32K outputs!with 32K outputs! Can make a square layout with 9-bit row and Can make a square layout with 9-bit row and

6-bit column decoders6-bit column decoders

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SRAM PerformanceSRAM Performance Current ones have cycle times in low Current ones have cycle times in low

nanoseconds (say 2.5ns)nanoseconds (say 2.5ns) Used as cache (typically on-chip or off-chip Used as cache (typically on-chip or off-chip

secondary cache)secondary cache) Sizes up to 8Mbit or so for fast chipsSizes up to 8Mbit or so for fast chips

SRAMs also common for low powerSRAMs also common for low power

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Wider MemoryWider Memory What if you don’t have What if you don’t have

enough bit width?enough bit width?

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Larger/Wider MemoriesLarger/Wider Memories Made up from sets of Made up from sets of

chipschips Consider a 64K by 8 Consider a 64K by 8

RAMRAM

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LargerLarger 256K X 8256K X 8 Decoder for high-Decoder for high-

order 2 bitsorder 2 bits Selects chipSelects chip Look at selection logicLook at selection logic Address rangesAddress ranges

Tri-state outputsTri-state outputs

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Deeper MemoryDeeper Memory Adding chips to increase Adding chips to increase

storage, but keep same storage, but keep same widthwidth

Need decoderNeed decoder

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TodayToday Fast look at non-volatile memoryFast look at non-volatile memory Static RAMStatic RAM Next: Dynamic RAMNext: Dynamic RAM

Complex, largest, cheapComplex, largest, cheap Much more design effort to useMuch more design effort to use

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