1

DLD

Lecture 19Recap II

2

Recap

° Number System/Inter-conversion, Complements

° Boolean Algebra

° More Logic Functions: NAND, NOR, XOR

° Minimization with Karnaugh Maps

° More Karnaugh Maps and Don’t Cares

° NAND and XOR Implementations

° Circuit Analysis and Design Procedures

° Binary Adders and Subtractors

° Magnitude Comparators and Multiplexers

° Encoders, Decoders and DeMultiplexers

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Boolean Algebra

° Formal logic: In formal logic, a statement (proposition) is a declarative sentence that is either

true(1) or false (0).

° It is easier to communicate with computers using formal logic.

° Boolean variable: Takes only two values – either true (1) or false (0).

They are used as basic units of formal logic.

4

Venn Diagrams

4

A BA

BA

A B

BA

A B

BA

A B

BA

A B

BA

A

A

A

5

Boolean Algebra

° Boolean Algebra is a mathematical technique that provides the ability to algebraically simplify logic expressions. These simplified expressions will result in a logic circuit that is equivalent to the original circuit, yet requires fewer gates.

A

B

C

B+AC

A

BC AB+A(B+C)+B(B+C)

6

Logical Operations

° The three basic logical operations are:• AND

• OR

• NOT

° AND is denoted by a dot (·).

° OR is denoted by a plus (+).

° NOT is denoted by an overbar ( ¯ ), a single quote mark (') after, or (~) before the variable.

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X X 9)

1 X X 8)

X X X 7)

1 1 X 6)

X 0 X 5)

0 X X 4)

X X X 3)

X 1 X 2)

0 0 X 1)

Y X Y X 14B)

Y X YX 14A)

YXYXX 13D)

YXYXX 13C)

YXXYX 13B)

YXYXX 13A)

YZYWXZXWZWYX 12B)

XZXYZYX 12A)

ZYXZY X 11B)

ZXYYZX 11A)

X Y Y X 10B)

X Y Y X 10A)

Commutativ

e Law

Associative Law

Distributive Law

Consensus Theorem

Boolean & DeMorgan’s Theorems

DeMorgan’s

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Representation Conversion

° Need to transition between boolean expression, truth table, and circuit (symbols).

° Converting between truth table and expression is easy.

° Converting between expression and circuit is easy.

° More difficult to convert to truth table.

TruthTable

Circuit BooleanExpression

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10

The NAND Gate

° This is a NAND gate. It is a combination of an AND gate followed by an inverter. Its truth table shows this…

° NAND gates have several interesting properties…• NAND(a,a)=(aa)’ = a’ = NOT(a)

• NAND’(a,b)=(ab)’’ = ab = AND(a,b)

• NAND(a’,b’)=(a’b’)’ = a+b = OR(a,b)A B Y

0 0 1

0 1 1

1 0 1

1 1 0

AB

Y

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The NAND Gate

° These three properties show that a NAND gate with both of its inputs driven by the same signal is equivalent to a NOT gate

° A NAND gate whose output is complemented is equivalent to an AND gate, and a NAND gate with complemented inputs acts as an OR gate.

° Therefore, we can use a NAND gate to implement all three of the elementary operators (AND,OR,NOT).

° Therefore, ANY switching function can be constructed using only NAND gates. Such a gate is said to be primitive or functionally complete.

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AY

A

B

Y

YAB

NOT GateAND Gate

OR Gate

NAND Gates into Other Gates

(what are these circuits?)

13

Cascaded NAND Gates

3-input NAND gate

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NAND Gate and Laws

15

The NOR Gate

° This is a NOR gate. It is a combination of an OR gate followed by an inverter. It’s truth table shows this…

° NOR gates also have several

interesting properties…• NOR(a,a)=(a+a)’ = a’ = NOT(a)

• NOR’(a,b)=(a+b)’’ = a+b = OR(a,b)

• NOR(a’,b’)=(a’+b’)’ = ab = AND(a,b)

A B Y

0 0 1

0 1 0

1 0 0

1 1 0

AB

Y

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Functionally Complete Gates

° Just like the NAND gate, the NOR gate is functionally complete…any logic function can be implemented using just NOR gates.

° Both NAND and NOR gates are very valuable as any design can be realized using either one.

° It is easier to build an IC chip using all NAND or NOR gates than to combine AND,OR, and NOT gates.

° NAND/NOR gates are typically faster at switching and cheaper to produce.

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NOT Gate

OR Gate

AND Gate

NOR Gates into Other Gates

(what are these circuits?)A

Y

YAB

A

B

Y

18

NOR Gate and Laws

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The XOR Gate (Exclusive-OR)

° This is a XOR gate.

° XOR gates assert their output

when exactly one of the inputs

is asserted, hence the name.

° The switching algebra symbol

for this operation is , i.e.

1 1 = 0 and 1 0 = 1.

° Output is high when either A or B is high but not the both

A B Y

0 0 0

0 1 1

1 0 1

1 1 0

AB

Y

20

The XNOR Gate

° This is a XNOR gate.

° This functions as an

exclusive-NOR gate, or

simply the complement of

the XOR gate.

° The switching algebra symbol

for this operation is , i.e.

1 1 = 1 and 1 0 = 0.

A B Y

0 0 1

0 1 0

1 0 0

1 1 1

AB

Y

21

22

K-Maps

Ex: How do you transform a K-map into a truth table? Is it unique? How do you transform a K-map into an n-cube? Is it unique?

Two- and Three-Variable Maps

Application of Karnaugh Maps: The One-bit Adder

Adder

Cin

Cout

SB

A

A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

+

S = A’B’Cin + A’BCin’ + A’BCin + ABCin

Cout = A’BCin + A B’Cin + ABCin’ + ABCin

= A’BCin + ABCin + AB’Cin + ABCin + ABCin’ + ABCin

= BCin + ACin + AB

= (A’ + A)BCin + (B’ + B)ACin + (Cin’ + Cin)AB

= 1·BCin + 1· ACin + 1· AB

How to use a KarnaughMap instead of the

Algebraic simplification?

Application of Karnaugh Maps: The One-bit Adder

Adder

Cin

Cout

SB

A

A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

+

Karnaugh Map for Cout

Now we have to cover all the 1s in theKarnaugh Map using the largestrectangles and as few rectanglesas we can.

A

B

Cin

0

0

0

1 1 1

01

A

B

Cin

Application of Karnaugh Maps: The One-bit Adder

Adder

Cin

Cout

SB

A

A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

+

0

0

0 01

1 1 1

Karnaugh Map for Cout

Now we have to cover all the 1s in theKarnaugh Map using the largestrectangles and as few rectanglesas we can.

Cout = ACin

A

B

Cin

Application of Karnaugh Maps: The One-bit Adder

Adder

Cin

Cout

SB

A

A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

+

0

0

0 01

1 1 1

Karnaugh Map for Cout

Now we have to cover all the 1s in theKarnaugh Map using the largestrectangles and as few rectanglesas we can.

Cout = Acin + AB

A

B

Cin

Application of Karnaugh Maps: The One-bit Adder

Adder

Cin

Cout

SB

A

A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

+

0

0

0 01

1 1 1

Karnaugh Map for Cout

Now we have to cover all the 1s in theKarnaugh Map using the largestrectangles and as few rectanglesas we can.

Cout = ACin + AB + BCin

A

B

Cin

Application of Karnaugh Maps: The One-bit Adder

Adder

Cin

Cout

SB

A

A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

+

0

1

1 10

0 1 0

Karnaugh Map for S

S = A’BCin’

A

B

Cin

Application of Karnaugh Maps: The One-bit Adder

Adder

Cin

Cout

SB

A

A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

+

0

1

1 10

0 1 0

Karnaugh Map for S

S = A’BCin’ + A’B’Cin

A

B

Cin

Application of Karnaugh Maps: The One-bit Adder

Adder

Cin

Cout

SB

A

A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

+

0

1

1 10

0 1 0

Karnaugh Map for S

S = A’BCin’ + A’B’Cin + ABCin

A

B

Cin

Application of Karnaugh Maps: The One-bit Adder

Adder

Cin

Cout

SB

A

A B Cin S Cout0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

+

0

1

1 10

0 1 0

Karnaugh Map for S

S = A’BCin’ + A’B’Cin + ABCin + AB’Cin’

No Possible Reduction!

Can you draw the circuit diagrams?

Karnaugh Maps for Four Input Functions

° Represent functions of 4 inputs with 16 minterms

° Use same rules developed for 3-input functions

° Note bracketed sections shown in example.

C + B’D ’

Solution set can be considered as a coordinate System!

Karnaugh map: 4-variable example

° F(A,B,C,D) = m(0,2,3,5,6,7,8,10,11,14,15)

F =

D

A

B

A

B

CD

0000

1111

1000

01111 0

0 1

0 1

0 0

1 1

1 1

1 1

1 1C

+ A’BD

Don’t cares

° In digital systems it often happens that certain input conditions can never occur.

For example, suppose that x1 and x2 control two interlocked switches such that both switches cannot be closed at the same time. Thus the only three possible states of the switches are that both switches are open or that one switch is open and the other switch is closed.

Namely, the input valuations (x1, x2) = 00, 01, and 10 are possible, but 11 is guaranteed not to occur.

Then we say that (x1, x2) = 11 is a don’t-care condition , meaning that a circuit with x1 and x2 as inputs can be designed by ignoring this condition.

° A function that has don’t-care condition(s) is said to be incompletely specified.

Karnaugh maps: Don’t cares

° In some cases, outputs are undefined

° We “don’t care” if the logic produces a 0 or a 1

° This knowledge can be used to simplify functions.

0 0

1 1

X 0

X 1D

A

1 1

0 X

0 0

0 0

B

C

CDAB

00

01

11

10

00 01 11 10

- Treat X’s like either 1’s or 0’s- Very useful- OK to leave some X’s uncovered

+ C’D

Karnaugh maps: Don’t cares

° f(A,B,C,D) = m(1,3,5,7,9) + d(6,12,13)• without don't cares

- f =

0 0

1 1

X 0

X 1D

A

1 1

0 X

0 0

0 0

B

C

A ’D

CDAB

00

01

11

10

00 01 11 10

C f0 00 11 01 10 00 11 X100110011

D0101010101010101

10100XX00

A0000000011111111

+

B0000111100001111

+

Don’t Care Conditions

° In some situations, we don’t care about the value of a function for certain combinations of the variables.• these combinations may be impossible in certain contexts

• or the value of the function may not matter in when the combinations occur

° In such situations we say the function is incompletely specified and there are multiple (completely specified) logic functions that can be used in the design.• so we can select a function that gives the simplest circuit

° When constructing the terms in the simplification procedure, we can choose to either cover or not cover the don’t care conditions.

Map Simplification with Don’t Cares

F=ACD+B+AC0

AB

x x1

00 01

00

01

CD

0x 1

011 10

1x 0

111

1011 1

x

0AB

x x1

00 01

00

01

CD

0x 1

011 10

1x 0

111

1011 1

xF=ABCD+ABC+BC+AC

° Alternative covering.

Karnaugh maps: don’t cares (cont’d)

° f(A,B,C,D) = m(1,3,5,7,9) + d(6,12,13)• f = A'D + B'C'D without don't cares

• f = with don't cares

don't cares can be treated as1s or 0s

depending on which is more advantageous

0 0

1 1

X 0

X 1D

A

1 1

0 X

0 0

0 0

B

C

A'D

by using don't care as a "1"a 2-cube can be formed rather than a 1-cube to coverthis node

+ C'D

Some You Group, Some You Don’t

V

X 0

1 0

0 0

X 0

C C

B A

B A

BA

BA

C A

This don’t care condition was treated as a (1). This allowed the grouping of a single one to become a grouping of two, resulting in a simpler term.

There was no advantage in treating this don’t care condition as a (1), thus it was treated as a (0) and not grouped.

NAND-NAND & NOR-NOR Networks

DeMorgan’s Law:

(a + b)’ = a’ b’ (a b)’ = a’ + b’

a + b = (a’ b’)’ (a b) = (a’ + b’)’

push bubbles or introduce in pairs or remove pairs.

= =

==

NAND-NAND & NOR-NOR Networks

= =

==

NAND-NAND Networks

° Mapping from AND/OR to NAND/NAND

ab

cd

a) b)

c) d)

NAND-NAND Networks

Implementations of Two-level Logic

° Sum-of-products• AND gates to form product terms

(minterms)

• OR gate to form sum

° Product-of-sums• OR gates to form sum terms

(maxterms)

• AND gates to form product

Two-level Logic using NAND Gates

° Replace minterm AND gates with NAND gates

° Place compensating inversion at inputs of OR gate

Two-level Logic using NAND Gates (cont’d)

° OR gate with inverted inputs is a NAND gate• de Morgan's: A' + B' = (A • B)'

° Two-level NAND-NAND network• Inverted inputs are not counted

• In a typical circuit, inversion is done once and signal distributed

Two-level Logic using NAND Gates (cont’d)

Conversion Between Forms

° Convert from networks of ANDs and ORs to networks of NANDs and NORs

• Introduce appropriate inversions ("bubbles")

° Each introduced "bubble" must be matched by a corresponding "bubble"

• Conservation of inversions

• Do not alter logic function

° Example: AND/OR to NAND/NAND

A

B

C

D

Z

A

B

C

D

Z

NAND

NAND

NAND

Z = [ (A • B)' • (C • D)' ]'

= [ (A' + B') • (C' + D') ]'

= [ (A' + B')' + (C' + D')' ]

= (A • B) + (C • D)

Conversion Between Forms (cont’d)

° Example: verify equivalence of two forms

A

B

C

D

Z

A

B

C

D

Z

NAND

NAND

NAND

Conversion to NAND Gates

° Start with SOP (Sum of Products)• circle 1s in K-maps

° Find network of OR and AND gates

ABC

DE

FG

X

Multi-level Logic

° x = A D F + A E F + B D F + B E F + C D F + C E F + G• Reduced sum-of-products form – already simplified

• 6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!)

• 25 wires (19 literals plus 6 internal wires)

° x = (A + B + C) (D + E) F + G• Factored form – not written as two-level S-o-P

• 1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate

• 10 wires (7 literals plus 3 internal wires)

Level 1 Level 2 Level 3 Level 4

originalAND-OR network

A

CD

B

BC ’

F

introduction andconservation of

bubblesA

CD

B

BC ’

F

redrawn in termsof conventional

NAND gates A

CD

B ’

BC ’

F

Conversion of Multi-level Logic to NAND Gates° F = A (B + C D) + B C'

A

XBCD

F(a)

Original circuit

A

XBC

D

F(b)

Add double bubbles at inputs

D ’

A

X ’

BC

F(c)

Distribute bubblessome mismatches

D ’

AX

BC

FX ’

(d)

Insert inverters to fix mismatches

Conversion Between Forms

° Example

Making NAND circuits (Ex)° The easiest way to make a NAND circuit is to start with

a regular, primitive gate-based diagram.

° Two-level circuits are trivial to convert, so here is a slightly more complex random example.

Converting to a NAND° Step 1: Convert all AND gates to NAND gates and

convert all OR gates to NAND gates.

AND

AND

AND

AND

OR

OR

Logic Circuit Analysis

Analysis:

Determining the behavior of a system given its description.

The description of the system is often provided

in the form of a circuit diagram.

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Circuit Analysis Summary

° After finding the circuit inputs and outputs, you can come up with either an expression or a truth table to describe what the circuit does

° You can easily convert between expressions and truth tables

° The analysis and synthesis tools presented are sometimes based on the fundamental concepts of Boolean algebra

Find the circuit’sinputs and outputs

Find a Booleanexpression

for the circuit

Find a truth tablefor the circuit

Digital Design Overview

° Design digital circuit from specification

° Digital inputs and outputs known• Need to determine logic that can transform data

° Start in truth table form

° Create K-map for each output based on function of inputs

° Determine minimized sum-of-product representation

° Draw circuit diagram

Design Procedure (Mano)

Design a circuit from a specification.

1. Determine number of required inputs and outputs.

2. Derive truth table

3. Obtain simplified Boolean functions

4. Draw logic diagram and verify correctnessA00001111

B00110011

C01010101

R00000001

S01111111

S = A + B + CR = ABC

Analysis versus Design

° Design of a circuit starts with specification and ends up with a logic diagram.

° Analysis for a combinational circuit consists of determining the function that the circuit implements with:

A set of Boolean functions orA truth table, together with a possible

explanation of the operation of the circuit.We can perform the analysis by manually

finding the Boolean equations or truth table.

oThe first step in the analysis is to make sure that the given circuit is combinational and not sequential (i.e. no feedback or storage elements).

Half Adder

C A B S 0 0 0 1 A 0 B 0

S 0

C 1

0 0 0 00 1 1 01 0 1 01 1 0 1

Dec Binary 1 1+1 +1 2 10

Add two binary numbers• A0 , B0 -> single bit inputs

• S0 -> single bit sum

• C1 -> carry out

Multiple-bit Addition

A3 A2 A1 A0

0 1 0 1A 0 1 1 1B3 B2 B1 B0

B

0 1 0 10 1 1 1

A

B

0

1

0

1

1

1

1

Ai

+Bi

Ci

Si

Ci+1

Consider single-bit adder for each bit position.

Each bit position creates a sum and carry

Full Adder

A

B

S

C

C i+1

i

i

i

i

Si = Ci (Ai Bi)

Half-adder Half-adder

Ci+1 = AiBi + Ci(Ai Bi)

Full adder made of several half adders

Full Adder

half-adder

half-adderA

B

i

i

C i

C i+1

S i

S

C

C

A full adder can be made fromtwo half adders (plus an OR gate).

Hardware repetition simplifies hardware design

Full Adder

Full Adder

A B

C C

S

i i

i+1 i

i

Block Diagram

Putting it all together • Single-bit full adder

• Common piece of computer hardware

4-Bit Adder

Full Adder

A B

0 C

S

0 0

1

0

Full Adder

A B

C

S

1 1

2

1

Full Adder

A B

C

S

2 2

3

2

Full Adder

A B

C S

3 3

4 3

C 1 1 1 0A 0 1 0 1B 0 1 1 1S 1 1 0 0

Chain single-bit adders together.What does this do to delay?

Negative Numbers – 2’s Complement.

110 = 0116 = 00000001-110 = FF16 = 11111111

12810 = 8016 = 10000000-12810 = 8016 = 10000000

Subtracting a number is the same as:1. Perform 2’s complement

2. Perform addition

If we can augment adder with 2’s complement hardware?

4-bit Subtractor: E = 1

Full Adder

A B

C

0 0

1

0

Full Adder

A B

C

1 1

2

1

Full Adder

A B

C

2 2

3

2

Full Adder

A B

C SD

3 3

4 3 SD SD SD

E

+1

Add A to B ’ (one’s complement) plus 1

That is, add A to two’s complement of BD = A - B

Adder- Subtractor Circuit

Designing Comparators Functionally

Magnitude Comparator

° The comparison of two numbers• outputs: A>B, A=B, A<B

° Design Approaches• the truth table

- 22n

entries - too cumbersome for large n

• use inherent regularity of the problem

- reduce design efforts

- reduce human errors

MagnitudeCompare

A[3..0]

B[3..0]A = B

A < B

A > B

Magnitude Comparator

A0

A1

A2

A3

B0

B1

B2

B3

A_EQ_B

C0

C1

C3

C2

D01

D23

How can we find A > B?

How many rows would a truth table have?

28 = 256

Magnitude Comparator

A0

A1

A2

A3

B0

B1

B2

B3

A_EQ_B

C0

C1

C3

C2

D01

D23

If A =1001 and B = 0111is A > B?Why?

Because A3 > B3i.e. A3 . B3’ = 1

Therefore, one term in thelogic equation for A > B isA3 . B3’

Find A > B

Magnitude Comparator

If A = 1010 and B = 1001is A > B?Why? Because A3 = B3 and

A2 = B2 and A1 > B1i.e. C3 = 1 and C2 = 1 and A1 . B1’ = 1

Therefore, the next term in thelogic equation for A > B isC3 . C2 . A1 . B1’

A > B = A3 . B3’ + C3 . A2 . B2’ + …..

Magnitude Comparison

° Algorithm -> logic• A = A3A2A1A0 ; B = B3B2B1B0

• A=B if A3=B3, A2=B2, A1=B1and A1=B1

° Test each bit:- equality: xi= AiBi+Ai'Bi'

- (A=B) = x3x2x1x0

° More difficult to test less than/greater than• (A>B) = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0'

• (A<B) = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0

• Start comparisons from high-order bits

° Implementation• xi = (AiBi'+Ai'Bi)’

Multiplexers

o A multiplexer haso N control inputso 2N data inputso 1 output

o A multiplexer routes (or connects) the selected data input to the output.

o The value of the control inputs determines the data input that is selected.

4– to– 1- Line Multiplexer

Quadruple 2–to–1-Line Multiplexer

Notice enable bit

Notice select bit

4 bit inputs

Binary Decoder

° Black box with n input lines and 2n output lines

° Only one output is a 1 for any given input

° Convert binary information from n input lines to 2n output lines.

° Known as n-to-m-line decoder (m = 2n).

° May be used to generate the 2n minterms of n input variables.

BinaryDecoder

ninputs m=2n outputs

2-to-4 Binary Decoder2-to-4 Binary Decoder

° From truth table, circuit for 2x4 decoder is:

° Note: Each output is a 2-variable minterm (X'Y', X'Y, XY' or XY)

X Y F0 F1 F2 F3

0 0 1 0 0 00 1 0 1 0 01 0 0 0 1 01 1 0 0 0 1

F0 = X'Y'

F1 = X'Y

F2 = XY'

F3 = XY

X Y

Truth Table:

2-to-4Decoder

X

Y

F0

F1

F2

F3

3-3-to-8 to-8 BinaBinary ry DecDecoderoderx y z F0 F1 F2 F3 F4 F5 F6 F7

0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 00 1 0 0 0 1 0 0 0 0 00 1 1 0 0 0 1 0 0 0 01 0 0 0 0 0 0 1 0 0 01 0 1 0 0 0 0 0 1 0 01 1 0 0 0 0 0 0 0 1 01 1 1 0 0 0 0 0 0 0 1

F1 = x'y'z

x zy

F0 = x'y'z'

F2 = x'yz'

F3 = x'yz

F5 = xy'z

F4 = xy'z'

F6 = xyz'

F7 = xyz

Truth Table:

3-to-8Decoder

X

Y

F0

F1

F2

F3

F4

F5

F6

F7

Z

Encoders

° If the decoder's output code has fewer bits than the input code, the device is usually called an encoder.

e.g. 2n-to-n

° The simplest encoder is a 2n-to-n binary encoder• One of 2n inputs = 1

• Output is an n-bit binary number

.

.

.

.

.

.

2n

inputsn outputs

Binaryencoder

8-to-3 Encoder

°Description:

•23 = 8 inputs, 3 outputs

•one input =1, others = 0’s

•Each input generate unique binary code

8-to-3 Encoder

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

8-to-3 Encoder (truth table) 8-to-3

Encoder

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

inputs outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

8-to-3 Encoder (truth table) 8-to-3

Encoder

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

10000000

000

inputs outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

8-to-3 Encoder (truth table) 8-to-3

Encoder

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

01000000

100

inputs outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

8-to-3 Encoder (truth table) 8-to-3

Encoder

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

00000100

101

inputs outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

8-to-3 Encoder (truth table) 8-to-3

Encoder

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

00000001

111

inputs outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

8-to-3 Encoder (equations) 8-to-3

Encoder

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

inputs outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

Note: This truth table is not complete! Why?

Output equations:

A0 = ?A1 = ?A2 = ?

8-to-3 Encoder (equations) 8-to-3

Encoder

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

inputs outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

Output equations:

A0 = D1 + D3 + D5 + D7

A1 = ?A2 = ?

8-to-3 Encoder (equations) 8-to-3

Encoder

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

inputs outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

Output equations:

A0 = D1 + D3 + D5 + D7

A1 = D2 + D3 + D6 + D7

A2 = ?

8-to-3 Encoder (equations) 8-to-3

Encoder

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

inputs outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

Output equations:

A0 = D1 + D3 + D5 + D7

A1 = D2 + D3 + D6 + D7

A2 = D4 + D5 + D6 + D7

8-to-3 Encoder (circuit)

8-to-3Encoder

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

Output equations:

A0 = D1 + D3 + D5 + D7

A1 = D2 + D3 + D6 + D7

A2 = D4 + D5 + D6 + D7

A0

A1

A2

D1

D3 D5 D7

D2

D3 D6

D7

D4

D5 D6

D7

DeMultiplexer

• Performs the inverse of the operation of a MUX

• It has one input line, the input from which is transmitted to one of 2n output lines

• The output lines are selected based on the select inputs

E1x2

DeMUX

S

D0 D1

1x4 DeMUX

° The circuit has an input E, the outputs are given by:

° D0 = E, if S0S1=00 D0 = S1’S0’ E

° D1 = E, if S0S1=01 D1 = S1’S0 E

° D2 = E, if S0S1=10 D2 = S1S0’ E

° D3 = E, if S0S1=11 D3 = S1S0 E

E1x4

DeMUX

S0 S1

D0 D1

D2 D3