1 ERD2011 ITRS Winter Conference – Incheon, Korea – 11 December 2011

2011 ERD chapters, scope, difficult challenges, taxonomy, etc.

An Chen GLOBALFOUNDRIES

2 ERD 2011 ITRS Winter Conference – Incheon, Korea – 11 December 2011

Scope• The addition of “More-than-Moore” broadens the ERD chapter

coverage and leads to new directions. The scope of ERD goes beyond “digital” into diversified functional domains. New criteria and methodologies may be needed, e.g., benchmarking.

• Differentiation of “More Moore”, “More-than-Moore”, and “beyond CMOS”. (next page)

• The addition of “storage class memory”, and “select device/diode” in memory section address key issues in application and critical technology enablers.

• The addition of quantitative benchmarking (based on NRI work) in critical assessment complement the survey-based assessment. Need to ensure consistency.

• Technology highlights expanded: carbon nanoelectronics, STT-MRAM and ReRAM. Provide guidance in down-selection.

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Fig. ERD1

“Source: ERD-WG in Japan”?

An interesting visualization of concepts of “More Moore”, “More-than-Moore”, and “beyond CMOS”, but clarification may be needed.

More Moore: “The expansion of the CMOS platform by conventional dimensional and functional scaling”More-than-Moore: “added value to devices is provided by incorporating functionalities that do not necessarily scale according to Moore's Law” Beyond CMOS: “new information processing devices and architectures .... have been the main subjects of this chapter”

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Difficult challenges (1)• Difficult challenges labeled with time frame (2018-2026) instead

of technology nodes.

• “Develop 2nd generation new channel materials” for CMOS scaling: intend to incorporate novel material including graphene?

Difficult Challenges Summary of Issues and opportunities

Scale high-speed, dense, embeddable, volatile, and non-volatile memory technologies to replace SRAM and / or FLASH for manufacture by 2018.

SRAM and FLASH scaling in 2D will reach definite limits within the next several years (see PIDS Difficult Challenges). These limits are driving the need for new memory technologies to replace SRAM and possibly FLASH memories by 2018.

Identify the most promising technical approach(es) to obtain electrically accessible, high-speed, high-density, low-power, (preferably) embeddable volatile and non-volatile RAM

The desired material/device properties must be maintained through and after high temperature and corrosive chemical processing. Reliability issues should be identified & addressed early in the technology development

Scale CMOS to and beyond 2018 - 2026

Develop 2nd generation new materials to replace silicon (or InGaAs, Ge) as an alternate channel and source/drain to increase the saturation velocity and to further reduce Vdd and power dissipation in MOSFETs while minimizing leakage currents for technology scaled to 2018 and beyond.

Develop means to control the variability of critical dimensions and statistical distributions (e.g., gate length, channel thickness, S/D doping concentrations, etc.)

Accommodate the heterogeneous integration of dissimilar materials. The desired material/device properties must be maintained through and after high temperature and corrosive chemical processing

Reliability issues should be identified & addressed early in this development.

Extend ultimately scaled CMOS as a platform technology into new domains of application.

Discover and reduce to practice new device technologies and primitive-level architecture to provide special purpose optimized functional cores (e.g., accelerator functions) heterogeneously integrable with CMOS.

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Difficult challenges (2)• Add the issue of compatibility requirement of “new information

processing technology” with “system architecture” (row 5): highlight the importance of architectures in utilizing unique characteristics.

• Add an entry of “More-than-Moore” (row 6): highlight the trend of functional diversification and future directions beyond “Moore’s law”.

Scale CMOS to and beyond 2018 - 2026

Accommodate the heterogeneous integration of dissimilar materials. The desired material/device properties must be maintained through and after high temperature and corrosive chemical processing

Reliability issues should be identified & addressed early in this development.

Extend ultimately scaled CMOS as a platform technology into new domains of application.

Discover and reduce to practice new device technologies and primitive-level architecture to provide special purpose optimized functional cores (e.g., accelerator functions) heterogeneously integrable with CMOS.

Continue functional scaling of information processing technology substantially beyond that attainable by ultimately scaled CMOS.

Invent and reduce to practice a new information processing technology eventually to replace CMOS

Ensure that a new information processing technology is compatible with the new memory technology discussed above; i.e., the logic technology must also provide the access function in a new memory technology.

A new information processing technology must also be compatible with a systems architecture that can fully utilize the new device. A new non-binary data representation and non-Boolean logic may be required to employ a new device for information processing. These requirements will drive the need for a new systems architecture.

Bridge the gap that exists between materials behaviors and device functions.

Accommodate the heterogeneous integration of dissimilar materials

Reliability issues should be identified & addressed early in the technology development

Invent and reduce to practice long term alternative solutions to technologies that address existing MtM ITRS topical entries currently in wireless/analog and eventually in power devices, MEMS, image sensors, etc.

The industry is now faced with the increasing importance of a new trend, “More than Moore” (MtM), where added value to devices is provided by incorporating functionalities that do not necessarily scale according to "Moore's Law“.

Heterogeneous integration of digital and non-digital functionalities into compact systems that will be the key driver for a wide variety of application fields, such as communication, automotive, environmental control, healthcare, security and entertainment.

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Taxonomy

Work in Progress --- Not for Publication1 ERD WG 4/10/11 Potsdam, Germany - FxF Meeting

A Taxonomy for Nano Information Processing Technologies

State Variable

Device

Data Representation

Architecture

Material

SETs

Molecular

Spintronics Quantum

Scaled CMOS Ferromagnetic

Quantum

Analog

Digital

Multicore Morphic

Von Neumann

Silicon

Carbon

Ge & III-V mat’ls

Strongly correlated mat’ls

Quantum state

Spin orientationMolecular state

Electric charge Strongly correlated electron state

Phase state

Nanostructured mat’ls

Patterns

Analog

Is it good to move these boxes not included in “conventional scaled CMOS” to the right to be grouped with other similar boxes, and move the layer name to the left to provide necessary space? Right now they are mixed with red-lined yellow boxes representing the current CMOS platform technology.

The taxonomy for nano information processing technologies is the same as in 2009: a good visualization of layers of processing technology components and options.

Is it necessary to rename some entries?

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Two assessments – consistency

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Technology entries – memory • Memory entries:

– Ferroelectric FET

– Ferroelectric polarization ReRAM

– Nanoelectromechanical memory

– Redox memory

– Mott memory

– Macromolecular memory

– Molecular memory

• Changes: (1) STTRAM move out; (2) Ferroelectric polarization ReRAM added to ferroelectric memory; (3) nanothermal and nanoionic memories merged in Redox memory; (4) electronic effect memory move out; (5) Mott memory added.

• The “research activity” entry is useful to evaluate progress. Need to ensure consistent and comprehensive measures used in selecting papers.

• Potential new entries? – Example: magneto-electric (ME) cell

– …

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Technology entries – logic • Logic entries:

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Organization, consistency, clarity• Chapter 4 includes memory, logic, and MtM (page 5-27) and is very

heavy. An associated problem is the long section labels (e.g., “4.1.3.2.2.1 MIT switch”). Should it be divided into three separated chapters?

• Typos on page 13: following “4.1.4.4” is “4.1.1.5” and should be “4.1.4.1”; section “4.2” starts with “4.2.4” and should be “4.2.1”. Long section labels may cause confusion.

• Choice of figures: there is one Fig. in the whole chapter 4, Fig. ERD3 on excitonic FET. Why not figures for other devices?

• Should we add a figure list and a table list in the text?

• With new additions, there is significant increase of references: from 327 (2009) to 577 (2011).

• What can be done to increase the voting number for critical assessment? – Votes outside of ERD group?

– More frequent survey (e.g., workshop, conference)?

• “Lookout table” for speculative devices or devices with limited experimental proof?

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Entries with different maturity

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Overall• Good expansion from 2009 version

– More-than-Moore

– Storage class memory, select device/diode

– Quantitative assessment

– Significant addition of references

– Highlights

• Ensure clarity and consistency – Chapter organization

– Technology entries

– Critical assessments