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Four-Bit Serial Adder

By Huong Ho, Long Nguyen, Lin-Kai Yang

Ins: Dr. David ParentDate: May 17th, 2004

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Agenda

• Abstract

• Introduction

• Project Details

• Summary of Results

• Conclusions

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Abstract

We designed an 4-bit serial adder that operated at 200 MHz and used of power 10.75mW and occupied an area of 192x60 um².

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Introduction

• Bit-serial structure is designed to process the input one bit at a time, generally using the results of the operations on the first bit to influence the processing of subsequent bits.

• Because it passes all the bits through the same logic, bit-serial reduces a significant amount of required hardware. Typically, the bit-serial approach requires 1/nth of the hardware required for the equivalent n-bit parallel design.

• Bit-serial structure reduces signal routing (1-bit signals instead of n-bit signals) and higher-speed operation (one adder and a register rather than an n-bit adder).

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Introduction (cont.)

• The price of this logic reduction is that the serial hardware takes n clock cycles to execute, while the equivalent parallel structure executes in one clock cycle.

• Bit-serial architectures have been used successfully in many applications that are dealing with a bit stream such as signal processing, audio, video etc…. It was extremely popular in the 2-5u technology range.

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4-bit Serial Adder Schematic

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Longest Path CalculationsLogicLevel

Gates Τpav Cg todrive

#CDNs #CDPs #LNs LPs Wn Wp Cg

1 DFF 0.625

2 INV 0.625 30 1 1 1 1 1.5 2.5 7

3 AOI 1 0.625 7 10 10 3 3 2.57 4.32 12

4 AOI 2 0.625 2*12 7 7 2 2 3.45 5.80 21

5 NAND2 0.625 21 3 2 2 1 1.5 2.5 7

6 NAND2 0.625 7 3 2 2 1 1.5 2.5 7

7 INV 0.625 7 1 1 1 1 1.5 2.5 7

8 DFF 0.625 2*7

Note: All widths are in microns and capacitances in fF

nsns

PHL 625.8

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D-Flip Flop CalculationsParts Cg to

driveWn Wp Cg of

gate#CDs #SPMOS #SNMOS

NOR2 slave 14 1.56 5.50 12.1 3 2 1

Keeper mux slave NA 1.5 1.5 5.1 NA NA NA

Driver mux slave 12.1 1.65 3.0 8.0 5 2 2

NOR2 master 13.1 1.5 5.16 11.4 3 2 1

Keeper mux master

NA 1.5 1.5 5.1 NA NA NA

Driver mux master

11.4 1.65 2.85 7.6 5 2 2

nsPHLPHL 313.

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D-Flip Flop Schematic

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D-Flip Flop Waveform

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Full Adder Schematic

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Full Adder Waveform

psPHL 562

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4-bit Serial Adder Schematic

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4-bit Serial Adder Waveform

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4-bit Serial Adder Layout

Area = 192 x 60 um²

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Power Consumption

P = 10.75 mW

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DRC & Extraction

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4-Bit Serial Adder LVS

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Summary of Results

Parameters Specification Simulation Results

Speed 200 MHz 200 MHz

Power (4-bit) None 10.75mW= 93.3W/cm²

Area (4-bit) Minimum 192 x 60 um²

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Acknowledgements

• Thank you Dr. Parent for being so patient!!!

• Thanks to Cadence Design Systems for the VLSI lab.

• Thanks to our classmates who helped us in the lab.