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1 FPGA Introduction - ge.infn.itmusico/DownloadFiles/Dottorato/Fpga_2015.pdf · 1 FPGA Introduction...

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1 FPGA Introduction FPGA Introduction FPGA Introduction FPGA Introduction An FPGA is an digital integrated circuit 015 An FPGA is programmable in the in the field (=outside the factory), hence the name “field programmable” Design is specified by schematics or with a hardware description o XXX ciclo 20 Design is specified by schematics or with a hardware description language Tools compute a programming file for the FPGA The FPGA is configured with the design Dottorato The FPGA is configured with the design Your electronic circuit is ready to use With an FPGA you can build electronic circuits … e dati: FPGA … without using a soldering iron … without plugging together existing modules … without having a chip pr oduced at a factor y a e acquisizion … without having a chip produced at a factory A lot of material taken from H.Sakulin lecture Elettronica
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FPGA IntroductionFPGA IntroductionFPGA IntroductionFPGA Introduction An FPGA is an digital integrated circuit

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g g An FPGA is programmable in the in the field (=outside the

factory), hence the name “field programmable”◦ Design is specified by schematics or with a hardware description

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cic

lo20 ◦ Design is specified by schematics or with a hardware description

language◦ Tools compute a programming file for the FPGA◦ The FPGA is configured with the design

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to ◦ The FPGA is configured with the design◦ Your electronic circuit is ready to use

With an FPGA you can build electronic circuits …

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PGA ◦ … without using a soldering iron

◦ … without plugging together existing modules◦ … without having a chip produced at a factory

ae

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ion … without having a chip produced at a factory

A lot of material taken from H.Sakulin lecture

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What’s inside an FPGAWhat’s inside an FPGAWhat s inside an FPGAWhat s inside an FPGA01

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A A LookUpLookUp Table (LUT) based cellTable (LUT) based cellA A LookUpLookUp Table (LUT) based cellTable (LUT) based cell01

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ALTERA ARRIA GX (1)ALTERA ARRIA GX (1)ALTERA ARRIA GX (1)ALTERA ARRIA GX (1)01

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ALTERA ARRIA GX (2)ALTERA ARRIA GX (2)ALTERA ARRIA GX (2)ALTERA ARRIA GX (2)01

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Clock treesClock treesClock treesClock trees01

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Clock managersClock managersClock managersClock managers01

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Embedded RAM blocksEmbedded RAM blocksEmbedded RAM blocksEmbedded RAM blocks01

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Embedded multipliers and DSPEmbedded multipliers and DSPEmbedded multipliers and DSPEmbedded multipliers and DSP01

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Soft and Hard processor coresSoft and Hard processor coresSoft and Hard processor coresSoft and Hard processor cores01

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General Purpose I/OGeneral Purpose I/OGeneral Purpose I/OGeneral Purpose I/O01

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High Speed serial interconnectHigh Speed serial interconnectHigh Speed serial interconnectHigh Speed serial interconnect01

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TrendsTrendsTrendsTrends Look-up-tables with more inputs (5 or 6)

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Look up tables with more inputs (5 or 6) Speed of serial links increasing (multiple Gb/s) More hard macro cores (Ethernet MAC, Memory

f C )

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Sophisticated soft macros◦ CPUs

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PGA ◦ GPUs

Processor-centric architecturesM lti + FPGA l i (Xili ZYNQ)

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ion Multi-core processor + FPGA logic (Xilinx ZYNQ) Ultra-low-power FPGAs Mixed-signal FPGAs

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ica Mixed-signal FPGAs

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FPGA FPGA ASIC comparisonASIC comparisonFPGA FPGA –– ASIC comparisonASIC comparison FPGA

ASICHi h f

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FPGA◦ Rapid development

cycle (minutes / hours)

Higher performance Analog designs possible Better radiation hardness

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y ( )◦ May be reprogrammed

in the field (firmware d )

Better radiation hardness Long development cycle (weeks

/ months) Design cannot be changed once

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to upgrade) New features Bug fixes

Design cannot be changed once it is produced

Extremely high development t

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◦ Low development cost You can get started with

$200 d l

cost ASICs are produced at a

semiconductor fabrication f ili (“f b”) di

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ion a $200 development

board and free softwarefacility (“fab”) according to your design

Lower cost per device d FPGA h l

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ica compared to FPGA, when large

quantities are needed

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Programming techniquesProgramming techniquesProgramming techniquesProgramming techniques

Antifuse technology

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Antifuse technology

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EEPROM (Flash Eprom)

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SRAM

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SRAM FPGA ConfigurationSRAM FPGA ConfigurationSRAM FPGA ConfigurationSRAM FPGA Configuration01

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Programming using JTAGProgramming using JTAGProgramming using JTAGProgramming using JTAG01

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Programming from a host PCProgramming from a host PCProgramming from a host PCProgramming from a host PC01

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ManufacturersManufacturersManufacturersManufacturers Xilinx

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Xilinx◦ First company to produce FPGAs in 1985◦ About 50% market share, today

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Altera◦ About 40% market share

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Actel (now Microsemi)

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PGA ◦ Anti-fuse FPGAs

◦ Flash based FPGAs◦ Mixed Signal

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DevelopingDevelopingDevelopingDeveloping Schematic

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Schematic◦ Graphical overview◦ Can draw entire design

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HDL: Verilog, VHDLC bl k l

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◦ (Almost) independent of design tool◦ May use tools used in SW development (CVS, SVN …)

New trends

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◦ C-like languages (handle-C, system-C, …)◦ Labview

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Schematic and HDL are often combined together

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Combining various design entry stylesCombining various design entry stylesCombining various design entry stylesCombining various design entry styles01

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Design FlowDesign FlowDesign FlowDesign Flow01

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First Level Trigger at collidersFirst Level Trigger at collidersFirst Level Trigger at collidersFirst Level Trigger at colliders01

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FPGA used in trigger logic because:FPGA used in trigger logic because:FPGA used in trigger logic because:FPGA used in trigger logic because: They are fast

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They are fast◦ Much faster than discrete electronics (shorter

connections)

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Many parallel inputs◦ Data from many parts of the detector has to be

b d

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to combined◦ Can send parallel data rather than serialAll ti f d i ll l

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PGA All operations are performed in parallel

◦ Can build pipelined logic They can be re programmed

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ion They can be re-programmed◦ Trigger algorithms can be optimized

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FPGA used in data acquisitionFPGA used in data acquisitionFPGA used in data acquisitionFPGA used in data acquisition Frontend Electronics

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Frontend Electronics◦ Pedestal subtraction◦ Zero suppression

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◦ …C d li k

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Several serial LVDS links in parallel Up to 400 MB/s

Interface from custom hardware to commercial l i

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ion electronics◦ PCI bus, VME bus, Myrinet, etc.

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26 Example: Multi Purpose Digitizer (MPD)Example: Multi Purpose Digitizer (MPD) 16 channels, differntial, 12 bit, up to 50 MHz, synchronous ADC, Full-

Scale Range: 2Vpp 4 x HDMI-A front panel connectors for analog inputs

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p g p 2 x HDMI-A front panel connectors for digital controls (clock, fast

commands, I2C) 2 +2 general purpose coaxial (LEMO 00) front panel inputs and outputs,

software selectable NIM or LVTTL levels

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software selectable NIM or LVTTL levels Front panel coaxial (LEMO 00) clock input, 40 MHz, LVTTL, 50

terminated 10-100 RJ-45 copper Ethernet port

SFP f l i i bi i l li k i

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to SFP cage for multigigabit optical link connection 4 general purpose LEDs VXS connector option, 4 RX and 4 TX pairs connected to the FPGA ADC clock phase adjustable to compensate cable delay

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ADC clock phase adjustable to compensate cable delay Logic functions based on Altera ARRIA-GX EP1AGX60F780 FPGA On board real time data processing capabilities VME 64x compliant with up to 2eSST cycles

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VME live insertion capabilities 128 MB DDR2 SDRAM SD-Card interface

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Single +5V power supply Expansion option using PMC compliant connectors VME based or standalone operation

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MPD Block DiagramMPD Block DiagramMPD Block DiagramMPD Block Diagram01

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Inside the MPD FPGAInside the MPD FPGAInside the MPD FPGAInside the MPD FPGA01

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29 Channel Processor & Event BuilderChannel Processor & Event BuilderChannel processor

Event Builder01

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40 MHz

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Another Example: Another Example: TofPetTofPet EndoProbeEndoProbeAnother Example: Another Example: TofPetTofPet EndoProbeEndoProbe01

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TofPetTofPet ASICASICTofPetTofPet ASICASIC 64 channel SiPM readout in PET application Clock frequency 80 160 MHz

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Clock frequency 80 - 160 MHz Dynamic range of input charge 300 pC SNR (Qin = 100 fC) > 20-25 dB

A lifi i (i t t l jitt ) < 25 (FWHM)

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lo20 Amplifier noise (in total jitter) < 25 ps (FWHM)

TDC time binning 50 ps Coarse gain G0, G0/2, G0/4

M h l h 100 kH

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to Max. channel hit rate 100 kHz Max. output data rate 320 Mb/s (640 w/ DDR) Channel masking programmable

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PGA SiPM fine gain adjustment 500 mV (5 bits)

SiPM C up to 320pF, 2MHz DCR Calibration BIST internal gen. pulse, prog. ampl.

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Power < 10mW per channel

LVDS 10 MHz SPI configuration link for bias/channel setting

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LVDS 160-640 Mbps data output interface On-chip DACs and reference generators

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TofPetTofPet ASIC Block DiagramASIC Block DiagramTofPetTofPet ASIC Block DiagramASIC Block Diagram The TOFPET ASIC consists of a 64-channel analogue

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The TOFPET ASIC consists of a 64 channel analogue block, calibration circuitry, Golden-reference and Bias generators and a global controller.

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EndoProbeEndoProbe FPGA Block DiagramFPGA Block DiagramEndoProbeEndoProbe FPGA Block DiagramFPGA Block Diagram01

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