1 GSPS Ë 3.3 V CMOS ± ¥ 4 Õ r ï · ad9910 rev. b | page 5 of 64 Á 06479-002 16 parallel input...

ADI ADI ADI

1 GSPS 14 3.3 V CMOS

AD9910

Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

Fax: 781.461.3113 ©2007–2008 Analog Devices, Inc. All rights reserved.

14-BIT DAC1GSPS DDS CORE

LINEARRAMP

GENERATOR

1024-ELEMENT

RAM

HIGH SPEED PARALLELDATA INTERFACE

TIMING AND CONTROL

SERIAL CONTROLDATA PORT

REFCLKMULTIPLIER

0647

9-00

1

AD9910

1 GSPS ( 400 MHz )

1 GSPS 14 DAC

0.23 Hz

≤–125 dBc/Hz(1 kHz 400 MHz )

>80 dB SFDR

/ (I/O)

/ /

8

Sin(X)/(X) ( )

1.8 V 3.3 V

/

100 TQFP_EP

1024 ×32 RAM

PLL REFCLK

(LO)

FM

1.

PLL ................................................... 27

PLL ................................................................................. 27

(OSK) .................................................................... 27

OSK ................................................................................ 27

OSK ................................................................................ 28

(DRG) ............................................................... 28

DRG ................................................................................ 28

DRG ....................................................................... 30

DRG ....................................................................... 30

DRG .................................................................. 30

....................................................................... 30

................................................................... 32

DROVER ....................................................................... 32

RAM ....................................................................................... 33

RAM ............................................................................... 33

RAM / ............................................................ 33

RAM .................................................. 33

RAM_SWP_OVR RAM ........................... 34

RAM .............................................................. 34

RAM .............................................................. 34

RAM ................................................ 35

RAM .................................................................. 35

RAM Profile ..................................... 36

Profile ...................................... 38

RAM .............................................................. 38

RAM ..................................................... 39

RAM .............................................................. 41

........................................................................................ 42

Profile ...................................................................................... 42

I/O_UPDATE SYNC_CLK ............... 42

I/O .......................................................................... 43

................................................................................................... 1

................................................................................................... 1

........................................................................................... 1

........................................................................................... 4

................................................................................................... 5

........................................................................................... 6

.................................................................................. 6

............................................................................. 9

.................................................................................. 9

ESD ................................................................................... 9

................................................................... 10

................................................................................ 13

........................................................................................ 16

........................................................................................ 17

....................................................................... 17

RAM ...................................................................... 18

.............................................................. 19

...................................................... 20

(PDCLK) ................................................... 20

(TxENABLE) .................................................... 21

............................................................................ 22

................................................................................ 23

DDS ................................................................................ 23

14 DAC ....................................................................... 23

DAC ............................................................................ 24

sinc ......................................................................... 24

(REF_CLK/REF_CLK) ........................................ 24

REF_CLK/REF_CLK ............................................... 24

REF_CLK/REF_CLK ....................................... 25

REF_CLK/REF_CLK ....................................... 25

(PLL) ......................................................... 25

PLL ......................................................................... 26

AD9910

Rev. B | Page 2 of 64

/ (I/O_RESET) .......................................... 49

/ (I/O_UPDATE) ...................................... 49

I/O ..................................................................... 49

MSB/LSB ........................................................................ 49

.............................................................. 50

.............................................................. 55

1 (CFR1)— 0x00 .......................... 55

2 (CFR2)— 0x01 .......................... 57

3 (CFR3)— 0x02 .......................... 58

DAC — 0x03 ................................. 58

I/O — 0x04 .................................... 59

(FTW)— 0x07 ......................... 59

(POW)— 0x08 ......................... 59

(ASF)— 0x09 ....................... 59

— 0x0A ..................................... 60

— 0x0B ................................. 60

— 0x0C ................................. 60

— 0x0D ................................ 60

Profile ..................................................................... 61

........................................................................................ 62

................................................................................

................................................................................ 43

.................................................................................... 44

........................................................................................ 47

3.3 V ................................................................................ 47

DVDD_I/O (3.3V) 11/15/21/28/45/56/66 ........... 47

AVDD (3.3V) 74 77/83 ...................................... 47

1.8 V ................................................................................ 47

DVDD (1.8V) 17/23/30/47/57/64 ......................... 47

AVDD (1.8V) 3 ........................................................ 47

AVDD (1.8V) 6 ........................................................ 47

AVDD (1.8V) 89/92 ................................................ 47

........................................................................................ 48

— I/O ............................................................. 48

I/O ................................................................. 48

................................................................................ 48

........................................................... 48

I/O ............................................... 48

(SCLK) ............................................................... 48

CS ................................................................... 48

/ (SDIO) ............................................ 48

(SDO) ........................................................ 48

AD9910


“DVDD (1.8V)( 17/23/30/47/57/64)” 　　　　

“AVDD (1.8V)( 89/92)” ............................................... 47“ — I/O” ................................................ 48

17 ......................................................................................... 5019 ......................................................................................... 5720 21 ................................................................................ 58

2008 2 — 0 A　　　　　　　　　　　 “ ” .............................................................................. 1

1 REFCLK .......................................... 5SYNC_CLK .................................................... 6I/O Update/Profile[2:0] ........................................ 6TxENABLE/ ( PDCLK) 　　　　　　

TxENABLE/ ( PDCLK) ...................................... 6 ................................................................ 6

3 ........................................................................................... 109 10 11 12 13 14 .......................... 1230 7 .............................................................................. 24

“ I/O ” ............................................................. 4116 ................................................................... 4149 53 ........................................................................... 43

“ ” ................................................................... 46“ I/O ” .................................................... 47

17 ......................................................................................... 4919 ......................................................................................... 5620 ......................................................................................... 5732 ......................................................................................... 60

2007 5 — 0 　　　　　　　　　　　　

2008 12 — A B　　　　　　　　　　　2 ............................................................................................ 5

1 I/O_UPDATE 　　　　　　　　　

Profile .................................................... 71 XTAL_SEL .................................................. 8

3 ........................................................................................... 1120 ......................................................................................... 1622 ......................................................................................... 1723 ......................................................................................... 1824 ......................................................................................... 1925 ......................................................................................... 20

“REF_CLK/REF_CLK ” ....................................... 24“ REF_CLK/REF_CLK ” ...................................... 25“PLL ” 　　　　　　　　　　　　　　

“ (OSK)” ........................................................ 27“DRG ” “ ” ............... 30“DROVER ” ........................................................... 32

43 ......................................................................................... 35“ 45 Profile ”　　　　　 ................................................................................................. 38

47 ......................................................................................... 4048 ......................................................................................... 41

“I/O_UPDATE ” ................................................... 41“Profile” ......................................................................... 42“I/O_UPDATE SYNC_CLK ” ... 42“ 49 ” ............................................................... 42“ ” ............................................................... 44

AD9910


AD9910


0647

9-00

2

16PARALLEL

INPUT

PDCLK

SCLK

SDIO

I/O_RESET

PROFILE[2:0]

I/O_UPDATE

RAM

POWER-DOWN

CONTROL

EX

T_P

WR

_DW

NDAC_RSET

IOUT

IOUT

CS

TxENABLE

DAC FSC

OSK

RAM_SWP_OVR

A

θ INVERSESINC

FILTER

CLOCK

AMPLITUDE (A)

FREQUENCY (ω )

PHASE (θ)

DIGITALRAMP

GENERATOR

8

DAC FSC8

2DRCTL

DRHOLD

DROVER

2

MULTICHIPSYNCHRONIZATION

SYSCLK

PLL

÷2

CL

OC

K M

OD

E

REF_CLK

REF_CLK

REFCLK_OUT

XTAL_SEL

PARALLEL DATATIMING ANDCONTROL

SE

RIA

L I/O

PO

RT

2 AD9910

PROGRAMMINGREGISTERS

OUTPUTSHIFT

KEYING

DATAROUTE

ANDPARTITIONCONTROL

3

INTERNAL CLOCK TIMINGAND CONTROL

ω

Acos (ω t + θ)

Asin (ω t + θ)

SY

NC

_SM

P_E

RR

SY

NC

_CL

K

SY

NC

_OU

T

SY

NC

_IN

PL

L_L

OC

K

PL

L_L

OO

P_F

ILT

ER

MA

ST

ER

_RE

SE

T

22

DAC14-BIT

DDS

AUXDAC8-BIT

AD9910 14 DAC(DDS) 1 GSPS AD9910 DDS

DDS/DAC400 MHz

DDSDDS 321 GSPS

0.23 Hz DDS

I/O AD9910AD9910 AD9910

RAM /AD9910

AD9910

AD9910 (“ ” )

2.

AVDD (1.8V) DVDD (1.8V) = 1.8 V ± 5% AVDD (3.3V) = 3.3 V ± 5% DVDD_I/O (3.3V) = 3.3 V ± 5% T = 25°C RSET = 10 kΩIOUT = 20 mA (REFCLK) = 1000 MHz

AD9910


REFCLK

REFCLK 60 1000 MHz 3.2 60 MHz

REFCLK 1500 1900 MHz REFCLK 25 35 MHz

25 MHz 3 pF

2.8 kΩ 1.4 kΩ

REFCLK 45 55 % REFCLK 40 60 % REFCLK 50 1000 mV p-p 100 2000 mV p-p

REFCLK VCO VCO (KV) @ VCO 0 429 MHz/V

VCO 1 500 MHz/V VCO 2 555 MHz/V VCO 3 750 MHz/V VCO 4 789 MHz/V VCO 51 850 MHz/V REFCLK_OUT

20 pF 25 MHz

DAC 8.6 20 31.6 mA −10 +10 % FS 2.3 μA 0.8 LSB 1.5 LSB 5 pF 1 kHz 20 MHz AOUT

REFCLK −152 dBc/Hz 20x −140 dBc/Hz 100x −140 dBc/Hz

DAC −0.5 +0.5 V SFDR

SFDR 50.1 MHz ±500 kHz –87 dBc

521± kHz –87 dBc 5.21± kHz –96 dBc

101.3 MHz ±500 kHz –87 dBc 521± kHz –87 dBc 5.21± kHz –95 dBc

1

AD9910





SCLK 70 Mbps SCLK 4 ns

4 ns SCLK / 2 ns

SCLK 5 ns SCLK 0 ns

11 ns I/O_UPDATE/PROFILE[2:0]

SYNC_CLK 1.75 nsSYNC_CLK 0 ns

I/O_UPDATE >1 SYNC_CLKProfile 2 SYNC_CLK

Tx_ENABLE 16 PDCLK 250 MHz TxENABLE/ PDCLK 1.75 ns TxENABLE/ PDCLK 0 ns

2

8 SYSCLK 3

REFCLK 1 ms REFCLK

5 SYSCLK 3

Profile

DAC OSK 91 SYSCLK 3

DAC OSK 79 SYSCLK 3

79 SYSCLK 3

DAC 47 SYSCLK 3

RAM DAC 94 SYSCLK 3/

DAC 106 SYSCLK 3

58 SYSCLK 3

DAC 91 SYSCLK 3/

DAC 91 SYSCLK 3

47 SYSCLK 3

16 DAC 103 SYSCLK 3

91 SYSCLK 3

AD9910


CMOS Logic 1 2.0 V Logic 0 0.8 V Logic 1 90 120 μA Logic 0 38 50 μA

2 pF XTAL_SEL

Logic 1 2.0 V Logic 0 0.8 V Logic 1 90 120 μA Logic 0 38 50 μA

2 pF CMOS 1 mA

Logic 1 2.8 V Logic 0 0.4 V

IAVDD (1.8 V) 110 mA IAVDD (3.3 V) 29 mA IDVDD (1.8 V) 222 mA IDVDD (3.3 V) 11 mA

715 850 mW 330 400 mW 19 25 mW

1 VCO 5 1000 MHz

PLL PLL PLLSYSCLK DDS SYSCLK

SYSCLK

2

3

AD9910


2

AVDD (1.8V) DVDD (1.8V) 2 V AVDD (3.3V) DVDD_I/O (3.3V) 4 V

−0.7 V to +4 V 5 mA −65°C to +150°C −40°C to +85°C

θJA W/C°22 θJC W/C°8.2

150°C 10 300°C 06

479-

003

MUST TERMINATE OUTPUTS TO AGNDFOR CURRENT FLOW. DO NOT EXCEEDTHE OUTPUT VOLTAGE COMPLIANCERATING.

IOUT IOUT

DAC OUTPUTS

AVDD

AVOID OVERDRIVING DIGITAL INPUTS.FORWARD BIASING ESD DIODES MAYCOUPLE DIGITAL NOISE ONTO POWERPINS.

DIGITAL INPUTS

INPUT

DVDD_I/O

0647

9-05

5

ESD

3.

4.

ESD

ESDESD

5.

AD9910


26

27

28 29

30

55

54

53

52

51

TQFP-100 (E_PAD)TOP VIEW

(Not to Scale)

AD9910

D14

D13

DV

DD

_I/O

(3.

3V)

DG

ND

DV

DD

(1.

8V)

5

4

3

2

7

6

9

8

1

11

10

16

15

14

13

18

17

20

19

22

21

12

24

23

25

32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 5031 37

D12

D11

D10 D9

D8

D7

D6

D5

D4

PD

CL

K

TxE

NA

BL

E

DG

NDD3

D2

D1

DV

DD

_I/O

(3.

3V)

DV

DD

(1.

8V)

D0 F1

F0

80

IOU

T

79

AG

ND

78A

GN

D

77

AV

DD

(3.

3V)

76

AV

DD

(3.

3V)

75 AVDD (3.3V)

74 AVDD (3.3V)

73 AGND72 NC

71 I/O_RESET70 CS

69 SCLK

68 SDO67 SDIO

66 DVDD_I/O (3.3V)65 DGND

64 DVDD (1.8V)

63 DRHOLD62 DRCTL

61 DROVER

60 OSK

59 I/O_UPDATE

58 DGND57 DVDD (1.8V)

56 DVDD_I/O (3.3V)

SYNC_CLK

PROFILE0

PROFILE1

PROFILE2

DGND

100

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

NC

NC

NC

NC

AG

ND

XTA

L_S

EL

RE

FC

LK

_OU

T

NC

AV

DD

(1.

8V)

RE

F_C

LK

RE

F_C

LK

AV

DD

(1.

8V)

AG

ND

NC

NC

AG

ND

DA

C_R

SE

T

AV

DD

(3.

3V)

AG

ND

IOU

T

NC

PLL_LOOP_FILTER

AVDD (1.8V)

AGND

AGND

AVDD (1.8V)

SYNC_IN+

SYNC_IN–

SYNC_OUT+

SYNC_OUT–

DVDD_I/O (3.3V)

SYNC_SMP_ERR

DGND

MASTER_RESET

DVDD_I/O (3.3V)

DGND

DVDD (1.8V)

EXT_PWR_DWN

PLL_LOCK

NC

DVDD_I/O (3.3V)

DGND

DVDD (1.8V)

RAM_SWP_OVR

D15

0647

9-00

4

PIN 1INDICATOR

NOTES:1. EXPOSED PAD SHOULD BE SOLDERED TO GROUND.2. NC = NO CONNECT.

AD9910


3.

I/O1

1, 20, 72, 86, 87, 93, 97 100

NC

2 PLL_LOOP_FILTER I PLL “ PLL ”

3, 6, 89, 92 AVDD (1.8V) I VDD 1.8VAVDD (3.3V) I DAC VDD 3.3V74 77, 83

17, 23, 30, 47, 57, 64

DVDD (1.8V) I VDD 1.8V

11, 15, 21, 28, 45, 56, 66

DVDD_I/O (3.3V) I / VDD 3.3V

4, 5, 73, 78, 79, 82, 85, 88, 96

AGND I

13, 16, 22, 29, 46, 51, 58, 65

DGND I

7 SYNC_IN+ I

8 SYNC_IN− I

9 SYNC_OUT+ O

10 SYNC_OUT− O

12 SYNC_SMP_ERR O

14 MASTER_RESET I

18 EXT_PWR_DWN I

19 PLL_LOCK O

24 RAM_SWP_OVR O

25 27, 31 39, 42 44, 48

D[15:0] I

49, 50 F[1:0] I40 PDCLK O

41 TxENABLE I

52 54 PROFILE[2:0] I

55 SYNC_CLK O

(LVDS)“ ”

(LVDS)“ ”

(LVDS)“ ”

(LVDS)“ ”

AD9910SYNC_IN+/SYNC_IN−

0

“ ”

PLL PLL

RAM RAM

RAM RAM

1/4 AD9910 I/O_UPDATEPROFILE[2:0]

Profile DDS / profile 8 I/O

SYNC_CLK

(LVDS) ( )“ ”

( ) OSK0( ) ( )

0

( ) /1( )

“ (DRG)”0

( )“ (DRG)”

0/ / ( )

( )

( )AD9910

( ) AD9910AD9910 /

AD9910

/ ( ) /( “ / (I/O_RESET)” )

DAC ( ) 50Ω AGND

DAC ( ) 50Ω AGND

DAC AGND 10kΩ

“REF_CLK/REF_CLK ”

“REF_CLK/REF_CLK ”

“REF_CLK/REF_CLK ”1.8 V XTAL_SEL

AVDD(1.8V) AGND

EPAD

I/O1

AD9910


59 I/O_UPDATE I/O

60 OSK I

61 DROVER O

62 DRCTL I

63 DRHOLD I

67 SDIO I/O

68 SDO O

69 SCLK I

70 CS I

71 I/O_RESET I

80 IOUT O

81 IOUT O

84 DAC_RSET O

90 REF_CLK I

91 REF_CLK I

94 REFCLK_OUT O 95 XTAL_SEL I

96 (EPAD) (EPAD)

1 I = O =

AD9910


–50

–55

–60

–65

–75

–70

0647

9-03

4

SF

DR

(d

Bc)

OUTPUT FREQUENCY (MHz)

SFDR WITHOUT PLL

SFDR WITH PLL

0 50 100 150 200 250 300 350 400

400 450052 003 350200150100500

0647

9-04

6

SF

DR

(d

Bc)


–75

–70

–65

–60

–55

–45

–50

LOW SUPPLY

HIGH SUPPLY

400 450300250 35005 001 051 0020

0647

9-04

7

SF

DR

(d

Bc)


–75

–70

–65

–60

–55

–50

–40°C

+85°C

START 0Hz–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

50MHz/DIV STOP 500MHz

0647

9-03

5

1

SF

DR

(d

Bc)

0

–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

START 0Hz 50MHz/DIV STOP 500MHz

0647

9-03

6

1

SF

DR

(d

Bc)

0647

9-03

7

START 0Hz–100

–90

–80

–70

–60

–50

–40

–30

–20

–10

0

50MHz/DIV STOP 500MHz

1

SF

DR

(d

Bc)

6. SFDR(PLL = 15.625 MHz64)

9. 10 MHz SFDR REFCLK = 1 GHz



7. SFDR (±5%) REFCLK = 1 GHz

8. SFDRREFCLK = 1 GHz

AD9910


0647

9-03

8

CENTER 10.32MHz–120

–108

–96

–84

–72

–60

–48

–36

–24

–12

0

2.5kHz/DIV SPAN 25kHz

1

SF

DR

(d

Bc)

0647

9-03

9


–108

–96

–84

–72

–60

–48

–36

–24

–12

0


1

SF

DR

(d

Bc)

0647

9-04

0


–108

–96

–84

–72

–60

–48

–36

–24

–12

0


1

SF

DR

(d

Bc)

–90

–100

–120

–110

–140

–150

–130

–170

–160

M001k001k01k100101 1M 10M

0647

9-04

2

MA

GN

ITU

DE

(d

Bc/

Hz)

FREQUENCY OFFSET (Hz)

fOUT = 20.1MHz

fOUT = 98.6MHz

fOUT = 201.1MHz

fOUT = 397.8MHz

12. 10.32 MHz SFDR REFCLK = 1 GHz 14. 403.78 MHz SFDR REFCLK = 1 GHz

15. 1 GHz PLL13. 204.36 MHz SFDR REFCLK = 1 GHz

AD9910


–90

–100

–110

–120

–130

–140

–150

–16010 100 1k 10k 100k 1M 10M 100M

0647

9-04

3

MA

GN

ITU

DE

(d

Bc/

Hz)

FREQUENCY OFFSET (Hz)

fOUT = 20.1MHz

fOUT = 397.8MHz

fOUT = 98.6MHz

fOUT = 201.1MHz

400

450

300

250

350

200

150

100

50

0100 200 300 400 500 600 700 800 900 1000

0647

9-04

4

PO

WE

R D

ISS

IPA

TIO

N (

mW

)

SYSTEM CLOCK FREQUENCY (MHz)

DVDD 3.3V

AVDD 3.3V

AVDD 1.8V

DVDD 1.8V

400

450

300

250

350

200

150

100

50

0400 500 600 700 800 900 1000

0647

9-04

5

PO

WE

R D

ISS

IPA

TIO

N (

mW

)

SYSTEM CLOCK FREQUENCY (MHz)

DVDD 1.8V

AVDD 1.8V

AVDD 3.3V

DVDD 3.3V

16. 1 GHz50 MHz 20× PLL

17. (PLL )

18. (PLL )

AD9910


LOOPFILTER

PHASECOMPARATOR VCO

AD9910 REF_CLK

REFERENCECHARGE

PUMP

AD9510, AD9511, ADF4106

÷

÷

0647

9-05

6

LPF

AD9910(SLAVE 1)

AD9910(MASTER)

CLOCKSOURCE

AD9910(SLAVE 2)

AD9910(SLAVE 3)

FPGADATA

SYNC_CLK

REF_CLK

SYNC_CLK

SYNC_CLK

FPGADATA

FPGADATA

DATAFPGA

SYNC_CLK

C1S1

C2S2

C3S3

C4S4

A1

A2

A4

A3

A_END

CENTRALCONTROL

AD9510CLOCK DISTRIBUTOR

WITHDELAY EQUALIZATION

SYNC_OUT

AD9510SYNCHRONIZATION

DELAY EQUALIZATION

0647

9-05

8

AD9910REFCLK

n

PROGRAMMABLE 1 TO 32DIVIDER AND DELAY ADJUST

CLOCK OUTPUTSELECTION(S)

n = DEPENDENT ON PRODUCT SELECTION.

AD9515AD9514AD9513AD9512

LVPECLLVDSCMOS

CH 2

0647

9-05

7

LPF

19. PLL DDS

20. AD9510

21. AD9512/AD9513/AD9514/AD9515


0647

9-00

5

16PARALLEL

INPUT

PDCLK

SCLK

SDIO

I/O_RESET

PROFILE[2:0]

I/O_UPDATE

RAM

POWER-DOWN

CONTROL

EX

T_P

WR

_DW

N

DAC_RSET

IOUT

IOUT

CS

TxENABLE

DAC FSC

OSK A

θ INVERSESINC

FILTER

CLOCK

AMPLITUDE (A)

FREQUENCY (ω )

PHASE (θ)

DIGITALRAMP

GENERATOR

8

DAC FSC8

2

2


SYSCLK

PLL

÷2

CL

OC

K M

OD

E

REF_CLK

REF_CLK

REFCLK_OUT

XTAL_SEL


SE

RIA

L I/

O P

OR

T

2 AD9910


OUTPUTSHIFT

KEYING

DATAROUTE

ANDPARTITIONCONTROL

3


ω

Acos (ω t + θ)

Asin (ω t + θ)

SY

NC

_SM

P_E

RR

SY

NC

_OU

T

SY

NC

_IN

PL

L_L

OC

K

PL

L_L

OO

P_F

ILT

ER

MA

ST

ER

_RE

SE

T

22

AUXDAC8-BIT

DAC14-BIT

DDS

RAM_SWP_OVR

DRCTL

DRHOLD

DROVER

SY

NC

_CL

K

22.

AD9910 RAM

DDS/

I/ODDS RAM DDS

RAMDDS

DDS

DDSDDS

DDS

AD9910 (OSK)DDS

OSK DDSOSK

DDS

OSK

DDS AD9910“ ” 5

DDSProfile DDS

AD9910 8 Profile

Profile profile(PROFILE[2:0]) profile Profile

SYNC_CLK ProfileDDS

AD9910


0647

9-00

6

16PARALLEL

INPUT

PDCLK

SCLK

SDIO

I/O_RESET

PROFILE[2:0]

I/O_UPDATE

RAM

EX

T_P

WR

_DW

NDAC_RSET

IOUT

IOUT

CS

TxENABLE

DAC FSC

OSK A

θ INVERSESINC

FILTER

CLOCK

AMPLITUDE (A)

FREQUENCY (ω )

PHASE (θ)

DIGITALRAMP

GENERATOR

8

DAC FSC8

2

2


SYSCLK

PLL

÷2

CL

OC

K M

OD

E

REF_CLK

REF_CLK

REFCLK_OUT

XTAL_SEL


SE

RIA

L I/

O P

OR

T

2 AD9910


OUTPUTSHIFT

KEYING

DATAROUTE

ANDPARTITIONCONTROL

3


ω

Acos (ω t + θ)

Asin (ω t + θ)

SY

NC

_SM

P_E

RR

SY

NC

_OU

T

SY

NC

_IN

PL

L_L

OC

K

PL

L_L

OO

P_F

ILT

ER

MA

ST

ER

_RE

SE

T

22

DDS

AUXDAC8-BIT

DAC14-BIT

RAM_SWP_OVR

DRCTL

DRHOLD

DROVER

SY

NC

_CL

K

POWER-DOWN

CONTROL

RAM RAM ( 23) RAM I/O_UPDATE

( Profile) DDSRAM

RAM 1024×32RAM

RAM DDSDDS 32

DDS (RAM ) 8

RAM Profile Profile(PROFILE[2:0]) Profile Profile

SYNC_CLK RAM Profile

RAMDDS

RAM16 14

23. RAM

AD9910


0647

9-00

7

16PARALLEL

INPUT

PDCLK

SCLK

SDIO

I/O_RESET

PROFILE[2:0]

I/O_UPDATE

RAM

EX

T_P

WR

_DW

N

DAC_RSET

IOUT

IOUT

CS

TxENABLE

DAC FSC

OSKA

θ INVERSESINC

FILTER

CLOCK

AMPLITUDE (A)

FREQUENCY (ω )

PHASE (θ)

DIGITALRAMP

GENERATOR

8

DAC FSC8

2

2


SYSCLK

PLL

÷2

CL

OC

K M

OD

E

REF_CLK

REF_CLK

REFCLK_OUT

XTAL_SEL


SE

RIA

L I/O

PO

RT2 AD9910


OUTPUTSHIFT

KEYING

DATAROUTE

ANDPARTITIONCONTROL

3


ω

Acos (ω t + θ)

Asin (ω t + θ)

SY

NC

_SM

P_E

RR

SY

NC

_OU

T

SY

NC

_IN

PL

L_L

OC

K

PL

L_L

OO

P_F

ILT

ER

MA

ST

ER

_RE

SE

T

22

DDS

AUXDAC8-BIT

DAC14-BIT

RAM_SWP_OVR

DRCTL

DRHOLD

DROVER

SY

NC

_CL

K

POWER-DOWN

CONTROL

24.

( 24) DDS

(DRG)I/O

/

32 DRG 32

32 16 14MSB

( ) DRCTLDRHOLD

25.

AD9910


0647

9-00

8

16PARALLEL

INPUT

PDCLK

SCLK

SDIO

I/O_RESET

PROFILE[2:0]

I/O_UPDATE

RAM

POWER-DOWN

CONTROL

EX

T_P

WR

_DW

N

DAC_RSET

IOUT

IOUT

CS

TxENABLE

DAC FSC

OSK A

θ INVERSESINC

FILTER

CLOCK

AMPLITUDE (A)

FREQUENCY (ω )

PHASE (θ)

DIGITALRAMP

GENERATOR

8

DAC FSC8

2

2


SYSCLK

PLL

÷2C

LO

CK

MO

DE

REF_CLK

REF_CLK

REFCLK_OUT

XTAL_SEL


SE

RIA

L I/

O P

OR

T2 AD9910


OUTPUTSHIFT

KEYING

DATAROUTE

ANDPARTITIONCONTROL

3


ω

Acos (ω t + θ)

Asin (ω t + θ)

SY

NC

_SM

P_E

RR

SY

NC

_OU

T

SY

NC

_IN

PL

L_L

OC

K

PL

L_L

OO

P_F

ILT

ER

MA

ST

ER

_RE

SE

T

22

DDS

AUXDAC8-BIT

DAC14-BIT

RAM_SWP_OVR

DRCTL

DRHOLD

DROVER

SY

NC

_CL

K

( 25) DDS

18

16 MSB 16 (D[15:0]) LSB 2 (F[1:0] )16 DDS 4

16 ( DDS) 16

DDS 16FTW 32

16 FTW 324 FM

FM 16

(0) 16 FTW 32LSB FM 1 16

FTW 32 1 16FTW 2 FM

(PDCLK)

AD9910 PDCLK 1/4 DAC( ) PDCLK

PDCLK18

PDCLK PDCLKPDCLK

PDCLKPDCLK 0

AD9910

Rev. A | Page 21 of 64

4.

TxENABLETxENABLE

TxENABLEPDCLK 26

(TxENABLE)

AD9910 TxENABLETxEN-

ABLE 1 0 TxEN-ABLE TxENABLE

PDCLKPDCLK TxENABLE PDCLK

TxENABLE 18TxENABLE

()

F[1:0] D[15:0] 00 D[15:2] 14 01 D[15:0] 16 10 D[15:0] 32 11 D[15:8] 8

D[7:0] 8

0 1 − 2−14 D[1:0]

0 2π(1 − 2−16)

16 32 4 FM

MSB DDS 14 MSB DDS 6 LSBASF [5:0] 14 0 1 − 2−14

MSB DDS 16 MSB DDS 8 LSBPOW [7:0] 16 0 2π(1 − 2−16)

0647

9-00

9

FALSE

TRUETxENABLE

(BURST)

TxENABLE(CLOCK)

WORD1 WORD2 WORD3 WORD4 WORDN – 4 WORDN

PDCLK

PARALLELDATA PORT

tDS

tDStDH

tDH

26. PDCLK TxENABLE

AD9910

Rev. 0 | Page 22 of 64

DDS

/ OSK DDSI/O

DDS AD9910

5 DDS5 DDS

RAMDDS

RAM

5.

DDS

RAM RAM RAM RAM OSK OSK( )

DRG DRG DRG DRG ASF OSK

FTW

RAM RAM

FTW RAMPOW LSB

DRG DRG

FTWprofile

DRG POW RAM

FTWprofile

POWprofile

DRGASF LSB

FTWprofile

POWprofile

ASF profileprofile

(CFR2[24])

POWprofile

AD9910


DDS

(DDS)DDS CFR1[16]

DDS27

DDS 16 (POW)DDS

(Δθ)

Δθ POWFTW

DDS 14(ASF) DDS

dB3

ASF FTW

AD9910 DDS¼ fSYSCLK ¼ fSYSCLK

14 DAC

AD9910 14 DACDAC

DAC_RSET AGND(RSET) DAC

(IOUT) “ DAC”10 kΩ (RSET)

DAC

AD9910 (fOUT) DDS(FTW) fOUT FTW fSYSCLK

FTW 0 2,147,483,647 (231 − 1) 3232 dc

(½ fSYSCLK)

fOUT 1 FTW 2

round(x) xFTW fOUT

= 41 MHz fSYSCLK = 122.88 MHz FTW = 1,433,053,867 (0x556AAAAB)

FTW 231

27. DDS

0647

9-01

0

DDS_CLK

32 19FREQUENCYCONTROL

ANGLE-TO-AMPLITUDE

CONVERSION(SINE ORCOSINE)

PHASEOFFSET

CONTROL

TO DAC(MSBs)

D Q

R

ACCUMULATORRESET

32

16

MSB ALIGNED

AMPLITUDECONTROL

14

DDS SIGNAL CONTROL PARAMETERS

16

1419

32

32 14

1432-BIT

ACCUMULATOR

OUTf = SYSCLKfFTW

2 32��

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SYSCLK

OUT

ff322

OUTf = (for FTW ≥ 231) SYSCLKfFTW

21

32��

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=Δθ

��

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16

16

2360

22

POW

POWπ

=ScaleAmplitude

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14

14

220log

2

ASF

ASF

(1)

(2)

(3)

AD9910


DAC

DAC (IOUT) 8 DAC8 IOUT

RSET RSET Ω CODEDAC 8 127 RSET = 10,000ΩCODE = 127 IOUT = 20.07 mA

Sinc

AD9910 (DAC)DAC DACsin(x)/x Sinc

SincDAC Sinc Sinc

FIR SincSinc 28 Sinc

Sinc CFR1[22] 6DAC Sinc

Sinc ~3.0 dB40% DAC Sinc

28 Sinc(DAC 1/2) 4 dB

Sinc DAC SincSinc ±0.05 dB

29 Sinc Sinc

5 DDS5 DDS

RAMDDS

RAM

(REF_CLK/REF_CLK ) REF_CLK/ REF_CLK

REF_CLK/REF_CLK AD9910SYSCLK DAC REF_CLK

(PLL)REF_CLK 30

XTAL_SEL CFR3 30CFR3

��

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96CODE1

R86.4

SEToutI

6. Sinc

1, 7 −35 2, 6 +134 3, 5 −562

9276+ 4

1

0

–1

–2

–3

–44.02.01.00 5.03.0

0647

9-01

1

(dB

)

FREQUENCY RELATIVE TO DAC SAMPLE RATE

INVERSESINC

SINC

28. Sinc Sinc

29. Sinc DAC

–2.8

–2.9

–3.0

–3.14.02.01.00 5.03.0

0647

9-01

2

(dB

)

FREQUENCY RELATIVE TO DAC SAMPLE RATE

COMPENSATED RESPONSE

AD9910


REF_CLK/REF_CLK

REF_CLK/REF_CLK

REF_CLK/REF_CLK 0.1 μF

REF_CLK0.1 μF REF_CLK/REF_CLK

~1.35 V32

REF_CLK/REF_CLK ~2.5 kΩ ~1.2 kΩREF_CLK/REF_CLK

32 50 Ω

PLL PLLREF_CLK/REF_CLK

2 GHz 1 GHz

PLL REFCLK_OUTREF_CLK

REFCLK_OUT7

REF_CLK/REF_CLK

REF_CLK/REF_CLK25 MHz 31

XTAL_SEL 1 1.8V

30. REF_CLK

REF_CLK

REF_CLK

PLL

VCOSELECTDIVIDE

CHARGEPUMP

OUTIN

PLL_LOOP_FILTERENABLE

PLL_LOOP_FILTER

DRV0CFR3

[29:28]

REFCLK_OUT

XTAL_SEL

REFCLKINPUT

SELECTLOGIC

SYSCLK

ICPCFR3

[21:19]

NCFR3[7:1]

VCO SELCFR3

[26:24]

÷2

REFCLKINPUT DIVIDER BYPASSCFR3[15]

PLL ENABLECFR3

[8]

REFCLKINPUT DIVIDER

RESETBCFR3[14]

94

95 2

90

91

0

1

0

1

2

2

7 3

0

1

0647

9-01

3

7. REFCLK_OUT

DRV0 (CFR3[29:28])

0001

0111

REFCLK _ OUT

0647

9-01

4

REF_CLK

REF_CLK39pF39pF

XTAL

90

91

31.

32.

0647

9-01

5

TERMINATION

REF_CLK

DIFFERENTIAL SOURCE,DIFFERENTIAL INPUT

SINGLE-ENDED SOURCE,DIFFERENTIAL INPUT

SINGLE-ENDED SOURCE,SINGLE-ENDED INPUT

90

91

0.1μF

0.1μF

PECL,LVPECL,

ORLVDS

DRIVER

REF_CLK90

91

50�

0.1μF

0.1μF

BALUN(1:1)

REF_CLK

REF_CLK

REF_CLK

REF_CLK

90

91

0.1μF

0.1μF

50�

AD9910


(PLL)

(PLL)PLL 12×

127×PLL_LOOP_FILTER PLL

PLL PLL_LOCK

VCO PLL (fSYSCLK) 420 MHz1 GHz VCO

fSYSCLK 3334 VCO

33VCO

CFR3[26:24]

A −10°C900 MHz CFR3[26:24] 100b

B 90°C 900 MHzCFR3[26:24] 101b

33CFR3[26:24]

34VCO 34VCO

CFR3[26:24]33VCO

VCO

PLL (ICP) PLL

9

34. VCO06

479-

059

VCO0

VCO1

VCO2

VCO3

VCO4

VCO5

395 495 595 695 795 895 995

fLOW = 400fHIGH = 460






(MHz) 33. VCO

335 435 535 635 735 835 935 1035 1135

VCO0

VCO1

VCO2

VCO3

VCO4

VCO5

0647

9-06

0fLOW = 370fHIGH = 510






(MHz)

8. VCO

VCO (CFR3[26:24]) VCO

0OCV 000 1OCV 100 2OCV 010 3OCV 110 4OCV 001 5OCV 101

LLP 011 LLP 111

9. PLL

ICP (CFR3[21:19]) ICP (μA)

000 212 001 237 010 262 011 287 100 312 101 337 110 363 111 387

AD9910


PLL

PLL_LOOP_FILTER

PLL 35 PLL

PLL

PLL PLL_LOCK PLLREFCLK PLL_LOCK PLL

1 PFDPLL_LOCK PFD 0

(OSK)

OSK ( 36) DDSDDS

OSKOSK

OSK CFR1 OSK OSKOSK ASF 32

OSK OSK OSK OSK

OSK OSK0

OSK

ASF

I/O OSKOSK OSK 0

0

II PLL

(N) (KD) VCO (KV)(KV VCO1 )

(fOL) (φ)

R1= (4)

C1= (5)

C2= (6)

KD ICP KV 1

4 6 ICP9 uA KV /

(Hz/V) 1 / (MHz/V)(fOL) (Hz) (φ)

PLL ICP = 287 μA KV = 625 MHz/VN = 25 50 kHz45° R1 = 52.85 Ω C1 = 145.4 nF C2 = 30.11 nF

35. REFCLK PLL

PFD CP

PLL_LOOP_FILTER

VCO

÷N

PLL OUTPLL IN

AVDD

REFCLK PLL

2

R1

C1

C2

0647

9-01

6

��

��

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)sin(11

ϕVD

OL

KKπNf

22 )()tan(

OL

VD

πfNKK ϕ

��

��

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)( ϕϕ1

2 2OL

VD

πfNKK

0647

9-01

7

OSK ENABLE

AMPLITUDE SCALE FACTOR(ASF[15:2])

AMPLITUDE RAMP RATE(ASF[31:16])

AMPLITUDE STEP SIZE(ASF[1:0])

MANUAL OSK EXTERNAL

AUTO OSK ENABLE

OSK

DDS CLOCK

TO DDSAMPLITUDECONTROLPARAMETER

60

LOAD ARR AT I/O_UPDATE

OSKCONTROLLER

1416

14

2

AD9910


OSK

OSK

32 ASF I/OASF 16

[31:16] ASF 14[15:2] ASF

2 [1:0] /OSK

¼ fSYSCLK 16(Δt)

Δt =

M ASF (ARR) 16fSYSCLK = 750 MHz M = 23218 (0x5AB2)

Δt ≈ 123.8293 μs

OSK 14 DDSOSK 1 OSK 1 OSK (0)

OSK 0 OSK(0)

OSK 0 OSK0

OSK 1 OSK (0)

OSK OSK 0OSK (0)

OSK ASF10 14 OSK LSB

OSK ASF

16

OSK 0 1I/O OSK

ARR @ I/O 0 I/O_UPDATE

1 profile

(DRG)

DRG

AD9910DRG 9

3 2 64 3237

37.

SYSCLKf4M

(ASF[1:0])

1 00 2 10 4 01 8 11

DIGITAL RAMP LIMIT REGISTER

DR

CT

L

DDS CLOCK

DR

HO

LD

DR

OV

ER

DIGITAL RAMP RATE REGISTER

DIGITAL RAMP STEP REGISTER06

479-

018

TO DDSSIGNALCONTROLPARAMETER

DIGITAL RAMP ENABLE

DROVER PIN ACTIVE

LOAD LRR AT I/O_UPDATE

CLEAR DIGITALRAMP ACCUMULATORAUTOCLEAR DIGITAL

RAMP ACCUMULATOR64

64

DIGITAL RAMP DESTINATION2

DIGITAL RAMP NO-DWELL2

32

32DIGITALRAMP

GENERATOR

62 61 63

DDS CLOCK

D Q

R

LOWERLIMIT

0

1

DECREMENT STEP SIZE

PRESET

Q

DRCTL

LOAD

CLEAR DIGITAL RAMP ACCUMULATOR

AUTOCLEAR DIGITAL RAMP ACC.

NO DWELL

LIMIT CONTROL

DIGITAL RAMP ACCUMULATOR

INCREMENT STEP SIZE

32

32

0

1

NEGATIVE SLOPE RATE

POSITIVE SLOPE RATE

16

16

32

16

62

DRHOLD 63

32

32

LOADCONTROL

LOGICLOAD LRR AT I/O_UPDATE

DIGITALRAMPTIMER

ACCUMULATORRESET

CONTROLLOGIC

NO-DWELLCONTROL

2

3232


UPPERLIMIT

32

0647

9-01

9

AD9910


DRG DRG

DRG 32 DDSDRG 2

1132 32 16

14 MSBLSB

DRG/ DRG38

DRCTL 0 DRG1

DRG DRHOLD1 DRG

DRG

DRG DDS profile

(CFR2[21:20])

DDS DDS

00 01 31:16 1x1 31:18 1 x =

38.

10. OSK

31:0

AD9910


DRG

DRG 32DDS ¼ fSYSCLK

(+Δt) (−Δt)

+Δt=

−Δt=

P N 32 16N

P

(STEPP) (STEPN) 3264

STEPN32

STEPN STEPP M

=

=

=

=

fSYSCLK MHzDAC IFS

mA

32 16 1432

16 14

16

0 1 I/ODRCTL LRR @ I/O

“ ”

DRG

DRG64

DRG

DRG

0 00 DRG

0 “” 39

DRGDROVER DROVER

1Δt

1

DRG

SYSCLKf

4p

SYSCLKf4N

SYSCLK32 f

2��

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312Mπ

292

45 M

FSIM

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322

AD9910


1— 1 I/ODRG

2—I/O DRCTL = 1DRCTL DRGDRG DRCTL = 0 DRG

3—DRCTL 1 DRGDRCTL DRG

DRCTL = 0DRG

DRG

4—DRCTL 0 DRGDRCTL DRG

DRCTL = 1DRG

DRG

5—DRCTL 1

6—DRHOLD 1DRG

7—DRHOLD 0

8— 1 I/ODRG

9—I/O 1DRGDRG

10— 0I/O DRG

11—I/O 0

12— 1I/O DRG

13—I/O1

DDS DRG

DRCTL 1 DRG

39.

DRG OUTPUT

LOWER LIMIT

UPPER LIMIT

DRCTL

DRHOLD

AUTOCLEAR DIGITALRAMP ACCUMULATOR

CLEAR DIGITALRAMP ACCUMULATOR

I/O_UPDATE

POSITIVESTEP SIZE

NEGATIVESTEP SIZE

P DDS CLOCK CYCLES N DDS CLOCK CYCLES 1 DDS CLOCK CYCLE

DIGITAL RAMP ENABLE

DROVER

0647

9-02

0

CL

EA

R

RE

LE

AS

E

AU

TOC

LE

AR

–Δt+Δt

1 2 3 4 5 6 7 8 9

10

11

12

13

UPPER LIMIT

P DDS CLOCK CYCLES

1 2 3 4 5 6 7 8

DRG OUTPUT

LOWER LIMIT

DRCTL

POSITIVESTEP SIZE

DROVER

+Δt

0647

9-02

1

AD9910


2 DRGDRG

DRGDRG

DRG DRG

1 DRGDRG

DRCTL

DRCTL

DRCTL

DRCTL

DRCTL

DRGDRCTL

DRGDRCTL 1 0

DRGDRG

DRCTL 0 1 DRG

DRGDROVER 1

DROVER DDS

40 DRG1 I/O

DROVER 1

401— I/O

2—DRCTL 1 DRG

3—DRCTL 0 DRG

4— 1 DRGDRCTL 0

1

5—DRCTL 0 1 6 7— DRG

DRCTL

8— 1 DRGDRCTL 0

1

DRCTL 1 0 DRG

DROVER DROVER DRGDRG / DROVER 1

0DRG

DROVER DDS

40.

RAM

AD

DR

ES

S

DA

TA

QSCLK

I/O_RESET

SDIO

CS

PROFILEWAVEFORM END ADDRESS

WAVEFORM START ADDRESS

ADDRESS CLOCK


STATEMACHINE

UP/DOWNCOUNTER

SERIALI/O

PORT

2

32

10

10

U/D

3

0647

9-02

2

AD9910


RAM

RAM

AD9910 1024 × 32 RAM RAM/ RAM

I/O /RAM

RAM 8DDS

1 RAM RAMI/O profile

8 RAM profileprofile profile

10 10 16 3 RAM

profileRAM

DDS RAM/

RAM /

RAM / RAM0 RAM

1. RAM Profile 0 RAM Profile 7

2. profile RAM profile

3. RAM profile RAM( 0x16)RAM “

” 41 RAM /

RAM / /RAM I/O 32

/ RAM/

RAM profile

RAMRAM profile

I/O RAM profile RAM RAM profile

RAM ( )

RAMRAM RAM 1 RAM

PROFILE[2:0] profileRAM RAM

42 RAM

41. RAM /

13. RAM

RAM Profile RAM

000, 101, 110, 111 001 010 011 100

12. RAM

RAM

CFR1[30:29]

DDS DDS

00 31:0 01 10 31:18 11

( )31:16 ( ) 15:2 ( )

AD9910


/

16DDS

RAM profile 16

RAM profile16 M

=

(Δt)

Δt =

I/O RAM /RAM I/O

RAM 32 DDS1

RAM 32 12

RAM_SWP_OVR(RAM ) RAM_SWP_OVR

RAMRAM 0

RAM

RAM 5

RAM profile 3 RAMRAM profile RAM

profile 13

RAM

RAMPROFILE[2:0] RAM profile 32

DDS 32RAM profile 10

RAM_SWP_OVR 0

8 FSK PSK ASKRAM FSK RAM

profile RAM profile RAM32 profile

DDS

42. RAM

RAMA

DD

RE

SS

DA

TA

Q

PROFILE

DDS CLOCK

RAMPROFILE

REGISTERS

STATEMACHINE

UP/DOWNCOUNTER

3210

2

3

16

10

10

U/D

3

0647

9-02

3

WAVEFORM END ADDRESSWAVEFORM START ADDRESS

ADDRESS RAMP RATE

NO DWELLRAM MODE


M

fM

f SYSCLKDDSCLOCK

4=

SYSCLKf

MatePlayback R

4=1

31:16

0647

9-02

4



WAVEFORM END ADDRESS

1

M DDS CLOCK CYCLES


NO-DWELLHIGH = 0

NO-DWELLHIGH = 11

RAM ADDRESS

RAM ADDRESS

RAM_SWP_OVER

I/O_UPDATE

1 2 3

Δt

AD9910


profile

profile

RAM

RAMRAM DDS

DDS DDSDDS

360° 0°DDS

DDS

(BPSK) AD9910BPSK 180°

BPSK

DDS

RAM DDS

RAM

I/O profile RAMRAM profile

RAM profileRAM

RAM RAM DDS

RAM

RAM_SWP_OVR

43

profileRAM

1 (Δt) profile

43

1—I/O profileRAM_SWP_OVR 0

2— profileRAM_SWP_OVR 1

3—

profile RAM_SWP_OVR 0

43.

Profile (CFR1[20:17]) Profile

0000 profile0001 Profile 0 Profile 10010 Profile 0 Profile 20011 Profile 0 Profile 30100 Profile 0 Profile 40101 Profile 0 Profile 50110 Profile 0 Profile 60111 Profile 0 Profile 71000 Profile 0 Profile 11001 Profile 0 Profile 21010 Profile 0 Profile 31011 Profile 0 Profile 41100 Profile 0 Profile 51101 Profile 0 Profile 61110 Profile 0 Profile 7

1111

13. RAM

AD9910


1(CFR1) profile14

profile

Profile 0 profile profileI/O

44 CFR1profile 0010 RAM Profile 1

RAM Profile 0 RAM Profile 2RAM Profile 1 profile

profile /profile Δt

profile profileRAM profile RAM profile

profile 1 RAM profileRAM profile

profileprofile

PROFILE[2:0] Profile 14

profileProfile 0

Profile 0 profileprofile profile

profileprofile

AD9910


profile

1—I/O profile1 0010 RAM_SWP_OVR 0RAM Profile 0 RAM

Profile 0 Δt0 RAM Profile 0

2— RAM Profile 0RAM_SWP_OVR DDS

3— RAM Profile 0RAM Profile 1

RAM Profile 1 RAM Profile 1

Δt1



RAM Profile 2 RAM Profile 2Δt2


7— RAM Profile 2

RAM_SWP_OVER

WAVEFORM START ADDRESS 0

WAVEFORM END ADDRESS 0

1



1


1

RAM PROFILE 210


RAMADDRESS

I/O_UPDATE

Δt0

Δt1

Δt2

1 2 3 4 5 6 7

0647

9-02

5

44. Profile ( )

WAVEFORM STARTADDRESS 0

WAVEFORM ENDADDRESS 0

WAVEFORM STARTADDRESS 1

WAVEFORM ENDADDRESS 1

0647

9-02

6

1

RAM_SWP_OVER

RAM PROFILE

RAMADDRESS

I/O_UPDATE

010 0 11

1 2 3 4 5 6 7 8 9 10 11

Δt0

Δt1

1

AD9910


45. Profile

5 11— profileI/O

RAM I/O RAM RAM

Profile 08 profile RAM profile

RAM RAM DDS

PROFILE[2:1]RAM profile RAM profile

RAM RAM profile

I/O profileRAM

PROFILE0 1PROFILE0 Logic 1

RAMROFILE0

0 PROFILE00

RAM

Profile 45 profile

profile ( 1 ) 1000RAM Profile 1 RAM Profile 0

profile

1—I/O profile (1)1000 RAM_SWP_OVR 0RAM Profile 0 RAM

Profile 0 Δt0 ( RAM Profile 0)







0647

9-02

7



1

PROFILE0

RAM ADRESS

RAM_SWP_OVER

I/O_UPDATE

1 2 3 4 5 6 7 8

Δt Δt

M DDS CLOCK CYCLES

AD9910


PROFILE0

46 PROFILE0

RAM_SWP_OVR

RAM_SWP_OVR1 PROFILE00 1 RAM_SWP_OVR

1

46

1—I/O profile RAMRAM_SWP_OVR

0

2— PROFILE0 1 RAM

3— PROFILE0 1RAM_ SWP_OVR 1

4— PROFILE0 0 RAMRAM_ SWP_OVR 1

5— PROFILE0 1RAM

RAM_SWP_OVR

6— PROFILE0 0R AM

RAM_SWP_OVR

7— PROFILE0 0RAM_SWP_OVR

8—PROFILE0 1RAM

RAM_SWP_OVR 0 PROFILE0 0 1

RAM

I/O profileRAM PROFILEx

RAM profile RAM profile

RAM RAMDDS

I/O profileRAM

46.



1

Δt Δt

RAM ADRESS

RAM_SWP_OVER

I/O_UPDATE

M DDS CLOCK CYCLES

1 2 3

0647

9-02

8

AD9910


47.

PROFILERAM profile

RAM_SWP_OVR1, 0

47

1—I/O profile RAMRAM_SWP_OVR

0

2— RAM_SWP_OVR1

3— RAM_SWP_OVR0

AD9910


0647

9-02

9



1

1 2 3 4 5

RAM ADRESS

RAM_SWP_OVER

I/O_UPDATE

M DDS CLOCK CYCLES

Δt

48.

RAM

I/O profile

Profile RAM profile

RAM_SWP_OVRDDS

48

1—I/O profileRAM_SWP_OVR 0

2— profileRAM_SWP_OVR 1 DDS

3—

4— profileRAM_SWP_OVR DDS1

5—

4 5— I/O profile

AD9910


15. Profile

PROFILE[2:0] Profile

0 000 1 100 2 010 3 110 4 001 5 101 6 011 7 111

SYNC_CLK

SYSCLK

A B

NN + 1N – 1DATA INREGISTERS

DATA INI/O BUFFERS N N + 1 N + 2

I/O_UPDATE

THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B. 0647

9-06

1

49. I/O_UPDATE I/O

PROFILE

AD9910 profile8 Profile

Profile I/O(PROFILE[2:0]) profile

profileprofile 15

8 profileRAM = 0 profile

profile “ ”RAM = 1 RAM profile

profile (FSK)FSK

( 1) ( 0)(FSK) Profile 0

Profile 1

PROFILE1 PROFILE2 0 PROFILE0PROFILE0

Profile SYNC_CLK

I/O_UPDATE SYNC_CLK

I/O_UPDATE I/O

SYNC_CLKSYNC_CLK

AD9910

I/O_UPDATESYNC_CLK

DAC ( )SPI DAC

SYNC_CLK

I/O_UPDATEI/O_UPDATE

PROFILE[2:0]

49

AD9910


16.

I/O

(CFR2[15:14]) I/O

21 00 SYSCLKs 42 10 SYSCLKs 84 01 SYSCLKs 69 11 SYSCLKs

I/O

AD9910 I/O

2(CFR2) I/O

I/O_UPDATEI/O

I/O (CFR2[15:14]) 16

AD9910

DAC REFCLK

I/O0

1(CFR1) 4EXT_PWR_DWN

0I/O

0

EXT_PWR_DWN

1EXT_PWR_DWN 1

CFR1

EXT_PWR_DWN

DAC PLL VCO

I/OI/O

I/O I/OCFR2 I/O

I/O32 I/O ¼ fSYSCLK

1 1/2 1/4 1/832 I/O

fI/O_UPDATE =

A I/O 2 BI/O 32

A 0 B 0xFFFF B0x0003 I/O_UPDATE

1

B

fASYSCLK

22 +

AD9910


0647

9-05

0

SYNCGENERATOR

REF_CLK

5

SYSCLK

INTERNALCLOCKS

5

4

SYNCRECEIVER

SY

NC

GE

NE

RA

TO

RE

NA

BL

E

SY

NC

GE

NE

RA

TO

RD

EL

AY

SY

NC

PO

LA

RIT

Y

90

91

9

10

REF_CLKINPUT

CIRCUITRY

7

8

12

SYNC_IN+

REF_CLK

SYNC_IN–

SYNC_SMP_ERR

SYNCVALIDATION

DELAY

SYNCTIMING

VALIDATIONDISABLE

CL

OC

KG

EN

ER

AT

OR

SETUP ANDHOLD VALIDATION

SYNCRECEIVERENABLE

SYNCRECEIVER

DELAY

INPUT DELAYAND EDGEDETECTION

SYNC_OUT+

SYNC_OUT–

50.

SYSCLK

SYNCGENERATOR

ENABLE

SYNCGENERATOR

DELAYSYNC

POLARITY

SYNC_OUT+

SYNC_OUT–

0

1

D Q

R

PROGAMMABLEDELAY

÷16

5

9

10

9

10

LVDSDRIVER

0 647

9-05

1

51.

I/O

AD9910SYNC_Inx

50

SYSCLK

51AD9910

16_SYSCLK

OUTSYNCff =

SYNC_OUTxLVDS 50%

SYNC_OUTxSYSCLK SYNC_OUTx

SYSCLK SYSCLKI/O 5

~150 psSYNC_OUTx

( 52) (0x0A[27])

REFCLKREFCLK (

53)

AD9910


LVDSRECEIVER

PROGAMMABLEDELAY

5INTERNALCLOCKS

CLOCKSTATE

SYNC PULSE

SYSCLK

SETUP AND HOLDVALIDATION

4

Q0

RESET

Qn

DELAYED SYNC-IN SIGNAL

SYNCRECEIVER

DELAY

SYNCRECEIVERENABLE

SYNC_SMP_ERR

7

8

12

RISING EDGEDETECTOR

ANDSTROBE

GENERATOR

SYNCTIMING

VALIDATIONDISABLE

SYNCVALIDATIONDELAY

0647

9-05

2

CLOCKGENERATOR

SYNC_IN+

SYNC_IN–

52.

SYNCIN

SYNCOUT

REF_CLK

AD9910NUMBER 1 MASTER DEVICEFPGA

DATA

FPGA

DATA

FPGA

DATA

EDGEALIGNED

AT REF_CLKINPUTS

EDGEALIGNED

AT SYNC_ININPUTS.

PD

CL

K

SYNCIN

SYNCOUT

REF_CLK

AD9910NUMBER 2

PD

CL

K

SYNCIN

SYNCOUT

REF_CLK

AD9910NUMBER 3

PD

CL

K(FOR EXAMPLE AD951x)

CLOCK DISTRIBUTIONAND

DELAY EQUALIZATION

SYNCHRONIZATIONDISTRIBUTION AND

DELAY EQUALIZATION(FOR EXAMPLE AD951x)

0647

9-05

3

CLOCKSOURCE

53.

SYNC_InxLVDS

5 ~150 psSYNC_Inx

SYNC_Inx

SYSCLKSYNC_Inx

SYSCLK SYNC_Inx(

SYSCLK )( 6

) SYSCLKSYSCLK

()

AD9910 SYNC_InxSYNC_INx

AD9910


SYNC

PULSE

SYSCLK

DELAY

DELAY

CH

EC

K L

OG

IC

4SYNC VALIDATIONDELAY4

4 SYNC_SMP_ERR

SYNC RECEIVER

12

SYNC TIMING VALIDATION DISABLE

SETUPVALIDATION

HOLDVALIDATION

D Q

12

SETUP AND HOLD VALIDATION

TOCLOCKGENERATIONLOGIC

FROMSYNC

RECEIVERDELAYLOGIC

D Q

D Q

RISING EDGEDETECTOR

AND STROBEGENERATOR

0647

9-05

4

54.

( ) 533 AD9910

SYNC_INx

REFCLKREFCLK

SYNC_OUTx SYNC_INx( )

SYNC_OUT xSYNC_INx

REFCLK () SYNC_INx (

)(

)

SYSCLK SYNC_INx

( 54)

2

(4 ~150 ps )

SYSCLKSYNC_INx

SYNC_SMP_ERR ( )

SYSCLKSYSCLK 1 GHz( 1 ns)

1 2(150ps 300ps) SYNC_SMP_ERR

AD9910


AD9910

10.1 μF 0.01 μF 10 μF

3.3 V 3.3 V 1.8 V 1.8 V

3.3 V

DVDD_I/O (3.3V)( 11/15/21/28/45/56/66)

3.3 V

AVDD (3.3V)( 74 77 83)

3.3 V DAC 28 mA3.3V

1.8 V

DVDD (1.8V)( 17/23/30/47/57/64)

17 18fOUT 50 MHz 400 MHz ~5%

AVDD (1.8V)( 3)

1.8 V REFCLK (PLL)7 mA PLL

1.8 V AVDD89 92

3

PLL 3 PLL3

AVDD (1.8V)( 6)

DVDD 1.8 V

AVDD (1.8V)( 89/92)

1.8 V REFCLK 15 mA3 3 89 92

1.8 V

AD9910


MSB LSB

D7 D6 D5 D4 D3 D2 D1 D0

R/W X X A4 A3 A2 A1 A0

— I/O

AD9910

I/O

/ AD9910MSB LSB

/ (SDIO) 2-/

(SDIO/SDO) 3-(I/O_RESET CS) AD9910

I/O

AD9910( “ ” )

2( 0x01) 2 4SCLK

I/O_RESETI/O_RESET I/O

I/OI/O

AD9910 8 SCLK

I/O_UPDATEI/O

profile I/O

2

SCLK

profile (0x0E 0x15)profile profile Profile 5 (0x13)PROFILE[0:2] 101 profile

R/W— 7. 1 0

X, X— 6 5

A4, A3, A2, A1, A0— 4 3 2 1 0

I/OSCLK—

/ AD9910

CS—

CSSDO SDIO

CS (CS)SCLK

/ (SDIO)

AD9910CFR1 ( 0x00) 10 SDIO

(SDO)

AD9910 I/O

AD9910


I7SDIO

INSTRUCTION CYCLE DATA TRANSFER CYCLE

SCLK

CS

I6 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0

0647

9-03

0

55.

DO7


DON'T CAREI7 I6 I5 I4 I3 I2 I1 I0SDIO

SCLK

CS

SDO DO6 DO5 DO4 DO3 DO2 DO1 DO0

0647

9-03

156. 3

I7SDIO


SCLK

CS

I6 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0

0647

9-03

2

57.

I7SDIO


SCLK

CS

I6 I5 I4 I3 I2 I1 I0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

0647

9-03

3

58. 2

/ (I/O_RESET)

I/O_RESET I/OI/O_RESET

I/O_RESET ( 0)

/ (I/O_UPDATE)

I/O_UPDATE I/OI/O_UPDATE

1 SYNC_CLK I/O

I/O

55 58 I/OI/O

MSB/LSB

AD9910 (MSB)(LSB) 1 (0x00) 0 MSB LSB

LSBMSB

LSB( “” 17)

AD9910


17.

( ) ( ) 7 (MSB) 0 (LSB)6

1

(

)

CFR1 —

1(0x00)

31:24 RAM 00x0

OSK Sinc 0x00

15:8 LRR @ I/O

ARR @ I/O

OSKOSK

0x00

0x00 7:0 DAC REFCLK DAC SDIO LSB

CFR2—

2(0x01)

profiles31:24 0x00

23:16 I/O SYNC_CLKFTW

0x40

15:8 PDCLK PDCLK TxEnable

7:0 FM 0x20

CFR3—控制功能寄存器3(0x02)

31:24 DRV0[1:0] VCO SEL[2:0] 0x1FIcp[2:0]23:16 0x3F

15:8 REFCLK REFCLK

B

PFD PLL 0x40

N[6:0] 7:0 0x00 DAC(0x03)

0x0031:240x0023:160x0015:80x7FFSC[7:0]7:0

I/O(0x04)

0xFFI/O [31:24]31:2423:16 I/O [23:16] 0xFF 15:8 I/O [15:8] 0xFF 7:0 I/O [7:0] 0xFF

FTW—

(0x07)

0x00[31:24]31:2423:16 [23:16] 0x00 15:8 [15:8] 0x00 7:0 [7:0] 0x00

DDSprofile23:16

RAM

I/O 0x08

5 4 3 2 1

AD9910


POW—

(0x08)

00x0[15:8]15:87:0 [7:0] 0x00

ASF—

(0x09)

00x0[15:8]31:24[7:0]23:16 00x0

15:8 [13:6] 0x00

7:0 [5:0] [1:0] 0x00

0x00 (0x0A)

31:24 [3:0]

23:16 [5:0] 0x00 15:8 [4:0] 0x00 7:0 [4:0] 0x00

(0x0B) A/N[31:24]63:56

55:48 [23:16] N/A 47:40 [15:8] N/A 39:32 [7:0] N/A 31:24 [31:24] N/A 23:16 [23:16] N/A 15:8 [15:8] N/A 7:0 [7:0] N/A

(0x0C) A/N[31:24]63:56

55:48 [23:16] N/A 47:40 [15:8] N/A 39:32 [7:0] N/A 31:24 [31:24] N/A 23:16 [23:16] N/A 15:8 [15:8] N/A 7:0 [7:0] N/A

(0x0D) A/N[15:8]31:24

23:16 [7:0] N/A 15:8 [15:8] N/A 7:0 [7:0] N/A

Profile 0(0x0E)

80x00[13:8]63:5655:48 0[7:0] 0xB5 47:40 0[15:8] 0x00 39:32 0[7:0] 0x00 31:24 0[31:24] 0x00 23:16 0[23:16] 0x00 15:8 0[15:8] 0x00 7:0 0[7:0] 0x00

( ) 7 (MSB) 0 (LSB)6

1

(

)5 4 3 2 1

AD9910


RAMProfile 0(0x0E)

63:5655:48 RAM Profile 0 [15:8] 0x00

0x00

47:40 RAM Profile 0 [7:0] 0x00 39:32 RAM Profile 0 [9:2] 0x00

0x00 31:24 RAM Profile 0[1:0]

23:16 RAM Profile 0 [9:2] 0x00 0x00

0x00

15:8 RAM Profile 0[1:0]

7:0 RAM Profile 0 [2:0]

Profile 1(0x0F)

1[13:8]63:5655:48 1[7:0] 0x00

0x00

47:40 1[15:8] 0x00 39:32 1[7:0] 0x00 31:24 1[31:24] 0x00 23:16 1[23:16] 0x00 15:8 1[15:8] 0x00 7:0 1[7:0] 0x00

0x00 RAMProfile 1(0x0F)

63:5655:48 RAM Profile 1 [15:8] 0x00 47:40 RAM Profile 1 [7:0] 0x00 39:32 RAM Profile 1 [9:2] 0x00

0x00 31:24 RAM Profile 1[1:0]

23:16 RAM Profile 1 [9:2] 0x00 0x00

0x00

0x00



Profile 2(0x10)

2[13:8]63:5655:48 2[7:0] 0x00 47:40 2[15:8] 0x00 39:32 2[7:0] 0x00 31:24 2[31:24] 0x00 23:16 2[23:16] 0x00 15:8 2[15:8] 0x00 7:0 2[7:0] 0x00

0x00 RAMProfile 2(0x10)


0x00 31:24 RAM Profile 2[1:0]

23:16 RAM Profile 2 [9:2] 0x00 0x00

0x00



( ) 7 (MSB) 0 (LSB)6

1

(

)5 4 3 2 1

AD9910


Profile 3(0x11)

3[13:8]63:5655:48 3[7:0] 0x00

0x00

47:40 3[15:8] 0x00 39:32 3[7:0] 0x00 31:24 3[31:24] 0x00 23:16 3[23:16] 0x00 15:8 3[15:8] 0x00 7:0 3[7:0] 0x00



0x00 31:24 RAM Profile 3[1:0]

23:16 RAM Profile 3 [9:2] 0x00 0x00 15:8 RAM Profile 3

[1:0]

7:0 RAM Profile 3 [2:0] 0x00

0x00 Profile 4(0x12)

4[13:8]63:5655:48 4[7:0] 0x00 47:40 4[15:8] 0x00 39:32 4[7:0] 0x00 31:24 4[31:24] 0x00 23:16 4[23:16] 0x00 15:8 4[15:8] 0x00 7:0 4[7:0] 0x00



0x00 31:24 RAM Profile 4[1:0]

23:16 RAM Profile 4 [9:2] 0x00 0x00

0x00

0x00



Profile 5(0x13)

5[13:8]63:5655:48 5[7:0] 0x00 47:40 5[15:8] 0x00 39:32 5[7:0] 0x00 31:24 5[31:24] 0x00 23:16 5[23:16] 0x00 15:8 5[15:8] 0x00 7:0 5[7:0] 0x00

( ) 7 (MSB) 0 (LSB)6

1

(

)5 4 3 2 1

AD9910


RAMProfile 5(0x13)

63:5655:48 RAM Profile 5 [15:8] 0x00

0x00

47:40 RAM Profile 5 [7:0] 0x00 39:32 RAM Profile 5 [9:2] 0x00

0x00 31:24 RAM Profile 5[1:0]

23:16 RAM Profile 5 [9:2] 0x00 0x00

0x00

0x00



Profile 6(0x14)

6[13:8]63:5655:48 6[7:0] 0x00 47:40 6[15:8] 0x00 39:32 6[7:0] 0x00 31:24 6[31:24] 0x00 23:16 6[23:16] 0x00 15:8 6[15:8] 0x00 7:0 6[7:0] 0x00



0x00 31:24 RAM Profile 6[1:0]

RAM Profile 6[1:0]

23:16 RAM Profile 6 [9:2] 0x00 0x00

0x00

0x00

15:8


Profile 7(0x15)

7[13:8]63:5655:48 7[7:0] 0x00 47:40 7[15:8] 0x00 39:32 7[7:0] 0x00 31:24 7[31:24] 0x00 23:16 7[23:16] 0x00 15:8 7[15:8] 0x00 7:0 7[7:0] 0x00



0x00 31:24 RAM Profile 7[1:0]

23:16 RAM Profile 7 [9:2] 0x00 0x00

0x00



RAM (0x16) RAM [31:0] 0x00 1 N/A =

( ) 7 (MSB) 0 (LSB)6

1

(

)5 4 3 2 1

31:0

AD9910


18. CFR1

31 RAM 0 = RAM ( ) 1 = RAM ( / )30:29 RAM 12 00b28:24 23 OSK CFR1[9:8] = 10b 0 = OSK ( ) 1 = OSK OSK ( “ ” )

22 Sinc 0 = SincSinc ( ) 1 = Sinc

2120:17 profile l CFR1[31] = 1 I/O

14 0000b16 DDS 0 = DDS ( ) 1 = DDS15 LRR @ I/O CFR2[19] = 1 0 = ( ) 1 = I/OJJPDATE PROFILE[2:0]

14 0 = DRG ( )1 = DDS

I/O_UPDATE PROFILE[2:0]I/O _UPDATE

PROFILE[2:0] SYNC_CLK

13 0 = DDS ( )1 = I/O_UPDATE profile DDS

I/O 0 23( 0x000x16) 24

225 6(0x05 0x06)

0x001 CFR1

AD9910

( )

( A:B)(A) (B) 5:2

5 2 0 LSB

I/O_UPDATE profile

1 (CFR1)— 0x00

AD9910


12 0 = DRG ( )1 = DRG 1

I/O _UPDATE PROFILE[2:0] SYNC_CLK

11 0 = DDS ( ) 1 = DRG10 ARR @ I/O CFR1[9:8] = 11b 0 = OSK ( ) 1 = I/OJJPDATE PROFILE[2:0]

OSK9 OSK 0 = OSK ( ) 1 = OSK8 OSK CFR1[9] = 1 0 = OSK ( ) 1 = OSK7 I/O 0 = ( ) 1 = 6 DAC 0 = DAC ( ) 1 = DAC5 REFCLK I/O 0 = REFCLK PLL ( ) 1 = REFCLK PLL4 DAC 0 = DAC ( ) 1 = DAC3 0 = EXT_PWR_DWN ( ) 1 = EXT_PWR_DWN

21 SDIO 0 = SDIO 2 ( )

1 = I/O (SDIO) 3

0 LSB 0 = I/O MSB ( ) 1 = I/O LSB

AD9910


2 (CFR2)— 0x01

19. CFR2

31:25 24 profile CFR2[19] = 1 CFR1[31] = 1 CFR1[9] = 1 0 = ( ) 1 = profile ASF23 I/O I/O

0 = I/O I/O_UPDATE( )

1 = I/O I/O( I/OJJPDATE )

22 SYNC_CLK 0 = SYNC_CLK 0 1 = SYNC_CLK 1/4 fsysclk I/O ( )

21:20 11 00b “ (DRG)”

19 0 = ( ) 1 = 18 “ (DRG)” 0 = ( ) 1 = 17 “ (DRG)” 0 = ( ) 1 = 16 FTW

I/O

0 = FTW I/O FTW ( )

1 = FTW I/O DDS 32

15:14 CFR2[23] = 1 I/O

00 = 1 ( ) 01 = 2 10 = 4 11 = 813:12 11 PDCLK 0 = PDCLK 0

1 = PDCLK PDCLK ( )10 PDCLK 0 = PDCLK Q 1 I 0 ( ) 1 = PDCLK9 TxEnable 0 = 1 =

87 0 = DDS ( )

1 = DDS

AD9910


6 CFR2[4] = 10 = TxENABLE 0

D[15:0] F[1:0] ( ) TxENABLE 0

1 = TxENABLE 1D[15:0] F[1:0]

5 0 = SYNC_SMP_ERR ( )

1 = SYNC_SMP_ERR 0 ( )4 “ ” 0 = ( ) 1 = 3:0 FM “ ” 0000b

3 (CFR3)— 0x02

20. CFR3

31:30DRV0

29:28 REFCLK_OUT ( 7) 00b

VCO SEL

Icp

7226:24 REFCLK PLL VCO ( 8) 111b23:22 21:19 REFCLK PLL ( 9) 111b18:16 15 REFCLK 0 = ( ) 1 = 14 REFCLK B 0 = 1 = ( )13:11 10 PFD 0 = ( ) 1 =

98 PLL

N

0 = REFCLK PLL ( ) 1 = REFCLK PLL7:1 7 REFCLK PLL 0000000b

0

DAC — 0x03

21. DAC

FSC

31:87:0 8 DAC ( DAC ) 0x7F

AD9910


I/O — 0x04

I/O

22. I/O

31:0 I/O CFR2[23] = 1 32 /O( “ I/O ” ) 0xFFFFFFFF

(FTW)— 0x07

23. FTW

31:0 32

(POW)— 0x08

24. POW

15:0 16

(ASF)— 0x09

25. ASF

31:16 16 CFR1[9:8] = 11b “ (OSK)”

15:2 141:0 CFR1[9:8] = 11b “ (OSK)”

AD9910


— 0x0A

26.

31:28 4 SYSCLK SYNC_Inx(~150 ps ) 0000b

27 0 = ( ) 1 = 26 0 = ( ) 1 =

00000b

25 0 = SYSCLK ( ) 1 = SYSCLK2423:18 6 000000b

17:1615:11 5 ( ~150 ps )

10:87:3 5 ( ~150 ps ) 00000b

2:0

— 0x0B

CFR2[19] = 1 “ (DRG)”

27.

63:32 3231:0 32

— 0x0C

CFR2[19] = 1 “ (DRG)”

28.

63:32 32

31:0 32

CFR2[19] = 1 “ (DRG)”

29.

31:16 16

15:0 16

AD9910


Profile

Profile 0 Profile 7 — 0x0E 0x15

30. Profile 0 Profile 7

63:62 61:48 14 DDS47:32 16 DDS31:0 32 DDS RAM Profile 0 RAM Profile 7 — 0x0E 0x15

31. Profile 0 Profile 7 RAM

63:56 55:40 1639:30 1029:24 23:14 10

13:65 RAM 0 = RAM 1 = RAM

43 RAM 0 = 1 = 2:0 RAM 13 RAM — 0x16

RAM

32. RAM

31:0 RAM RAM Profile 0 RAM Profile 7RAM 32 (1 1024)

profile 8 I/O ( 0x0E0x015) 8 profile profile RAM

profile CFR1[31] = 1 RAM profile CFR1[31] = 0 CFR2[19] = 0 CFR2[4] = 0 profile

PROFILE[2:0] profileCFR1[31] = 1 CFR1

[20:17] ≠ 0000b profile( “RAMProfile ” )

AD9910


COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD

1

250562

7610075

51

14.00 BSC SQ

16.00 BSC SQ0.750.600.45

1.20MAX

1.051.000.95

0.200.09

0.08 MAXCOPLANARITY

VIEW AROTATED 90° CCW

SEATINGPLANE

0° MIN

7°3.5°0°0.15

0.05VIEW A

PIN 1

TOP VIEW(PINS DOWN)

0.270.220.17

0.50 BSCLEAD PITCH

1

252650

0016775

51

BOTTOM VIEW(PINS UP)

5.00 SQ*EXPOSEDPAD

0604

08-A

FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.

59. 100 [TQFP_EP] (SV-100-4) ( )

Model Temperature Range Temperature Range Package Option

AD9910BSVZ1 –40°C +85°C 100 (TQFP_EP) SV-100-4AD9910BSVZ-REEL1 –40°C +85°C 100 (TQFP_EP) SV-100-4AD9910/PCBZ1

1 Z = RoHS

AD9910


AD9910


©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

)B(80/21-0-97460D

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1 GSPS Ë 3.3 V CMOS ± ¥ 4 Õ r ï · ad9910 rev. b | page 5 of 64 Á 06479-002 16 parallel input...

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