1. Introduction2. Trends in RAMs3. Challenges to Low-Voltage(LV) RAMs4. Subthreshold-Current Reduction RAM Cells / Peripheral Circuits
5. Perspectives6. Conclusion
Trends in Low-Voltage RAM Circuits
FTFC2003, Paris, May 15 2003
Kiyoo Itoh, Hitachi Ltd.
Outline
K. Itoh, Hitachi
2
Trends in RAM Developments (R&D)
K. Itoh, VLSI Memory Chip Design, Springer-Verlag, March 2001
Mem
ory
Cap
acit
y/ch
ip (
bit
s)
16 G
1970 1980Year
256 K
1990 2000
1 G
64 M
4 M
16 K
1 K
ISSCC/VLSI Stand-alone RAMs
1832
72
DRAM
SRAM
Mem
ory
Cel
l Are
a (
m2 )
1
Year19901970 1980 2000
10,000
1,000
100
10
0.1
Full CMOS
Full CMOS
TFT load
Poly-Si load
Planar capacitor
3-D capacitor
ISSCC/VLSI Stand-alone RAMs
DRAM
SRAM
K. Itoh, Hitachi
3
Challenges to LV RAMs
K. Itoh, VLSI Memory Chip Design, Springer-Verlag, March 2001
Peripheral Circuits Leakage Reductions Compensation for speed variations due to design parameter variations / VT / (VDD –VT0), VT =VT0 (mean) + VT, Stringent control of VT Compensations for VT with internal control of VDD / VSUB
RAM Cells Leakage ReductionsTunnel Current Subthreshold CurrentShorter tREFmax (DRAM)Larger retention current (SRAM) Stable Operations Reduced Qs (= Cs VDD / 2) SEREver-increasing VT / VT
stand-alone RAM / e-RAM
RAM cell
array
DRAM
SRAM
periph.
Qs = Cs VDD/2WL
DL
Cs
VDD
0
"1"
"0"
DRAM
WL
VDD
DL
0(0)
Cs
VDD(VDD)
SRAM
DL
Qs = Cs VDD/2
K. Itoh, Hitachi
4
Soft Error Rate(SER) of RAM Cells
-particle induced SEs
Cosmic-ray neutron-induced SEs
Neutrons generate ten times as many
charges as -particles.
Impacts of Device Scaling on SEs:
For DRAM; decrease due to a large Cs
and spatial scaling (i.e.less collection).
For SRAM; increase due to decrease
in Cs despite spatial scaling.
Solutions:
Increase in Qs (= Cs·VDD/2)
C at SRAM cell node
ECC with small speed/area penalties
Purification of LSI materials
Shielding of cells with polyimide
Well structure (p+barriers, triple well)
Level keeper.
Uppsala, May3, 2001E. Ibe, The Svedberg Laboratory Workshop on Applied Physics,
0.1 1 10 100 1000
1E-5
1E-6
1E-7
1E-8
1E-9
1E-10
Memory Capacity (Mbit)
SE
R C
ross
Sec
tion
/ch
ip(c
m2 )
SRAM
DRAM
Alpha-ray
Nuclear reaction 16 f
C/
Cosmic-ray neutron
m
160
f C/
m
K. Itoh, Hitachi
5
Challenges to LV RAMs
K. Itoh, VLSI Memory Chip Design, Springer-Verlag, March 2001
Peripheral Circuits Leakage Reductions Compensation for speed variations due to design parameter variations / VT / (VDD –VT0), VT =VT0 (mean) + VT, Stringent control of VT Compensations for VT with internal control of VDD / VSUB
RAM Cells Leakage ReductionsTunnel Current Subthreshold CurrentShorter tREFmax (DRAM)Larger retention current (SRAM) Stable Operations Reduced Qs (= Cs VDD / 2) SEREver-increasing VT / VT
stand-alone RAM / e-RAM
RAM cell
array
DRAM
SRAM
periph.
Qs = Cs VDD/2WL
DL
Cs
VDD
0
"1"
"0"
DRAM
WL
VDD
DL
0(0)
Cs
VDD(VDD)
SRAM
DL
Qs = Cs VDD/2
K. Itoh, Hitachi
6
Gate Tunnel Current
D. J. Frank, 2002 VSI Circuits Symp. Short Course.
3.0
Gate Voltage (V)
Gat
e C
urr
ent
Den
sity
(A
/cm
2 )
106
105
104
103
102
101
100
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
nFETMeasurementSimulation
10 A
21.9A
0.0 0.5 1.0 1.5 2.0 2.5
15 A
20 A
25.6A
29.1A
32.2A
35.0A
36.1A
Gat
e-ox
ide
Thi
ckne
ss t
ox (
nm
)
Year
ISSCC, Symp.VLSI Circuits
2
3
45
20
30
40 50
10
100
1970 1975 1980 1985 1990 1995 2000
DRAMX 0.35/10y
MPUX 0.175/10y
M5.42.8
L
1.5V 2.75V
tunnel current
8 Mbe-DRAM
5.4
2.8
Leakage increase x 10 / 2 Å (SiO2)
Few circuitry solutions Reducing VG of MOSTs in SRAM cells Shutting off leakage with power switchNew high-k gate insulator as the final solution
K. Itoh, Hitachi
7
Subthreshold Current
tOX(SRAM) (nm)DRAM (bits)
4F (m) 0.35 0.25 0.18 0.13
tOX(DRAM) (nm) 10 7.5 6.0 4.5
64 M 128 M 256 M 512 MSRAM (bits) 4 M 8 M 16 M 32 M
5 3.75 3 2.25
0.1
1 G64 M
2
Th
resh
old
Vol
tage
VT (
V)
0
1
1.5
0.5
DRAM: tREFmax 2/GenSRAM: 1A@75C
SRAM Cell
DRAM Cell
PeripheryITRS 2001
Decreasing VT Cells; shorter tREFmax /larger Iretention Ever-higher VT to meet spec. Periphery; Leak dominates ISTB/IACT.Ever-lower VT for LP/high speed
In principle, dual VT is desired.
is W·10 -VT /S
S ~100 mV/dec.@100ºC( x10 with VT = -100mV)
VDD
0
iSW
IACT of DRAM periphery
Cu
rren
t (A
)
Capacity (bit)16M 64M 256M 1G 4G 16G 64G
10-6
10-5
10-4
10-3
10-2
10-1
100
101
1.2A
IAC
IACT
Cycle time: 180 nsT = 75C S = 97mV/dec.
IDC
VDD (V)1.01.21.53.3 2.5 2.0 0.8
Extrapolated VT at 25C (V)0.160.24 0.190.53 0.40 0.32 0.13
K. Itoh, VLSI Memory Chip Design, Springer-Verlag, March 2001
Iretention of 1-Mb SRAM
Extrapolated VT(V) @25C
Cu
rren
t (A
)
0.5
10A
102
100
10-2
10-4
10-6
10-8
10-10
10-12
100C75C
50C25C
0C
Tj
0 1.0
1A
K. Itoh, Hitachi
8
Key to Subthreshold-Current Reduction
High-Speed Scheme applicable to Active Mode
Reduction in high-speed active mode is difficult due to lack of time to control the leakage, while in slow-speed standby modeit is easy because of enough time available. Reduction scheme for active mode must be fast enough to control the leakage within one cycle of active mode. Such a scheme is also applicable to standby mode. On the contrary, slow scheme cannot be applied to active mode,even if it is applicable to standby mode. Key to High-Speed SchemeDon’t swing a large capacitance at a large voltage for fast control.If capacitance is large, swing it at the smallest voltage possible.If capacitance is small, a large voltage swing is acceptable.
K. Itoh, Hitachi
9
G-S Self-Backbias (most useful)
i1 = i2. = (VT2 – VT1) + (S/ln10) ln(W1/W2)
Reduction Ratio = i1 / i1’ = 10 /S
= W2/W1 for VT2 = VT1
M. Horiguchi et al., Symp. VLSI Circuits Dig. Tech. Papers, p.47, 1993.
SSI (Switched-S impedance,Q2) circuits
Q1
0
a: current density
i1’ = aW110-VT1/S
W1, VT1
without SSI with SSI
Q1
0
Q2
0
constant current
W2, VT2
W1, VT1
i2 = aW210-VT2 / S
i1 = aW110-( +VT1)/S
No matter how large i1’ is, it is confined to the constant current of Q2 with self-adjustment of . Adjustable reduction withW2 and VT2.
Features;Large reduction with small Fast recovery due to small Automatic reduction due to self-backbias.Reduction at = 0.2V, 0.13-m MOST;G-S backbiasing of Q1; 1/100(primary)Body Effect of Q1; 1/1.5(secondary)DIBL of Q2; 1/3(secondary) even for W1 = W2 “Stacking Effect”
K. Itoh, Hitachi
10
Static/Dynamic High-VT Schemes
In practice combination of low-actual VT and high VT is used to realize high speed with low VT/ low leakage with high VT. High-VT realization from low-actual VT
Static high VT Implantation Static VSUB Dynamic high VT G-S backbias Sub-S backbias
G-S backbias 0.2 V(1/100)VT = VT0 +
-G
D
SSub0
0
0
+
G
D
SSub0
Sub-S backbias 2.5 V ( 0.2V)VT = VT0 + = k ( + 2 2 ) k = 0.2 V1/2, 2 = 0.6 V
+
+ G
D
SSub0 0
0
G
D
SSub-
K. Itoh, VLSI Memory Chip Design, Springer-Verlag, March 2001
K. Itoh, Hitachi
11
Power Switch with Level Holder
Power switches are off after the input of low-VT circuit has been evaluated, and then the evaluated output has been held at a high-VT level-holder.
This prevents the output from discharging, allowing the switch to quickly turn on at necessary timing for preparing the next evaluation.Drawbacks; large area/large swing of switch
“Don’t swing heavily-capacitive loads at a high voltage”
T. Sakata et al., 1993 Symp. VLSI Circuits.
high-VT levelholder
VDD
OUTIN
power switch
K. Itoh, Hitachi
12
Applications to RAM Cells A dual-VT/dual-VDD/dual-tox approach for RAM cells Cells need a high VT, and thus a high VDD/thick tox for a large Qs and small itunnel. Periphery needs low-VDD/low-VT, and thus thin-tox for LP/high speed.However, this has not been widely accepted yet. Current status of leakage reduction of RAM-cells
G-S backbias to low-VT QT cutsleakage and increases read current. High-VT QD/QL reduce leakage. Boosted supply VDH offsets high-VT/VT of QD/QL, so signal charge and drivability of QD are preserved.
VDD min at SNM= 0.1V, VT= 0.1V:0.6 V at VDH –VDD= 0 V0.3 V at VDH –VDD= 0.1 V
VDD
VTlow0
VTlow- VThigh
WLDL
Cs
VDD
VDH
WL
DL
QD
QT
QL
DL
Leakage / SE issues become serious for SRAMs.
DRAM SRAM
K. Itoh et al., VLSI Circuits Symp., p.132, June 1996
K. Itoh, Hitachi
13
Sub-S Backbias, High-VT SRAM Cell
K.Osada et al. ISSCC2003 Dig. pp. 302-303
Raised-S /lowered DL at active-standby transition
1.5 V
0.5 V 1.5 V
WL 0 V
DL DL 0.5V 1.0V
VSS1.0V
0.0 V 1.5 V1.5 V
Standby
Active
G-S backbias100% reduction ofsubthreshold leakage
Electric-field relaxation90% reduction ofgate leakage & GIDL
Sub-S backbias90% reduction ofsubthreshold leakage
K. Itoh, Hitachi
14Retention Current per Cell (measured)
K. Osada et al. ISSCC2003 Dig. pp. 302-303
Conv.
Prop.
Conv.
102 fA
PMOST
1244 fA
Prop.
PMOSTNMOSTNMOST
25ºC
90ºC
Sub. + GIDL 48.5
PMOSTNMOST NMOST
95 fA
PMOST
Sub. + GIDL 1182
17 fA
Tunnel 46.5
Tunnel 62
3 14
81
VT (extrap.) = 0.7 V(N), -1 V(P)tox (electrical) = 3.7 nm
K. Itoh, Hitachi
15
Sub-S Backbias, High-VT SRAM Cell
K. Osada et al. ISSCC2003 Dig. pp. 302-303
1. Still large current for power-aware systems:1.6 A for 16Mb even if highVT/thick tox/Sub-S backbias are used.
Thus, higher VT/thicker tox are needed.2. Reduced QS in standby mode restrictslow-voltage operations.Further lowering VDD with the same voltage swing increases SER due to decreased Qs, implying that the scheme will be less effective at lower VDD.
Limitations and Challenges
1.5-V 27-ns 6.42 x 8.76 mm2 16-Mb SRAMECC with 3.2ns/9.7 % speed/area penalties
VT (extrap.) = 0.7 V (N), -1.0 V (P)
tox (electrical) = 3.7 nm
DL
0.5 V
Active Standby0V Conv.
Prop.
1.5 V
VDD(1.5V)
WLDL 1.0 V
Active StandbyConv.
Prop.
K. Itoh, Hitachi
16
Applications to Periphery (Active)
Leakage from inactive circuits must be reduced within one cycle of active mode, calling for high-speed reduction schemes.
Fortunately, periphery has favorable features to reduction.
General Features of Periphery:
Even in active mode, leakage from inactive circuits will dominate the total leakage of chip, since inactive circuits overwhelm active circuits in number, as in all CMOS LSIs.
active inactive
Periphery
(selected) (non-selected)
K. Itoh, Hitachi
17
(1) Iterative-Circuit Blocks All circuits except the selectedone are inactive.(2) Robust CircuitsNAND dec. for X/Y.No leakage-sensitive NOR.(3) Input-Predictable Logic allows to prepare reduction scheme in advance.(4) Slow Cycle (tRC =25, 60 ns)Each circuit is active only for a short period within “long” cycle, enabling additional timefor leak control.
Reduction Schemes; G-S self-backbias Multi-static VT with static VSUB application Power switch with level holder
Favorable Features of Periphery
SA
AC
75
DCDriver
695Decoder
209 69Others132drv.
16-Gb DRAM 1180mA
(Subthreshold) 1105
K. Itoh, VLSI Memory Chip Design, Springer-Verlag, March 2001.
VDH
Non
-selected
Selected
Selected WL
Selected
CS
LRowdec.
Non
-selected
WD Memory array
Selected
Non-selected
Non-selected
Col.dec.
CLK
axi
WLSelected
Non-selectedVDH
tRC
P
axiVDH 0
X
DynamicNAND
ayi
VDD
VDD 0
Y
StaticNAND
K. Itoh, Hitachi
18
Applications of G-S Self-Backbias
without SSI with SSI
i0WQ
#0
i0W
#n-1
i1 = ni
= 0Q1
0
Q2
i2
W2
W1 = nWi1 = ni
Iterative Circuit Block NAND Decoders (4-input)
K. Roy, Tutorial, 2002 Symp. VLSI Circuits.
n MOSTs in inactive circuits equivalent to one MOST with W1 = nW. Reduction ratio = W2/W1 = W2/nW
W2 W without speed penalty, because one MOST is selected. 1/n.
With a larger n, leakage/area-penalties due to Q2 are negligible ( 0, W2 « nW).
“Stacking effect” reduces leakage of non-selected decoders, althoughthe magnitude of reduction is input -dependent.
10 0.7
0
0
0
0
1
2
3
1.5
0
1.5
1.5
0
0
0
0
0
1.5
1.5
1.7
0
0
0
0
0
1.5
1
1
2
0
VT = 0.25V
nA
K. Itoh, Hitachi
19
n decoders divided into m sub-blocks, n/m decoders each. SSI connected to select each sub-block.
Standby Mode: All SSIs/dec.; off. Total leakage 0.Leakage of each sub-block 0, if W2 is small. Active Mode: Selected SSI/dec.; on. Others; off.Total leakage leakage of one selected sub-block ( i.e.,1/m).Leakage of each non-selected sub-block 0. Leakage of the selected sub-block is reduced due to“stacking effect”.
W2 W without speed penalty because one decoder is selected. Small W2 / small minimize area/ speed penalties.
-SSI at NMOS Source- m
0
0
0
selected non-selected
p
a0
a1
a2 W
VDD #0
STB ACT
0
a0
a1
a2
VDD
1
2
W20
0
0
#1 #m-1
0
0
n/m
SSI
p
n/m i 0 0
Application to NAND Dec. Block
K. Itoh, Hitachi
20
-SSI at PMOS Source- n drivers divided into m sub-blocks,n/m drivers each. SSI connected toselect each sub-block. Standby Mode: All SSIs/drivers;off. Total leakage 0 Leakage of each sub-block 0 Active Mode:Selected SSI/driver;on. Others; off.Total leakage leakage of one selected sub-block (i.e.,1/m). Leakage of each non-selected sub-block 0. W2 W without speed penalty because one driver is selected. Small W2/small minimize area/speed penalty.
e.g. 256Mb =1.5 10-3 , = 0.25V, recovery =1-2ns with W2/W = 5, n/m = 256, S = 90mV/dec.
Application to Word-Driver Block
m
VDD
#0
0
#1 #m-1
selected non-selected
WL7
i
WL0
i0
0
0
VDD
n/m iVDD
0VDD
n/m
VDD
VDD
VDD-VDD
VDD
SSI0
W
W2
STB ACT
VDD-
K. Itoh, Hitachi
21
Active-Current Reduction (16-Gb)
Conventional
1180mA
Proposed SSI, dual VT, power switch
69
SA
VDH = 1.75V, VDD = 1V, tRC = 180nsVT = -0.12V, S = 97mV/dec., 75C
AC
75
DC
Drivers695
(Subthreshold) 1105
Decoder209
Others132
75
116
41
drv.
T. Sakata et al., 1993 Symp. VLSI Circuits.
Effectiveness with an actual chip has not been verified yet, although the scheme was proposed as early as 1993.
K. Itoh, Hitachi
22
Perspectives for RAM Cells
Existing DRAMs/SRAMsSmall cells while maintaining QS at a lower VDD
Gain cells (3-T cell) to maintain vsig at a lower VDD
On-chip ECC (small/fast) to cope with reduced QS
Emerging RAMs (Non-Volatile RAMs)Attractive at low voltages; Leakage-/SE-free structuresNDRO/Non-charge-based operations
Challenges; Scalability/stability remain unsolved, as developments are at early stages.
FRAM; Stability (fatigue/imprint)MRAM; Reduction of HW that increases with scalingOUM; Reduction of proximity heating (Ovonic Unified Memories)
K. Itoh, Hitachi
23
Perspectives for Peripheral Circuits
As for memory, subthreshold current in active mode could be
reduced by improving CMOS circuits.
In fast RAMs(fast SRAMs), reduction is extremely difficult
without innovations. (Such is the case for SoC.)
New devices such as FD-SOI with smaller S-factor
Innovative LP circuits learned from “old circuits” such as Bip/BiC, E/D,
gate boost, CML, and I2L.
( Memory-rich SoC architectures to reduce no. of random logic gates.)
Per
cen
tage
of
Are
a (
)
LSTP/LOP: Low Standby/Operating Power
Year
100
80
60
40
20
02001 2007 20132004 2010 2016
LP-SOC100mm2, 0.1W
ITRS2001
Memory LOP
Logic LOP
LSTP
LSTP
L3 Cache
L3 Cache L3 Cache L3 Cache
Don Weiss, ISSCC2002, p.112.
On-chip L3 cache in MPU
Itanium™ MPU0.18-m 6-Al metalECC/redundancy24-Mb L3-SRAM1.5V, 1.2GHz
K. Itoh, Hitachi
24
Conclusion
1. Trends in LV RAMs were explained.
2. LV RAM circuits focusing on reducing leakagecurrent of cells and periphery were discussed.
3. Perspective was given with emphasis on needsfor new devices/circuits for reducing active-modeleakage currents, and high-speed NV-RAMs.
