1

Introduction

Linus SvenssonD4, linsve-7@student.luth.se

Åke ÖstmarkD4, akeost-6@student.luth.se

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Why we are here

Project called Design and Implementation of a 32-bit FPU in VHDL

Complete project presentation fpu.varulv.net

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Today's topics

Floating-Point Unit (FPU) Design of our FPU Multiplication, an example of an algorithm Normalisation and rounding Implementation in an HDL Testing of the implementation Final result Life after SMD082 Questions

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Floating-Point Unit (FPU)

A unit providing floating-point processing capabilities Konrad Zuse had a proposal for building a computer in Germany

in 1939 First commercial machine with floating-point hardware was the

IBM 704 in 1955 Professor W. Kahan

-Twenty years ago anarchy threatened floating-point arithmetic. Forming of the IEEE floating-point committee in 1977 The first chip manufactured in complains with the IEEE standard

754 were the Intel 8087 Math Coprocessor The Intel486 DX processor for the first time integrated the CPU

and the FPU architectures on one chip

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A possible place for the FPU

FPU

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Why an FPU

LAB3 SMD082Multiplication

…...bgezal $r0 posbrk #run posbrk on "a"nopbeq $v1 $r0 fmulzero #if a==0or $s0 $r0 $v0 #s0:=a's sign bitor $a0 $r0 $v1 #a0:=a's fractionor $a1 $r0 $a3 #a1:=a's exponentbgezal $r0 prenrm #run prenrm on "a"nopor $s1 $r0 $v0 #s1:=a's fractionor $s2 $r0 $v1 #s2:=a's exponentlw $a0 -8($fp) #fetch "b"bgezal $r0 posbrk #run posbrk on "b"nop…...

LAB3 SMD082 with an FPUMultiplication

fmul $v0 $a1 $a2 #Done...

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Design of our FPU

We started on a high level of abstraction Defined I/O

FPUAB C

Op

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Design of our FPU

We divided the design into smaller blocks …

FPUAB C

Op

Arithmetic Operations

AB

Op

Normalisation and Rounding C

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Design of our FPU

…until we had a low level of abstraction

Arithmetic Operations

AB Normalisation

and RoundingC

Addition/ subtraction

MultiplicationAB

Op

Division

C

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Design of our FPU

Picked an existing algorithm, or modified an existing algorithm, or designed a new algorithm

Page #

Addition/ subtraction

MultiplicationAB

Op

Division

C

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Multiplication

A = 1.11•20 = 1.75 B = 1.10•2-1 = 0.75 Iter 1

– B(0) == 0– RES := RES>>1

– RES = 0000000

Start

B(i)=1

RES:=RES>>1 i:=i+1

RES:=RES+A

Donei<3

0

1

0

1

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Multiplication

A = 1.11•20 = 1.75 B = 1.10•2-1 = 0.75 Iter 2

– B(1) == 1– RES := RES + A – RES = 1110000– RES := RES>>1– RES = 0111000

Start

B(i)=1

RES:=RES>>1 i:=i+1

RES:=RES+A

Donei<3

0

1

0

1

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Multiplication

A = 1.11•20 = 1.75 B = 1.10•2-1 = 0.75 Iter 3

– B(2) == 1– RES := RES + A – RES = 1010100– RES := RES>>1– RES = 0101010

Start

B(i)=1

RES:=RES>>1 i:=i+1

RES:=RES+A

Donei<3

0

1

0

1

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Multiplication

1 . 1 1x 1 . 1 0

0 0 01 1 1

1 1 11 0 . 1 0 1 0

signA xor signB = 0 expA + expB = -1 man = 10.1010

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Normalisation

Express the result in normalised form

Binary form Decimal form10.1010•2-1 (2.625•2-1 = 1.3125)

1.01010•20 (1.3125•20 = 1.3125)

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Rounding

The result has to many digits and must be rounded

Binary Decimal1.01010•20 (1.3125)

Identify the nearest numbers that can be represented

Binary Decimal1.01•20 (1.25)1.10•20 (1.50)

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Rounding

Four different round modes

Binary Decimal- Round to nearest 1.01•20 1.25- Round toward + 1.10•20 1.50- Round toward - 1.01•20 1.25- Round toward zero 1.10•20 1.25

- Exact 1.01010•20 1.3125

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Implementation in an HDL

A software programming language used to model the intended operation of a piece of hardware

Two languages- Verilog- VHDL

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What is VHDL

VHSIC (Very High Speed Integrated Circuits) Hardware Description Language

Created by US Department of Defence. Adopted as an IEEE standard in 1987. Latest standard is IEEE 1076 ‘93

Intended for documenting and modeling digital systems at different abstraction levels ranging from system level down to gate level

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Main language concepts

Concurrency– VHDL can describe activities that are happening in parallel

Structure, hierarchy– VHDL allows to structure a design in a hierarchical manner

Sequential statements– VHDL also allows sequential execution of statements. Just like

any other programming language

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VHDL example

if selectX = '1’ then X <= A; else X <= B; end if;

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VHDL example 2

if selectX = '1’ then X <= A; else X <= B; end if;

if selectY = '1’ then Y <= A; else Y <= B; end if;

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Speedup

Sign

Exponent

Mantissa

Sign, exponent and mantissa in parallel

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Testing - Verification

Verification– Are we building the product right?

Bottom-up integration Testing every module on its own before

integrating it into higher level modules

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Testing - Tools used

THE FPU

clk

op 00011

status 0000000 0000001

fpuCtrl

state multiplying normalizing idle

Oper. & Res.

a 00000000000000000000000000000001

b 00111111100000000000000000000000

cout 00000000000000000000000000000001 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

• ModelSim

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Testing - Tools used

• Synplify

un1_un17_done_v_2

multiply_productsign_2

ed

ed

ed

0

multiply_productsign_1

[31]

[31]

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Testing - Example

Avoid introducing new errors in verified code

A := operand_AB := operand_BC := expected_result

if result is equal to Ctest is ok

elseraise flag to indicate fault in test

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Testing - Validation

Validation– Are we building the right product?

What if we have misinterpretedthe IEEE standard 754?

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Testing - Validation

Simulate with a test bench using Modelsim Compare the simulated result with the computed result

from an UltraSparc IIi running Solaris

FPU

Testbench

Test-vectorsSimulation results

C program

Log file

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Final result

Operations - addition- subtraction- division- multiplication- square root

- ceiling- floor- fraction- float2integer- integer2float

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Final result

Round modes

- to nearest- towards +- towards - - towards zero

Exceptions

- overflow- underflow- divide by zero- inexact operation- invalid operation

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Final result

statusBox

theStatus

ClkRes etEx c UnderflowEx c Ov erflowEx c Inex ac tOpDoneEx c Inv al idOpEx c Div ideBy Zero

[ 11: 0]Ctrl [11:0]

[ 4: 0]Op[4:0]

[ 31: 0]CInt[31:0]

[ 1: 0] Ex c Integer[1:0][ 31: 0]

Cin[31:0]

TrapUnderflowTrapOv erflow

[ 31: 0]Cout[31:0]

[ 6: 0]Status [6:0]

[ 1: 0]RoundMode[1:0]

norm

theNormalizer

ClkRes etStartASignTrapUnderflowTrapOv erflowEx c Inv al idOp

[ 9: 0]AEx p[9:0]

[ 27: 0]AMan[27:0]

[ 1: 0]RoundMode[1:0]

Ex c Inex ac tOpEx c Underflow

Ex c Ov erflowDone

[ 31: 0]C[31:0]

muxer

theMuxer

PreChec k SignRoundfunc SignSqrtSignConv SignAddSignMulSignDiv Sign

[ 9: 0]PreChec k Ex p[9:0]

[ 27: 0]PreChec k Man[27:0]

[ 9: 0] Roundfunc Ex p[9:0][ 27: 0]

Roundfunc Man[27:0][ 9: 0] SqrtEx p[9:0]

[ 27: 0]SqrtMan[27:0]

[ 9: 0]Conv Ex p[9:0]

[ 27: 0] Conv Man[27:0][ 9: 0]

AddEx p[9:0][ 27: 0] AddMan[27:0][ 9: 0]

MulEx p[9:0][ 27: 0]

MulMan[27:0][ 9: 0] Div Ex p[9:0]

[ 27: 0]Div Man[27:0]

[ 4: 0] Op[4:0]

CSign[ 27: 0]

CMan[27:0][ 9: 0]

CEx p[9:0]

fpuCtrl

theFpuCtrl

ClkRes etDoneAddDoneMulDoneDivDoneNormDoneSqrtDoneConvDoneRound

[ 4: 0] Op[4:0]

StartAddAdd_Sub

StartDivStartMul

StartNormStartSqrt

StartConvStartRoundOpConv ert

Done

[ 1: 0]OpRound[1:0]

roundfunc

theRoundFunc

ClkRes etStart

[ 1: 0]Op[1:0]

[ 31: 0] A[31:0]

CSignDone

[ 9: 0]CEx p[9:0]

[ 27: 0]CMan[27:0]

conv

theConv

ClkRes etStartOp

[ 1: 0]RoundMode[1:0]

[ 31: 0] A[31:0]

CSignDone

[ 9: 0]CEx p[9:0]

[ 27: 0]CMan[27:0][ 31: 0]

CInt[31:0][ 1: 0]Ex c Integer[1:0]

sqrt

theSqrt

ClkRes etStart

[ 31: 0]A[31:0]

DoneCSign

[ 27: 0]CMan[27:0]

[ 9: 0]CEx p[9:0]

div

theDiv

ClkRes etStart

[ 31: 0] A[31:0][ 31: 0]

B[31:0]

CSignDone

[ 9: 0]CEx p[9:0]

[ 27: 0]CMan[27:0]

mul

theMultiplier

ClkRes etStart

[ 31: 0]A[31:0]

[ 31: 0] B[31:0]

DoneCSign

[ 9: 0]CEx p[9:0]

[ 27: 0]CMan[27:0]

add

theAdder

ClkRes etStartAdd

[ 31: 0] A[31:0][ 31: 0]

B[31:0]

CSignDone

[ 9: 0]CEx p[9:0]

[ 27: 0]CMan[27:0]

precheck

thePrechecker

[ 31: 0] A[31:0][ 31: 0]

B[31:0][ 4: 0]

Op[4:0]

CSignEx c Inv al idOp

Ex c Div ideBy Zero[ 31: 0]Aout[31:0][ 31: 0]

BOut[31:0][ 4: 0]

OpOut[4:0][ 9: 0]

CEx p[9:0][ 27: 0]

CMan[27:0]

Status [6:0][ 6: 0]

C[31:0][ 31: 0]

B[31:0][ 31: 0]

A[31:0] [ 31: 0]

Ctrl [11:0][ 11: 0]

Op[4:0][ 4: 0]

Res et

Clk

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Life after SMD082

Computer Architecture / DatorarkitekturSMD077, 4p, LP2

Computation Structures / Beräkningsstrukturer SMD098, 4p, LP2

Project in Digital Synthesis / Projekt i digital syntesSMD106, 8p, LP3-4

Computer Science, Advanced course / Datateknik, fördjupningskurs SMD061-3, 2-4p, LP1-4

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Questions