1 LECTURE 4. HIGH-EFFICIENCY POWER AMPLIFIER DESIGN 4.1. Overdriven Class B 4.2. Class F circuit...

1

LECTURE 4. HIGH-EFFICIENCY POWER AMPLIFIER DESIGNLECTURE 4. HIGH-EFFICIENCY POWER AMPLIFIER DESIGN

4.1. Overdriven Class B4.1. Overdriven Class B

4.2. Class F circuit design4.2. Class F circuit design

4.3. Inverse Class F4.3. Inverse Class F

4.4. Class E with shunt capacitance4.4. Class E with shunt capacitance

4.5. Class E with parallel circuit4.5. Class E with parallel circuit

4.6. Class E with transmission lines4.6. Class E with transmission lines

4.7. Broadband Class E circuit design4.7. Broadband Class E circuit design

4.8. Practical high efficiency RF and microwave 4.8. Practical high efficiency RF and microwave power amplifierspower amplifiers

2

for DC current:


0 -1 2

Is

t 1

kIs

i

1

1

1cc1 cos

sin

2

V

V

Vcc

2 0

2Vcc

t 1 -1 +1 2-1

Vcc(1+k)

v

In overdriven Class B, voltage and current waveforms have increased amplitudes with the same peak values as in conventional Class B

for fundamental voltage :

n

n

n

n

n

nVV 1

1

11

1

11ccn

2cos

sin 1

sin

sin 1

sin

2

for odd voltage components, n = 3, 5, … :

cc0 VV for DC voltage:

for fundamental current:

for odd current components, n = 3, 5, … :

2 tan

2 1

1s

0

I

I

1

1

1s1 cos

sin

I

I

n

n

n

n

n

nII 1

1

11

1

11sn

2cos

sin 1

sin

sin 1

sin

for even voltage components, n = 2, 4, … : 0 n V

3


Out-of-band impedances :

- fundamental output power

2

11

12

s cc111 cos

sin

2

IVIV

P

2 tan

2 1

1s cc

000

IVIVP - DC output power

nRI

VZ oddfor ,

2 L

s

ccn

nZ even for , 0 n

where RL is load resistance 2 tan

2

cos sin

1

1

1

2

11

1

0

1

P

P

Collector efficiency :

1 cos

1 lim

nsi lim

sin lim

10

1

1

01

1

0 111

81%

8

2

- maximum collector efficiency for square voltage and current waveforms

Analyzing on extremum gives = 88.6% for optimum angle 1= 32.4

For

4

- fundamental current component


0 2

Is

t

i

2 s

1

II

Vcc

2 0

2Vcc

t 1 -1

Vcc(1+k)

v

- fundamental voltage component when 1 0

cc1

4

VV

scc

1 IV

P - fundamental output power

scc

0 IV

P - DC output power

100% 0

1 P

P - collector efficiency

Harmonic impedance conditions:

nZ

nZI

VRZ

oddfor

even for 0

8

n

n

s

ccL1

Vcc

2 0

2Vcc

0 2

Is

t t

i v Ideal voltage and current waveforms:

5

v(t) = 2Vcc – v(t + )

4.2. Class F circuit design: quarterwave transmisssion line4.2. Class F circuit design: quarterwave transmisssion line

Cb Vcc

/4

vin

R

C0 L0

iR

x

l

0

vinc

iinc

vref

iref

iT i

v

- collector voltage

iT(t) = iT(t + ) = IRsint

i(t) = IR(sint + sint) - collector current

- transmission-line current

Assumptions for transistor:

• ideal switch:no parasitic elements

• half period is on,half period is off:50% duty cycle

Assumptions for load:

• purely sinusoidal current:ideal L0C0-circuit tuned at

fundamental

i(t) = IR sint - load current

6

4.2. Class F circuit design: quarterwave transmission line4.2. Class F circuit design: quarterwave transmission line

sinusoidal load current

collector current consisting of fundamental

and even harmonics

transmission-line current consisting of even harmonics

iR/I0

1.5

1.0

0.5

0 t,

300 240 120 60 -0.5

-1.0

-1.5

180

i/I0

3.0

2.0

1.0

0 t, 300 240 180 120 60 0 v/Vcc

1.5

1.0

0.5

0 t, 300 240 180 120 60 0

2.0

iT/I0

1.5

1.0

0.5

0 t, 300 240 180 120 60 0

rectangular collector voltage

7

For maximally flat waveforms:4.2. Class F circuit design4.2. Class F circuit design

collector current v/Vc

c

2.0

1.5

1.0

0.5

0 /2 3/2

n = 1, 3

v/Vcc

2.0

1.5

1.0

0.5

0 /2 3/2

n = 1, 3, 5

cc1 8

9 VV

cc3 8

1 VV

collector voltage

2.5

i/I0

2.0

1.5

1.0

0.5

0 /2 3/2

n = 1, 2

2.5

i/I0

2.0

1.5

1.0

0.5

0 /2 3/2

n = 1, 2, 4

01 3

4 II

02 3

1 II

Voltage harmonic components Current har-monic compo-

nents 1 1, 3 1, 3, 5 1, 3, 5, 7 1, 3, 5, …,

1 1/2 =0.500 9/16 = 0.563 75/128 = 0.586 1225/2048 = 0.598 2/ = 0.637

1, 2 2/3 = 0.667 3/4 = 0.750 25/32 = 0.781 1225/1536 = 0.798 8/3 = 0.849

1, 2, 4 32/45 = 0.711 4/5 = 0.800 5/6 = 0.833 245/288 = 0.851 128/45 = 0.905

1, 2, 4, 6 128/175 = 0.731 144/175 = 0.823 6/7 = 0.857 7/8 = 0.875 512/175 = 0.931

1, 2, 4,…, /4 = 0.785 9/32 = 0.884 75/256 = 0.920 1225/4096 = 0.940 1 = 1.000

optimum values:

optimum values:

8

4.2. Class F circuit design: second current and third voltage 4.2. Class F circuit design: second current and third voltage harmonic peakingharmonic peaking

L1

Cbypass

C2

Rout Cout

Vcc

L2

To output matching

circuit Yout

2222

1

222

outout 1

1 Im

LCLL

CLjCjY

out212out

2o

1 5

12 ,

3

5 ,

6

1CCLL

CL

, 0 9 9 1 9 1

, 0 4 1

, 0 1 1

out22022

20out1

20

222201

out22022

20out1

20

CLCLCL

LCLL

CLCLCL

0.5 1.5 2.0

S21, dB

0

10

20

30 40 1.0 f, GHz

0

Load network

Circuit parameters

Output susceptance:

Three harmonic impedance conditions:

S21 simulation (f0 = 500 MHz)

ImY1 = 0

ImY2 = ImY3 = 0

9

6 ,

2 31

1

Cbypass

Rout Cout

Vdd

To output matching

circuit

2

3

Yout

0.5 1.5 2.0

S21, dB

0

10

20

30

40 1.0 f, GHz

0

Load network

ImY1 = 0

ImYeven =

ImY3 = 0


out0

12 3

1tan

3

1

CZ

Circuit parameters:


Requires additional impedance matching at fundamental

4.2. Class F circuit design: even current and third voltage 4.2. Class F circuit design: even current and third voltage harmonic peakingharmonic peaking

10

Drain voltage and current waveforms


Class F power amplifier with lumped elements

500

24 V

300

1.5 k

100 pF

3.5 pF

Pout

1.1 pF 6 pF

10 pF

25 nH 2 pF 15 nH

3.6 nH

4.5 nH

Pin

12.5 17.5 20

efficiency, %

10

80

60

20

0 15 Pin, dBm

100

40

22.5

gain, dB 22

20

12

14

16

18

1

2

1

2

0

20

40

vd, V

0 1 2 3 t, nsec

id, A

0.7

0

f0 = 500 MHz

LDMOSFET:gate length 1.25 um

gate width 7x1.44 mm

1 - inductance Q-factor = efficiency > 82%,

linear power gain > 16 dB

2 - inductance Q-factor = 30 efficiency < 71%,

linear power gain > 14 dB

Output matching

11


500

24 V

300

1.5 k

Pout

4.5 pF

50 45

100 pF

2.5 pF

Pin

50 75

30 90

30 12

50 73

30 30

50 13

20

40

vd, V

0 1 2 3 t, nsec

0

1

id, A

12.5 17.5 20

efficiency, %

10

80

60

20

0 15 Pin, dBm

100

40

22.5

gain, dB 22

20

12

14

16

18

Class F power amplifier with transmission lines

f0 = 500 MHz



Output power - 39 dBm or 8 W

Collector efficiency - 76%

Linear power gain > 16 dB

T-matching circuit for output impedance transformation


Output matching

12

Concept of inverse Class F mode was introduced for low voltage power amplifiers designed for monolithic applications (less collector current)


- fundamental current

- fundamental voltage

0s

1 IV

P - fundamental output power

0s

0cc0 IV

IVP - DC output power

100% 0

1 P

P - ideal collector efficiency


I0

2 0

2I0

t

i

0 2

Vs

t

v

ccs

1 2

2

VV

V

0

1

4

II

nZ

nZI

VRZ

even for

oddfor 0 8

n

n

0

sL1

Dual to conventional Class F with mutually interchanged

current and voltage waveforms

13

Optimum load resistances for different classes


(B)L

(F)L

2

1

cc)invF(L

2

8

2 RR

I

VR

(B)L

1

cc)F(L

4

4 R

I

VR

1

cc)B(L I

VR

Load resistance in inverse Class F :

Load resistance in Class F :

Load resistance in Class B :

Load resistance in inverse Class F is

the highest(1.6 times larger than

in Class B)

Less impedance transformation ratio and easier matching

procedure

14

4.3. Inverse Class F: second current and third voltage 4.3. Inverse Class F: second current and third voltage harmonic peakingharmonic peaking

1

Cbypass

Rout Cout

Vdd

To output matching

circuit

2

3

4 ,

3 31

0.5 1.5 2.0

S21, dB

0

10

20

30

40 1.0 f, GHz

0

ImY1 = 0

ImY2 = 0

ImY3 =



Load network

Circuit parameters:

Requires additional impedance matching at fundamental

1

out 01

23

1 2 tan

2

1 CZ

15


500

24 V

300

1.5 k

Pout

6 pF

50 45

100 pF

2.5 pF

Pin

50 75

30 60

30 44

50 63

50 45

50 22

0

20

40

60

vd, V

0 1 2 3 t, nsec -20

1.4

2.1

0.7

0

-0.7

id, A

12.5 17.5 20

efficiency, %

10

80

60

20

0 15 Pin, dBm

100

40

22.5

gain, dB

22

20

12

14

16

18

Inverse Class F power amplifier with transmission lines

f0 = 500 MHzDrain voltage and current waveforms



Output power - 39 dBm or 8 W

Collector efficiency - 71%

Linear power gain > 16 dB

T-matching circuit for output impedance transformation

Output matching

16

500

24 V

300

1.5 k

Pout

9 pF

50 63

100 pF

2 pF

Pin

30 54

30 65

30 62

50 45

500

24 V

300

1.5 k

Pout 9 pF

50 63

100 pF

2 pF

Pin

30 54

30 60

30 62

50 45

50 83


Inverse Class F power amplifier with transmission lines

f0 = 500 MHz

Output matching

Load network with output matching

5 15 20

efficiency, %

0

80

60

20

0 10 Pin, dBm

100

40

25

gain, dB

22

20

12

14

16

18

0

20

40

60

vd, V

0 1 2 3 t, nsec -20

4

6

2

0

-2

id, A

17


RFC R

L C0

C

Vcc Vbe

vb

L0 In Class E power amplifiers, transistor operates as on-to-off

switch and ideal shapes of current and voltage waveforms do not

overlap simultaneously resulting in 100% efficiency

Unlike Class F power amplifiers analyzed in frequency domain as their voltage and current waveforms contain either in-phase or out-of-phase

harmonics, Class E power amplifiers are analyzed in time domain as their current and voltage waveforms contain harmonics having specified

different phase delays depending on load network configuration

Basic circuit of Class E power amplifier with shunt capacitance consists of series inductance L, capacitor C shunting transistor, series fundamentally

tuned L0C0 resonant circuit, RF choke to supply DC current and load R

Shunt capacitor C can represent intrinsic device output capacitance and external circuit capacitance

Active device is considered as ideal switch to provide instantaneous device switching between its on-state and off-state operation conditions

18

• transistor has zero saturation voltage, zero on-resistance, infinite off-resistance and its switching action is instantaneous and lossless


R C

iC iR i I0

RFC L

v

Vcc

C0 L0

Idealized assumptions for analysis:

• total shunt capacitance is assumed to be linear

• RF choke allows only DC current and has no resistance

• loaded quality factor QL of series fundamentally tuned resonant L0C0 -circuit is infinite to provide pure sinusoidal current flowing into load

• reactive elements in load network are lossless

• for optimum operation 50% duty cycle is used

0 2

ttv

0

2

ttd

tdv

sin RR tIti

Optimum voltage conditions across switch:

- sinusoidal current flowing into load

19


R C

iC iR i I0

RFC L

v

Vcc

C0 L0

- switch is on

0 2

ttv

0

2

ttd

tdv


0 C

td

tdvCti

0 t

tIIti sin R 0or using initial condition 0 0 i

sin R 0 II when sin sin R tIti

2 t - switch is off 0 ti tIItiС sin R 0

t

ttC

Itdti

Ctv

sin cos cos 1

RС

482.32 2

tan 1

From first optimum condition:

sin cos2

2

3

0

ttt

C

Itv

20


Optimum circuit parameters :

-1.5

-1

-0.5

0

0.5

1

1.5

60 120 180 240 300

iR/I0

t

0

0.5

1

1.5

2

2.5

0 60 120 180 240 300

i/I0

t

0 0.5

1 1.5

2 2.5

3 3.5

0 60 120 180 240 300

v/Vcc

t

R

L 1.1525

RC

1

.18360

out

2cc0.5768

P

VR

CRR

LCR

R

L

1tan tan 11

R C V1

L I1 IR

- series inductance

- shunt capacitance

- load resistance

Optimum phase angle at fundamental seen by switch :

Load current

Collector voltage

Collector current

21


Power loss due to non-zero saturation resistance

R C

RFC L

Vcc

C0 L0

R C

RFC L

Vcc

C0 L0

rsat

i(2)

1

2

i

2 +1

a

R

r

V

PrP sat

2cc

2outsat

sat 3 3

8

12

2a

a

P

20or 35.0 a where

Non-ideal switch

For nonlinear capacitances represented by abrupt

junction collector capacitance with = 0.5,

peak collector voltage increases by 20%

Power loss due to finite switching time

Nonlinear capacitance

Only 1%

22

• basic circuit of Class E power amplifier with parallel circuit consists of parallel inductance L supplying also DC current, parallel capacitor C shunting

transistor, series fundamentally tuned L0C0 resonant circuit and load R

• shunt capacitor C can represent intrinsic device output capacitance and external circuit capacitance

• active device is considered as ideal switch to provide instantaneous device switching between its on-state and off-state operation conditions


R L C

Vcc vb

C0 L0

0 2

ttv

0

2

ttd

tdv

Optimum voltage conditions across

switch:

sin RR tIti - sinusoidal current in load

23

- switch is on

0 2

ttv

0

2

ttd

tdv


0 C

td

tdvCti

0 t

2 t - switch is off 0 ti

under initial conditions

R C

iC iR

i

L v

Vcc

iL

L0 C0

0 Lcc tvVtv

sin sin Rcc

R L tItL

Vtititi

tititi RLC

sin 1

RL cc tIitdtvVLtd

tdvC

t

0 v and sin R

ccL I

L

Vi


and

24

- second-order differential equation

where

To define three unknown parameters q, and p, two optimum conditions and third equation for DC Fourier component are applied

resulting to system of three algebraic equations:


0 cos Rcc2

22

tLIVtvtd

tvdLC

cos

1 1 sin cos

2

2

2 1cc

tq

pqtqCtqC

V

tv

,/1 LCq

2

0

cc 2

1 tdtvV

412.1 q 5.1551 .211 p

and coefficients C1 and C2 are defined from initial conditionscc

R V

LIp

0 2

ttv

0

2

ttd

tdv

25

-1

0

1

120 t

iR/I0

240

-1

0

1

2.5

180

t

iC/I0

R C V1 L

I1

IX

IR

VR

244.34 tan

R

X1

I

I

0.732 R

L

RC

685.0

out

2cc 1.365

P

VR


0

1

2.5

180 t

i/I0

0

2

3.5

180 t

v/Vcc

-0.5 0

1.5

3

180

t

iL/I0


- parallel inductance

- parallel capacitance

- load resistance

Optimum phase angle at fundamental seen by switch :

Load current

Collector voltage

Collector current

Current through capacitance

Current through inductance

26

4.6. Class E with transmission lines: approximation4.6. Class E with transmission lines: approximation

49.052 tan 1 net1 jRZ

2

2 0 t

v/Vcc

3

1

3 4

RL

RFC

Vcc

Cb MESFET output l1

l2 Cout S

Znet

RL

RFC

Vcc

Cb Bipolar output l1 l2

Cout

S

90 @ 2.7 GHz

90 @ 1.8 GHz

Optimum impedance at fundamental seen by device :

Two-harmonic collector voltage approximation

• electrical lengths of transmission lines l1 and l2 should be of 45° to

provide open circuit seen by device at second harmonic

• their characteristic impedances are chosen to provide optimum inductive impedance seen by

device at fundamental

• for three harmonic approximation, additional open circuit transmission line stub

with 90-degree electrical length at third harmonic is required

( 1.5 GHz, 1.5 W, 90% )

27

Transmission-line Class E power amplifierwith parallel circuit

ωL θZ tan0

34.244 tan 1 / net1 jRZ

0.732 tan0Z

Rθ

C

Znet

TL

R TL

C

Vcc

vin

C0 L0

Cb

filter

R

C

Znet

TL

Parallel inductance is replaced by transmission line providing optimum inductive reactance at fundamental :

Optimum impedance at fundamental seen by device :

Relationship between optimum transmission line

and load parameters :

0.732 R

L whereImpedance seen by device at fundamental

Impedance seen by device at harmonics


28

Znet(0)

Znet(20)

Znet(30)

0

1

2

0.00

0.2 0.4 0.6 0.8 1.0 t, nsec

vc/Vcc

3

-1

0

1

0.00

0.2 0.4 0.6 0.8 1.0 t, nsec

ic, A

2

3

on off on

30 , 8

Cbypass

Rout Cout

3.5 V

5 pF 4 pF 50

50 12

50 , 16 10 pF

Znet

Transmission-line Class E power amplifier with parallel circuit :

example of load network of DCS1800 handset HBT power amplifier

Collector voltage

Collector current

Current flowing through collector

capacitance

• parameters of parallel transmission line is chosen to realize optimum inductive impedance at fundamental

• output matching circuit consisting of series microstrip line with two

parallel capacitances should provide capacitive reactances at second and

third harmonics


29

4.6. Class E with transmission lines: design example4.6. Class E with transmission lines: design example

1.71-1.98 GHz handset InGaP/GaAs HBT power amplifier:two-stage MMIC designed in 2001

Pout

3.5 V

Pin

Vb1

3.5 V

Bias circuit

Vb2

Bias circuit

Short mictostrip

line: 15

Shunt inductance: bondwire

Short mictostrip

line: 15

DCS1800/PCS1900:

Pout 30 dBm PAE 51 %

WCDMA:Pout = 27 dBm

ACPR = -37 dBc PAE = 38 %

3x3mmpackage

30

4.6. Class E with transmission lines: design example4.6. Class E with transmission lines: design example

28 V Vg

Z0 = 50 = 25

Z0 = 50 = 40

Pout

W = 281.44 mm L = 1.25 m

Pin = 1 W Z0 = 50 = 30

16 pF

16 pF

1 k

9 pF

9 pF

Bandwidth: 480-520 MHz

Output power: 20 W

Power gain: 15 dB

PAE: 67%

LDMOS die

Input Gate bias Output Drain supply

15 mm

30 mm

28 V single-stage LDMOSFET power amplifier module

31

0 2

ttv

0

2

ttd

tdv


R

/4

C

Vcc

v

C0 L0

L

i

iC

iR iT

iL

Cb

vT

0 sin 2

RC

2

2C

2

tItiq

td

tid - second-order differential equation

RtC 2 iti

cos Rcc

t

C IL

V

td

tdi

boundary conditions:

• sinusoidal load current

• 50% duty cycle

649.1 q 40.8- .3021 p

LCq /1 cc

R V

LIp

4.6. Class E with quarterwave transmission line4.6. Class E with quarterwave transmission line

32


1.349 R

L

RC

2725.0

out

2cc 0.465

P

VR


- series inductance

- shunt capacitance

- load resistance

Load current

Collector voltage

Collector current

Current through capacitance

Current through transmission line

0

1.5

2.5

60 180 300 t,

i/I0

-2.0

-1.0

0

1.0

2.0

60 180 300

t,

iR/I0

0

1.5

3.5

60 180 300

v/Vc

c

t,

-1.5

0

1.5

2.5

60 180 300

t,

iC/I0

0

1.0

2.0

60 180 300 t,

iT/I0

33

Optimum impedances at fundamental and harmonics for different Class E load networks


Class E with shunt capacitance

Class E with parallel circuit

Class E with quarterwave transmission line

f0 (fundamental)

Class E load network 2nf0

(even harmonics) (2n+1)f0

(odd harmonics)

C

L

R

C

L

R

C L R

C C

C L C L

C L C

34

Input load network admittance


Rout C L R

C0 L0

Zin

Device

output

0

2 1

Xin

0

in

1

1

LjRLjCjY

1 2

20

000 /1 CL

0

Im

0

d

Yd in

0 2

1

20

2

R

L

LC

1.026 0 R

L

02

0 1/ LC

Reactance compensation load network

Reactance compensation principle

1 - impedance provided by series

L0C0 resonant circuit

2 - impedance provided by parallel LC resonant circuit

• summation of reactances with opposite slopes results in constant load phase over broad frequency range

To maximize bandwidth:

Optimum circuit parameters using equations for inductance L and capacitance C in Class E mode

35


0 00

3

3

d

Bd

d

dB

Rout C L R

C0 L0

Yin

Device

output C1 L1

0

2 1

2

02

12

R

LRC

LC

0

2 8

1

4

2100

212

102

20

21

2

R

RCLLRCCL

R

LRC

L

1 5

2 0

R

L

020

1

LC

2

5 3

20

1

R

LC

121

1

CL

120 160 180

, degree

100

40

35

140 f, MHz 30

1 2

Double reactance compensation load network To maximize bandwidth:

Optimum circuit parameters using equations for inductance L and capacitance C in Class E mode

Load network phase angle

1 - single reactance compensation load network

2 - double reactance compensation load network

36


20 nH

28 V

50

1.5 k 10 nF

20 pF Pout

10 pF 10 pF

10 nF

50 nH 1 nF 64 nH

62 nH

Pin 110 nH 10 pF

300

120 160 180

efficiency, %

100

74

72

70

68 140 f, MHz

76

gain, dB

9.5

10.0

10.5

1

2

20

400

60

80

vd, V

0 3 6 9 t, nsec 0

1.0

1.5

0.5

0

-0.5

id, A

Broadband Class E power amplifier with double reactance compensation

f0 = 120…180 MHz




1 - drain efficiency > 71%

2 - power gain > 9.5 dB

Input power - 1 W

Input VSWR < 1.4

Gain flatness 0.3

Pin = 1 W

37

Typical bipolar RF Class F power amplifier

• zero-volt Class C biasing using RF choke

4.8. Practical high efficiency RF and microwave power amplifiers4.8. Practical high efficiency RF and microwave power amplifiers

Vcc

/4

Pout

C1

Pin

L2 L4

L3 C2

C4

C3

Cb

• T-type input and output matching circuits with parallel capacitance

• quarterwave transmission line in

collector to suppress even harmonics

• high-Q series LC circuit to provide high impedance conditions for harmonics

Up to 90% collector efficiency for 10 W at 250 MHz

38


Pin 50

R1

l1 Pout 50

Cb Cb

Vg Vdd

C2

L1

l2

C4

C5

ZS2 ZL2

Harmonic controlled MESFET microwave Class F power amplifier

• Class AB biasing with small quiescent current

• T-type input and output matching

circuits with parallel capacitance

• using second harmonic controlled circuits with series

50-ohm microstrip line and capacitance each at device

input and output

74% power-added efficiency for 1.4 W at 930 MHz

Input second-harmonic termination circuit is required to provide input quasi-square voltage waveform minimizing device switching time

39

High power LDMOSFET RF Class E power amplifier

• Class B with zero quiescent current

• L-type output transformer to match optimum 1.5-ohm

output impedance to 50-ohm load

• series inductance and ferrite 4:1 transformer is required to match

device input impedance

70% drain efficiency for 54 W at 144 MHz

Pin

12 nH 24 nH

Pout 50

120 pF

55 pF

MRF183

100 nH

20 V

4:1

100 pF

• required value of Class E shunt capacitance is provided by device

intrinsic 38-pF capacitance and external 55-pF capacitance

• quality factor of resonant circuit was chosen to be sufficiently low ( 5 ) to provide some

frequency bandwidth operation and to reduce sensitivity to resonant circuit parameters


40

Low voltage fully integrated MESFET Class E power amplifier


• Class AB with small quiescent current

• Class F interstage harmonic controlled circuit using two LC

resonant circuits tuned on fundamental and third harmonic

to approximate square-wave driving signal

50% power-added efficiency for 24 dBm within 800-870 MHz

• Class E load network with optimum series inductance and shunt capacitance

Pin

Pout

2.5 V

3.7 nH

50

5 nH

10 pF

1.2 nH

3.9 nH

1.5 pF

7.9 pF

3.7 nH

3.1 pF 6.2 nH 8.1 pF

7.7 pF 3.7 nH 40 pF

-0.7 V -1 V

10 k 50

40 pF 9.4 nH

• T-type output matching circuit for impedance transformation to 50-ohm load

41

225-400 MHz 28 V 20 W LDMOSFET Class AB power amplifier: simulations


Pin = 1 W

75

28 V

2.5 k 10 k 100 pF

Z0 = 30 = 69

Z0 = 50 = 50

Z0 = 30 = 41

30 pF 33 pF

Pout

8 pF45 pF

75 pF

Z0 = 30 = 33

20 nH

100 pF

W = 281.44 mmL = 1.25 m

gm = 0.6 A/VfT = 4.5 GHz

Stability

Power gain Power-added efficiency

60%

70%14 dB

12 dB

225 MHz 400 MHz400 MHz225 MHz

Date post:	22-Dec-2015
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1 LECTURE 4. HIGH-EFFICIENCY POWER AMPLIFIER DESIGN 4.1. Overdriven Class B 4.2. Class F circuit...

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