1

PDLoop Filter

1/N

RefVCO

Phase-Locked Loop

LO

2

Frequency Divider Design Example

Yu Lin

3

Frequency Divider approaches(1)

• Analog approaches– Regenerative injection-locked frequency

divider

– Basic mixer theory: fo=fin-fLO

– Examples • If fo=fLO, then fin=2fo

• If third harmonic of LO, fLO=3*fo

4

Frequency Divider approaches(2)• Digital logic approaches

– Static Logic: bistable circuit as memory – Divider/2 Examples

• Edge-Triggered DFF.

Input

Output

D

CLKQ

Q

Input

OutputD

CLKQ

Q

Q

Q

D

5

• Eg 2. JK FF– J=K=1, toggle

J

K

Q

Q

CLK

J

K

Q

Q

CLK

TH< 　 (tud1, tdd2) < T

CLK

Q

CLK

Q

tud1 tdd2

T

TH

6

Frequency Divider approaches(3)

• Digital logic approaches– Dynamic Logic– No dedicated bistable circuit– Parasitic cap between node as storage element– Compared to static approach

• Faster • Simpler implementation• Frequency has lower limit

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Design of divide/2

– SiGe BiCMOS – Dynamic frequency divider– Input frequency: 40GHz– +/-20% input frequency range (32GHz~48GHz)– Work from 0 C to 100 C at 40GHz– Input 200mv – Output 200mV

Reinhold, M.; Dorschky, C.; Rose, E.; Pullela, R.; Mayer, P.; Kunz, F.; Baeyens, Y.; Link, T.; Mattia, J.-P., A fully integrated 40-Gb/s clock and data recovery IC with 1:4 DEMUX in SiGe technology, Solid-State Circuits, IEEE Journal of Vol.36,  Issue 12,  Dec. 2001 Page(s):1937 - 1945

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90.5T< 　 (tud1, tdd2) < T

Cin

Cin

2C

2C

3C

3C

4C

4C

5C

5C

tdd1tud2

T

10

• Four-phase clock• Fully differential• 0C or 90C phase-shifted

Cin

Cin

2C

2C

3C

3C

4C

4C

5C

5C

tdd1tud2

T

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Design key points• Find optimal current density for highest ft

• Choose appropriate current for the current sources• Choose appropriate resistors to set up good quiescent

points• Appropriate resistance and parasitic capacitance, delay

time (tdd1 and tud2) around 0.75*T

GHzf

GHzf

7.26

104075.0*2

1

3.53

104075.0

1

9

min

9

max

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Design key points(2)• Resistances are related to the quiescent point and input

frequency range, key point of robust design• Added buffer to do level shifting, improve the driving

capability and adjust gain • Driving capability increases when increase the current

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Simulation results(1)

The output of divider core at 27°C with normal model with 28G Hz input

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Simulation results(2)

The output of divider core at 27°C with normal model with 40G Hz input

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Simulation results(3)

The output of divider core at 27°C with normal model with 53G Hz input

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Simulation results(4)

Frequency range (GHz)

Slow Normal Fast

0C 26-55 29-55 39-76

27C 27-51 28-53 36-70

100C 27-42 24-44 33-56

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VCO Design Example

Chao Su

Chao Su; Thoka, S.; Kee-Chee Tiew; Geiger, R.L., A 40 GHz modified-Colpitts voltage controlled oscillator with increased tuning range, ISCAS '03. Proceedings of the 2003 International Symposium onVolume 1,  25-28 May 2003 Page(s):I-717 - I-720 vol.1

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A system with characteristic

If

It will oscillate at

0012

23 asasas

)0,0,0( 210

210

aaa

aaa

2

010 a

aa

19

Basic Colpitts VCO

023

CCL

g

CCL

LGgCCs

CCL

CCGLss

L

m

L

pmL

L

Lp

CC

LGgCCCCGg

L

pmLLpm

Oscillate when

Assume for inductor

pLGQ

0

1

11

3

1

2

Q１

ＬＣωＱ

ωＣg

Ｌ２Ｔ

２

ＴＬm

C

gmTWhere

Then

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• For given L, gm, C, – Wide frequency range can be obtained with high Q

by tuning CL

– High Q can be achieved with reduction of effective GP

CC

Qg

CCLG

g

CLC

LGgCC

L

m

Lp

m

L

PmL

00

CC

Qg

L

m

0

21

Modified Colpitts Circuit

• Achieve negative resistance by cross-coupled BJT

22

23

Simulation results

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Divide/2 Modified Colpitts VCO

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Measurement Results

• Three VCOs with three different inductors

• fVCO=(28~31GHz)

• fd/2=(14.8~16GHz)

• Tuning range smaller compared to simulation