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13/Aug/2013

13/Aug/2013

Dr. Eric Kuo Eric_Kuo@gemteks.com

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Acknowledgement

The author would like to specially thank Dr. Ching Ku Liao, who

works for MediaTek, for many useful advises in EM and transient

co-simulation

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Acknowledgement

The author would like to specially thank Christ Lin and Eric Chen,

who work for Graser, for many kindly help in Sigrity Installation

and Settings.

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Root Cause of PI

Lv V=LvdI/dt LvCharge

Discharge

IN OUT

L V=L dI/dt L

CPU/DSP/Switching chip are the class oflow-voltage high current applications

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Z-Profile of PWR/GND Planes

@ DC Open

ICapacitivebehavior before

GND

HF Behave as ca acitive

PWR F PDN DC Z I Z I 1

GND

VdispVdd +/-5%Vdd

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Resonance/Anti-resonance

-

V

no matter how large the current is, there is no voltage drop

No reliability issue

nt -resonance approac es to n n tyEven very small current will drive an huge voltage drop

Reliability issue

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Equivalent Ckt of PDN

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Target Impedance Estimation

From the data sheet of the switching circuit, the consumedpower and applied voltage are usually given, hence

P

V max

The average current is assumed to be 50% of the,

%50 I

Z T

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Bypass/Decoupling Capacitors

Switching circuit requires current to charge the load If the output impedance is too high, then VRM is unable to

respond well (VRM output impedance exceeds the desiredimpedance)

External capacitors store charge. They bypass the VRM

and supply the current to the switching circuit The bypass capacitors are also called decoupling

capacitors (decouple the VRM from the switching circuit)

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ESR & ESL of the Decoupling Capacitor

ESR

ESL

Decap C

Equivalent circuit of

decou lin ca acitor

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Z-Profile of Decoupling Capacitor

Capacitive Inductive

-20dB/decade +20dB/decade

Shunt Modelerm na e w

Series ModelESR

GNDIdeal Cap

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Decoupling Capacitors

Decouple the VRM from the switching circuit Provides a low impedance path

VRM Bulkcapacitors

decouplingcapacitors

PCBplanes

Low frequency High frequency

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Ultra Low Impedance Measurement

1-Port Measurement

111 S Impedance of PDN is usually much smaller than 50~0

111 S 11

It makes the Z cannot be slow enough

2-Port Measurement

S 12

11 1 S

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Example 1

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Calculated Z-Profile

Bare board

Area: Ad =10 mil5 cm

C = r A/d = 8.854*10 -12 F/m*4.2*0.05 2 m 2/ (10/40 * 10 -3 m) = 372 pF

At 300 kHz, Zc = 1/( C) = 1.426*10 3

De-Cap: 1uF

At 300 kHz, Zc = 1/( C) = 0.5305

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Measurement: Bare Board

Simulation w/ transmission line effect

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Measurement: Bare Board De-embedded

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Measurement: Board W/ Decap

Simulation w/ transmission line effect

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Measurement:Board W/ Decap De-embedded

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Example 2: DDR3-1600

U101

VRM

U201 U204

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Target Impedance Estimation

In data sheet, the I max = 210mA The swing is from 1.4V to 1.6V

(ripple is +/- 6.67%) Hence the target impedance can be calculated as

957.0067.05.1rippleVdd

Z 21.05.0%50 max I

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CorrelationUltra Low Impedance Measurement

2125 S

Z 2-Port measurement to capture the ultra low impedance

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ESL & ESR Effect

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Z-Profile @ U101, U201, and U204

400 MHz

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DQ1 Only: Write

DQ1

VDD RAMW/ Decap

VDD @ RAM

ecap

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All DQ: Write

VDD swing from 1.42 ~ 1.55, within the spec (1.5 +/- 6.67%)

ll d

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All DQ: Read

VDD swing from 1.45~ 1.55, within the spec (1.5 +/- 6.67%)

C l i

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Conclusions

Target impedance is the main parameter to design thepower plane

Ultra-low impedance measurement and proper embeddedtechnique should be applied to obtain the good correlation Sigrity PowerSI and SystemSI provides an user-friendly

workflow to speed up the design flow

R f

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References

M. Swaminathan and A. E. Engin, Power integrity modelingand design for semiconductors and systems , NJ: Prentice-

, Agilent ultra-low impedance measurements using 2-portmeasuremen , app ca on no e,