1 Shaorui Li, Jie Ma, Gianluigi De Geronimo, Hucheng Chen, and Veljko Radeka Brookhaven National Laboratory, NY, USA LAr TPC Electronics CMOS Lifetime at 300K and 77K Outline: 1. Overview of basics on hot-carrier effects and lifetime. 2. CMOS Lifetime due to aging in TSMC 180nm: A. CMOS lifetime in dc operation: analog front-end ASIC ; B. CMOS lifetime ac operation: logic circuits and FPGAs. 3. Thermal Cycling 4. Future R&D Needs: Commercial FPGA and regulators
Transcript
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Shaorui Li, Jie Ma, Gianluigi De Geronimo, Hucheng Chen, and Veljko Radeka
Brookhaven National Laboratory, NY, USA
LAr TPC Electronics CMOS Lifetime at 300K and 77KLAr TPC Electronics CMOS Lifetime at 300K and 77K
Outline:1. Overview of basics on hot-carrier effects and lifetime.2. CMOS Lifetime due to aging in TSMC 180nm: A. CMOS lifetime in dc operation: analog front-end ASIC ; B. CMOS lifetime ac operation: logic circuits and FPGAs.3. Thermal Cycling4. Future R&D Needs: Commercial FPGA and regulators
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• Motivation: Low noise multiplexed readout of noble liquid detectors for neutrinos, nucleon decay, dark matter, double beta decay, in particular for very large liquid argon Time Projection Chambers (TPCs).
• The goal: A continuous and unattended cryogenic operation for a long time (>10-20 years).
• Electronics for noble liquid TPCs: It is known that CMOS operation at cryogenic temperature (~-200C) offers considerable advantages as compared to room temperature operation, with respect to speed, transconductance/drain current ratio (subthreshold slope) and noise.
• The key question: How is the lifetime of CMOS affected by cryogenic operation?
IntroductionIntroduction
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10-6 10-5 10-4 10-3 10-2 10-1 100 101 1020
20
40
60
80
100
120 MEASURED
NMOS PMOS T=300K L=360nm L=270nm L=180nm
NMOS PMOS T=77K L=360nm L=270nm L=180nm
gm/I D
[V-1]
Drain Current Density [mA/mm]
CMOS018
Design region (approx.) for low power and low noise at 77K (moderate inversion): gm increase by a factor of ~2.
Static Characteristics: Lower Power at 77KStatic Characteristics: Lower Power at 77K
K77Tat116~
K300Tat30~
Tnk
q
I
g
BD
m
Favorable for cryogenic operation:
• higher gm -> lower noise
• higher gm/ID -> lower power
Asymptotic value at weak inversion:
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• Most failure mechanisms (e.g. electromigration, stress migration, time-dependent dielectric breakdown, and thermal cycling) are strongly temperature dependent and become negligible at cryogenic temperature.
• The only remaining mechanism that may affect the lifetime of CMOS devices at cryogenic temperature is the degradation (aging) due to channel hot carrier effects (HCE).
• The degradation mainly concerns NMOS devices - PMOS usually exhibits a lifetime much longer than NMOS.
• Lifetime due to HCE aging: A limit defined by a chosen level of monotonic degradation in e.g., drain current, transconductance. The device “fails” if a chosen parameter gets out of the specified circuit design range. This aging mechanism does not result in sudden device failure.
• The lifetime due to HCE at both the cryogenic temperature, as well as at room temperature, is limited by a predictable and a very gradual degradation (aging) mechanism which can be controlled or avoided by device design and operating conditions. In this study we have been following the basics established in the literature, e.g., Hu et al. (1985), and the practices adopted more recently by Chen&Cressler et al. (2006), as well as by industry.
IntroductionCMOS Lifetime at Cryogenic TemperaturesCMOS Lifetime at Cryogenic Temperatures
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• Some hot electrons exceed the energy required to create an electron-hole pair, , resulting in impact ionization. Electrons proceed to the drain. The holes drift to the substrate. The substrate current,
(1)• A very small fraction of hot electrons exceeds the energy required to create an interface state (e.g., an acceptor-like trap), in the Si-SiO2 interface, , for electrons (~4.6eV for holes). This causes a change in the transistor characteristics (transconductance, threshold, intrinsic gain). The time required to change any important parameter (the changes in different parameters are correlated) by a specified amount (e.g., gm by -10%) is defined as the device lifetime. It can be calculated as,
(2)
Overview of Basics on Hot-Electron Effects and NMOS LifetimeOverview of Basics on Hot-Electron Effects and NMOS Lifetime
1.3i eV
3.7it eV
1i mq E
sub dsI C I e
2it mq E
ds
WC e
I
q = electron chargeλ=electron mean free path
Em= electric field
Ids= drain-source current
W= channel width
C1, C2 - constants
• It has been widely recognized that Isub is a monitor for all hot-electron effects and it is the best predictor of device lifetime, because both observable hot electron effects (electrical and optical) are driven by a common driving force –the maximum channel electric field Em , which occurs at the drain end of the channel.
• The substrate current is connected to the lifetime (defined by any arbitrary but consistent criterion) by
(3) 1
ds a
sub ds
I WI I
2.9 3.2
1.3 ; 3.7 4.1
it
i
i it
a
eV eV eV
~
~ ~
dsatdsm VVE
6
• Commercial technologies are rated > 10 years lifetime (10% gm shift) at T = 300 K, L = Lmin, VDS = nominal VDD+5%, VGS ≈ VDS/2
• Degradation is due to impact ionization:
→ shift in Vth and gm
Basics of Hot Carrier Effects Basics of Hot Carrier Effects
• Substrate current is a monitor of impact ionization• increases steeply with drain voltage
• has a broad maximum at VGS ≈ VDS/2
• A lower temperature results in increased mean free path λ increasing the substrate current Isub and gm degradation. Degradation is independent of temperature if the product λ(VDS – VSAT) is kept constant.
• Accelerated lifetime test (well-established by foundries): transistor is placed under a severe electric filed stress (large VDS), to reduce the lifetime due to hot-electron degradation to a practically observable range, by a drain source voltage considerably higher (~80%) than the nominal voltage (1.8V for Lmin=180nm).
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Stress Test Flow Chart and Layout of test NMOS transistorsStress Test Flow Chart and Layout of test NMOS transistors
Test transistors, NMOS L=180nm, W=10µm (5 fingers x 2µm), designed to have negligible IR drop and power dissipation <15mW in stress tests to prevent temperature change due to self-heating.
CMOS in dc Operation: Analog Front-End ASICCMOS in dc Operation: Analog Front-End ASIC
• The measured points at both 300K and 77K are very close to the characteristic slope for the interface state generation,
0.1 0.2 0.3 0.4 0.5 0.61E-5
1E-3
0.1
10
1000
100000
1E7
1E9
*I D
S/W
(s*
A/
m)
1/VDS
(V-1)
3.2, 3.1, 3.0, 2.8 V
1.8V
Lifetime ~ 3200 yrs at Vds=1.8V, 77K
1.7V
300K
77K
Vds<1.8V
dsatdsm
itds
VVEqW
I
1
ln
ASIC design: Vds<1.5V
• The projected lifetime at 300K is ~ an order of magnitude longer than at 77K. Reducing Vds at 77K by ~ 6% makes the lifetime equal to that at 300K. Design at
low Ids/W for even longer lifetime.
3it ia
9
0 1 210-14
10-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
Isu
b/W
[A
/m]
1/Vds [1/V]
300K 77K
NMOS L=180nm, W=10µm (5x2µm), Vgs=1V
Stressed lifetime=798s at Vds=3.2V, 77K
Stressed lifetime=8506s at Vds=3.2V, 300K
Vds=1.8V
Lifetime ~ 5500 yrs at Vds=1.8V, 77K
ASIC design: Vds<1.5V
Measurement Type II: Substrate Current Density Isub /W vs 1/Vds
3subI
• One order of magnitude in substrate current Isub corresponds to three orders of magnitude in lifetime. At 77 K, Vds = 1.8 V projects a lifetime of ~5500 years.
L=360 nm; -”- ; Ids/W=1.0µA/µmL=9 µmL=270 nm
L=270 nm; Vds=1.5V; Ids/W=2.4µA/µm
L=9 µm
Isub
/W (
A/ m
)
1.5V 1.0V 0.5V 0 2 4 6
1E-20
1E-19
1E-18
1E-17
1E-16
1E-15
1E-14
1E-13
1E-12
1E-11
1E-10
1E-9
1E-8
1/Vds (1/V)
L=360 nm; -”- ; Ids/W=1.0µA/µmL=9 µmL=270 nm
L=270 nm; Vds=1.5V; Ids/W=2.4µA/µm
L=9 µm
Isub
/W (
A/ m
)
1.5V 1.0V 0.5V 0 2 4 6
1E-20
1E-19
1E-18
1E-17
1E-16
1E-15
1E-14
1E-13
1E-12
1E-11
1E-10
1E-9
1E-8
0 2 4 61E-20
1E-19
1E-18
1E-17
1E-16
1E-15
1E-14
1E-13
1E-12
1E-11
1E-10
1E-9
1E-8
1/Vds (1/V)
• Isub/W and 1/Vds distribution for all transistors in the analog front-end ASIC for LAr TPC (TSMC 180nm, 1.8V node) shows that all transistors are well below nominal voltage of 1.8V and at low Isub; Reduced Vds < 1.5 V results in essentially making HCE negligible and a very long extrapolated life time.
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101 102 103 104 105 106 107 10810-9
10-8
10-7
10-6
10-5
10-4
pre stress post stress
6000 s -> 10% gm degradation
Eq
uiv
ale
nt
inp
ut
no
ise
[V
/sq
rt(H
z)]
Frequency [Hz]
101 102 103 104 105 106 10710-9
10-8
10-7
10-6
10-5
10-4
Eq
uiv
ale
nt
inp
ut
no
ise
[V
/sq
rt(H
z)]
Frequency [Hz]
pre stress post stress
12960 s -> 2% gm degradation
Noise Degradation: Less Degradation in PMOS Noise Degradation: Less Degradation in PMOS
NMOS L=180nm, W=10µm (5x2µm)
• PMOS: much less degradation than NMOS • PMOS is used in the preamp input and, by design, it is the main noise
contributor in the front-end ASIC.
PMOS L=180nm, W=10µm (5x2µm)
101 102 103 104 105 106 107 10810-9
10-8
10-7
10-6
10-5
10-4
10-3
Eq
uiv
ale
nt
Inp
ut
no
ise
[V
/sq
rt(H
z)]
Frequency [Hz]
pre stress post stress
920 s -> 10% gm degradation post stress
3900 s -> 15% gm degradation
101 102 103 104 105 106 10710-9
10-8
10-7
10-6
10-5
10-4
pre stress post stress
1500s stress -> 2% degradation of gm post stress
5000s stress -> 3.5% degradation of gm
Eq
uiv
ale
nt
inp
ut
no
sie
[V
/sq
rt(H
z)]
Frequency [Hz]
300 K 300 K
77 K 77 K
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CMOS Lifetime in AC Operation: Logic Circuits and FPGAsCMOS Lifetime in AC Operation: Logic Circuits and FPGAs
• Long established (e.g. Quader&Hu et al.(1994), White&Bernstein (2006)] and adapted by foundries: considering the ac stress as a series of short dc stresses, each for effective stress time teff during the switching cycle, strung together.
• The lifetime of digital circuits (ac operation) is extended by the inverse duty factor 1/(fck teff ) compared to dc operation. This factor is large (>100) for deep submicron technology and clock frequencies (up to 200 MHz) which may be needed for the TPC readout.• Design guidelines for digital circuits and FPGAs: Keep the inverse duty factor 1/(fck teff ) high . Additionally, reducing Vds by 10% adds an order of magnitude margin to the lifetime.
• Rough estimation of teff [Quader&Hu et al. (1994)]:
-1/4 of the gate voltage rise time for NMOS
-1/10 of the gate fall time for PMOS
More detailed estimation can be found in the design manuals of major foundries. An accurate estimation requires a calculation of the substrate current during the change of state.
Quader&Hu et al. (1994)
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Thermal Cycling of FE ASICs and FE Boards (for MicroBooNE)Thermal Cycling of FE ASICs and FE Boards (for MicroBooNE)
Cold motherboard with 12 ASICs populated. During extensive testing of ASICs and the motherboard, ASICs have gone through ~2200 immersions (of multiple chips) in LN2, the board has been immersed ~40 times without a single failure.
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• FPGA Lifetime: a standard method is to observe ring oscillator frequency under severe Vds stress [Wang et al. 2006], as degradation of Ids leads to increased rise (propagation) time and reduced ring oscillator frequency. Needs further R&D.
• Regulators for cryogenic operation: 1.2 V and 2.5 V for FPGA, and 1.8 V for LAr ASICs. Selected 3 baseline devices, Globaltech GS2915L18F, TI TPS74201/74401, from a total of 19 devices (from ADI, Intersil, Linear, Maxim, National) tested.
Cold longtime experiment: Globaltech GS2915L18F tested >2 years; TI TPS74201/74401 will start soon. Needs further R&D on lifetime.
Future R&D Needs: Commercial FPGA and RegulatorsFuture R&D Needs: Commercial FPGA and Regulators
• FPGA candidates for cryogenic operation:
List of FPGA screening tests: configuration (JTAG & Active Serial), embedded memory, high speed transceiver, I/O interface.
✔
✔✔
✗
Vendor Family Technology Speed of GTX [Gbps]
# of GTX Memory [Mbit]
Core Voltage
[V]
Status
Altera Arria GX 90 nm 3.125 4-12 1.2-4.5 1.2 Tested by BNL
Altera Arria II 40 nm 6.375 8-24 2.9-16.4 0.9 Tested by BNL
Altera Stratix II GX 90 nm 6.375 4-20 1.4-6.7 1.2 Tested by SMU
Altera Cyclone IV E 60 nm n/a n/a 0.3-3.9 1.0, 1.2 Tested by BNL
Altera Cyclone IV GX 60 nm 3.125 2-8 0.5-6.5 1.2 Tested at BNL
Altera Cyclone V 60 nm 3.125 2-8 0.5-6.5 1.2 Tested by BNL
Principal Findings and Design GuidelinesPrincipal Findings and Design Guidelines
1.1. Two different measurements were used: accelerated lifetime measurement under severe electric field stress by the drain-source voltage (Vds), and a separate measurement of the substrate current (Isub) as a function of 1/Vds. The former verifies the canonical very steep slope of the inverse relation between the lifetime and the substrate current , , and the latter confirms that below a certain value of Vds a lifetime margin of several orders of magnitude can be achieved for the cold electronics TPC readout.
1.2. Lifetime of digital circuits (ac operation) is extended by the inverse duty factor 1/(fck teff ), compared to dc operation. This factor is large (>100) for deep submicron technology and clock frequency needed for TPC. As an additional margin, Vds may be reduced by ~10%.
2. PC boards, packages, hybrids: Extremely low failure rate (incidence) in ATLAS LAr and NA48 LKr calorimeters, over a long time scale demonstrates on a large scale that surface mount circuit board technology withstands very well even multiple abrupt immersions in LN2 applied in board testing, and that the total failure incidence in continuous operation over time, ranging from 6 to13 years so far, is very low.
-3subτ I
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References (only a few key references, among numerous references on the subject, are given here):
References (only a few key references, among numerous references on the subject, are given here):
1. S. Li, J. Ma, G. De Geronimo, H. Chen, and V. Radeka, “LAr TPC electronics CMOS lifetime at 300 K and 77 K and reliability under thermal cycling,” IEEE Trans. Nuclear Science, vol. 60, no. 6, pp. 4737-4743, Dec. 2013.
2. G. De Geronimo, A. D’Andragora, S. Li, N. Nambiar, S. Rescia, E. Vernon, H. Chen, F. Lanni, D. Makowiecki, V. Radeka, C. Thorn, and B. Yu, “Front-end ASIC for a liquid argon TPC,” IEEE Trans. Nuclear Science, vol. 58, no. 3, pp. 1376-1385, June 2011.
3. J. R. Hoff, R. Aroar, J. D. Cressler, G. W. Deptuch, P. Gui, N. E. Lourenco, G. Wu, and R. J. Yarema, “Lifetime studies of 130 nm nMOS transisors intended for long-duration, cryogenic high-energy physics experiments,” IEEE Trans. Nuclear Science, vol. 59, no. 4, pp. 1757-1766, Aug. 2012.
4. C. Hu, S. C. Tam, F.-C. Hsu, P.-K. Ko, T.-Y. Chan, and K. W. Terrill, “Hot-electron-induced MOSFET degradation-model, monitor, and improvement”, IEEE Journal of Solid-State Circuits, vol. sc-20, no. 1, pp. 295-305, Feb. 1985.
5. T. Chen, C. Zhu, L. Najafizadeh, B. Jun, A. Ahmed, R. Diestelhorst, G. Espinel, and J. D. Cressler, “CMOS reliability issues for emerging cryogenic Lunar electronics applications,” Solid-State Electronics, vol. 50, pp. 959-963, 2006.
6. V.-H. Chan and J. E. Chung, “Two-stage hot-carrier degradation and its impact on submicron LDD NMOSFET lifetime prediction”, IEEE Tran. Electron Devices, vol. 42, no. 5, pp. 957-962, May 1995.
7. K. K. Ng and G. W. Taylor, “Effects of hot-carrier trapping in n- and p-channel MOSFET’s”, IEEE Tran. Electron Devices, vol. ed-30, no. 8, pp. 871-876, Aug. 1983.
8. P. K. Hurley, E. Sheehan, S. Moran, and A. Mathewson, “The impact of oxide degradation on the low frequency (1/f) noise behavior of p channel MOSFETs”, Microelectronics Reliability, vol. 36, no. 11/12, pp. 1679-1682, laar, “Hot-Ca1996.
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9. K. N. Quader, E. R. Minami, W.-J. Huang, P. K. Ko, and C. Hu, “Hot-Carrier-Reliability Design Guidelines for CMOS Logic Circuits”, IEEE Journal of Solid-State Circuits, vol. sc-29, no. 3, pp. 253-262, March 1994.10. J. Wang, E. Olthof, and W. Metserrier Degradation Analysis Based on Ring Oscillators”, Microelectronics Reliability, 46, pp. 1858-1863, 2006.11. M. White and J.B. Bernstein, “Microelectronics Reliability: Physics-of -Failure Based Modeling and Lifetime Evaluation”, JPL Publication 08-5 2/08.
Note: Manuals for each CMOS technology node provided by major foundries (e.g. IBM) are devoted to guidelines how to maximize transistor lifetime.
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Backup Slides
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0.0 0.3 0.6 0.9 1.2 1.5 1.80
2
4
6
8
10CMOS018SIMULATED (foundry parameters)
LN RT
I D [m
A]
VDS
[V]
NMOS, L=0.18µm, W=10µm
0.0 0.3 0.6 0.9 1.2 1.5 1.80
2
4
6
8
10CMOS018
NMOS, L=0.18µm, W=10µm
MEASURED
LN RT
I D [m
A]
VDS
[V]
Some differences in saturation voltage, sub-threshold slope, transconductance
ID vs VDS
ID vs VGS
0.0 0.3 0.6 0.9 1.2 1.5 1.810-5
10-4
10-3
10-2
10-1
100
101
CMOS018
SIMULATED(foundry parameters)
LN RT
ID
gm
I D [m
A],
gm [m
S]
VGS
[V]
NMOS, L=0.18µm, W=10µm
0.0 0.3 0.6 0.9 1.2 1.5 1.810-5
10-4
10-3
10-2
10-1
100
101
CMOS018
MEASURED
ID
gm
LN RT
I D [m
A],
gm [m
S]
VGS
[V]
NMOS, L=0.18µm, W=10µm
Static Characteristics: Larger Sub-Threshold Slope at 77 KStatic Characteristics: Larger Sub-Threshold Slope at 77 K
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