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Team M1Enigma Machine

Milestone 6 - 5 March, 2006

Adithya Attawar (M11)Shilpi Chakrabarti (M12)

Zavo Gabriel (M13)Mike Sokolsky (M14)

Design Manager: Prateek Goenka

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Status Finished:

Behavioral Verilog and C simulation Structural Verilog Logic optimization Module-level spice delay and power simulations Floorplan

In Progress: Top-level schematic testing Module layout

Todo: Global Layout Testing Simulation

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Design Decisions Implement additional RSA encryption

module Optimization of floorplan for signal routing Found adder was using un-buffered

transmission gates to drive 6 gates. Doh! Changed signal path to decrease number

of muxes needed

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Propagation delay for old adder: 600 ps

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Propagation delay for fixed adder: 260 ps

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Project Update Quick look at the M4 Project

Found 3 original unbroken 4-wheel enigma messages Example:

CLXP LWRU HCEY ZTCS OPUP PZDI UQRD LWXX FACT TJMB HDVC JJMM ZRPY IKHZ AWGL YXWT MJPQ UEFS ZBCT VRLA LZXW VXTS LFFF AUDQ FBWR RYAP SBOW JMKL DUYU PFUQ DOWV HAHC DWAU ARSW TXCF VOYF PUFH VZFD GGPO OVGR MBPX XZCA NKMO NFHX PCKH JZBU MXJW XKAU OD?Z UCVC XPFT CDXP LWRU VA

Using brute-force and hill climbing algorithms has broken one message using a distributed network of several hundred computers

Means even though it can be broken, it’s not very easy to do!!!!!!! (So you can send credit cards with it, right?)

Also means we have original cipher texts and settings to decode them! (Results coming next presentation)

Adder% 26

C RegN Reg

Out Reg

Mux

Mux

ROM206X

5-bits

ROM26X

5-bits

RAM26X

5-bits

MuxWheel Position Register

Wheel Counters

Wheel Order Reg

Input

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Results of structural simulation 4000 creg:10 nreg: 1 rev:0 output:10 4100 creg:10 nreg: 8 rev:0 output:22 4200 creg:18 nreg: 3 rev:0 output:22 4300 creg:18 nreg: 3 rev:0 output:19 4400 creg:21 nreg: 6 rev:0 output:19 4500 creg:21 nreg: 2 rev:0 output: 8 4600 creg:23 nreg: 6 rev:0 output: 8 4700 creg: 7 nreg: 6 rev:1 output: 7 4800 creg: 7 nreg: 0 rev:1 output:23 4900 creg: 7 nreg: 3 rev:1 output:23 5000 creg: 7 nreg:19 rev:1 output:23 5100 creg: 0 nreg: 1 rev:1 output:23 5200 creg: 0 nreg:21 rev:1 output: 4 5300 creg:21 nreg: 1 rev:1 output: 4 5400 creg:21 nreg: 1 rev:1 output:21 5500 creg:10 nreg: 1 rev:1 output:21 5600 creg:10 nreg: 1 rev:1 output:21

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Results of Structural Simulation

Text Value Cipher Decode

I 8 20 8

A 0 14 0

M 12 8 12

V 21 6 21

E 4 21 4

R 17 9 17

Y 24 15 24

T 19 0 19

I 8 18 8

R 17 14 17

E 4 10 4

D 3 1 3

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Power Module Power (μWatts)

Adder 85

5-bit Register 80.3

Wheel Register 747

Wheelpos Register 450

3-bit Counter 146

Wheel Counters 2500

ROM + RAM ?

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5-bit Register Layout

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And the new module…

Adder% 26

C RegN Reg

Out Reg

Mux

Mux

ROM206X

5-bits

ROM26X

5-bits

RAM26X

5-bits

MuxWheel Position Register

Wheel Counters

Wheel Order Reg

Input

MULTIPLIER(loop E iterations)

P

D

MODULO(Divider)

E

M

OUT

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RSA Module Description RSA encryption

3 inputs: plaintext (5’b), modulus, exponent (12’b) Result = PE % M

Take in a wheel initial position (5 bits), multiply it E times, and modulo M, output result (12 bits)

Repeat for all wheels used in Enigma encoding

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RSA Module Status Behavioral Verilog done, verified Structural Verilog in progress

Goal: Choose multiplier design, done and verified by end of Spring Break

Schematics Goal: Started by end of Spring Break

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RSA Design Decisions Basic FSM to control loading of P (from

Enigma), E, and M (from off-chip), as well as looped multiply operation

Multiplier Sequential is small, easy to implement

SLOW. Also requires nested counters (2 layers of loops)

Array multipliers are faster, more complex Several interesting designs out there

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Low output is 1 Volt!?!?

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Problems/Questions Top level schematic still not verified

This should be taken care of in the next day or two

SRAM voltage problems in schematic simulation