1 V, GHz CM08 Mixers for Wireless -...

1 V, 1.9 GHz CM08 Mixers for Wireless

Applications

A thesis submitted in conformity with the requirements for the degree of Master of Applied Science

Department of Electrical and Computer Engineering Universi@ of Toronto

2001

O Copyright by Song Ye 2001

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1 V, 1.9 GHz CMOS Mixers for Wiless Applications Master of Applied Science, 2000

Song Ye

Department of Electricai and Computer Engineering University of Toronto

Abstract

This thesis deais with the design and implementation of 1 V, 1.9 GHz mixers using

CMOS technology for CDMA applications. The use of CMOS ailows the implementation

of the mixers on the same chip with the rest of the anaiog and digital circuits economically

while achieving high performance. The mixers topologies explored are a dual-gaie mixer

and a back-gûte mixer. The duai-gate mixer is designed in a 0.5 um SOI process and the

back-gate mixer is designed in a 0.25 um standard bulk CMOS process.

Equations describing the nonlinear behavior of the CMOS duai-gate mixer are derived.

The anaiysis yields guidelines for improving third-order intermodulation distortion of the

mixer. The dual-gate mixer exhibits 1.8 dB conversion gain, -0.8 dBm IIP3 and 9.8 dB noise

figure at 1.9 GHz while operating from a 1 V supply with a power consumption of 3 mW

and a die area of 1.44 mm2.

The back-gate mixer utilizes the inherent lateral bipolar transistor in CMOS. Device

simulations were performed to analyze the behavior of the laterai bipolar transistor and

extract a madel for it. The characteristic of the transistor were verified through

measurements. The mixer circuit only draws 1.3 mW from a 1 V supply. The measurement

shows a conversion gain of 6.5 dB. an IIP3 of -3.5 dBm and a noise figure of 9.7 dB at 1.9

GHZ. III= c ~ p area is 1 A mm2.

1 would like to express my sincere gratitude to Professor C. Andre T. Salama for his

insightful guidance and invaluable assistance throughout the course of this work.

1 also would like to thank Professors John Long and Wai Tung Ng for their technical

advice and help.

1 am indebted to Dr. Koji Yano from Yamanashi University for his technical advice and

help in anaiyzing the lateral bipolar in the back-gate mixer.

My appreciation extends to al1 the staff and students in the Microelectronic Research

Lsiboratory. 1 am specially grateful to Dana Reem for her technical assistance during the

chip testing. Thanks go to Anthoula Kampouris, Richard Barber, Milena Khazak, Farhang

Vessal, Rick Kubowicz, Dusan Suvakovic, Mehrada Ramezani, Sotoudeh Harnedi-Hagh,

Zhixian Jiao, Jeewika Ramezani, Polly Tang for al1 their help.

Thanks also to my wonderful friends who made my life in Uoff so pleasant and

unforgettable. Especially, 1 would like to express my appreciation to John Ren, Wei An,

Heng Jin, Yucai Zhang for valuable discussion both technically and personally, and the rest

of my friends: Shuo Chen, Mike Sheng, Hongfei Lu, Franklin Zhao, Edward Chun Keung

Yu, 1-Shan Michael Sun for constructive discussions and cheefil chats.

My deepest appreciation goes to my parents for their constant support and

encouragement. To my mother-in-law for taking care of my son. To my newbom son,

Bmce, for keeping quiet while 1 sleep. Finally, to my wife Lang, thank you for your

patience, support and love.

This work was supported by the Natural Sciences and Engineering Research Councii of

Canada, Micronet, CITO, Gennum, Mitel, Norte1 Networks and PMC Sierra.

Table of Contents

........................................................................ 1.1 Architecture of Wireless Receivers 1

1.2 Murer Development ................................................................................................ 3

1.3 Performance Parameters of a Mixer ..................................................................... 4

............................................................................................ 1.3.1 Conversion Gain 4

.......................................................................................... 1.3.2 Gain Compression 4

............................................... 1.3.3 Third-Order Intermodulation Distortion (iP3) 6

1.3.4 Noise Figure (NF) .......................................................................................... 8

............................................................................................ 1.3.5 Port Retum Loss 9

1 .3.6 Port Isolation .................................................................................................. 9

....................................................................................... 1.3.7 Power Consurnption 9

............................................................................................... 1.3.8 Summary 1 0 .................................................................................................. 1.4 Mixer Topologies 10

.............................................................................................. 1.5 Why CMOS Mixers 12

1.6 Previous Work on CMOS Mixers ....................................................................... 13

......................................................................................... 1 . 7 Objective of the Thesis 14

............................................................................................. 1.8 Outline of the Thesis 16

CEAPTER 2 A CMOS on SOI DuabGate Mixer ......................................................... 20

.................................................................................... 2.1 Technology Consideration 19

.................................................................................................. 2.2 Duai-Gate Mixers 20

........................................................................ 2.3 Topology of the Duai-Gate Mixer 20

.............................................................. 2.4 Anaiysis of the CMOS Duai-Gate Mixer 21

............................................................................................ 2.4.1 Intermodulation 21

.......................................................................................... 2.4.2 Conversion Gain 23

2.5 Duai-Gate Mixer Design ....................................................................................... 23

2.5.1 Design Flow ................................................................................................. 23

2.52 Design Considerations ................................................................................ 23

2.5.3 Complete Design .......................................................................................... 27

................................................................................................ 2.6 Simulation Results 28

2.7 Layout ................................................................................................................... 31

.......................................................................................... 2.8 Experimental Results 32 .................................................................................... 2.8.1 RF Port R e m Loss 33

2.8.2 LO Port Return Loss ................................................................................... -34

2.8.3 IF Port Retuni Loss ...................................................................................... 35

.......................................................................... 2.8.4 Conversion Gain and PldB 36

2.8.5 IIP3 ............................................................................................................... 37

2.8.6 Noise Figure ................................................................................................. 39

2.8.7 LO-IF. LO-RF. RF-IF Isolation ................................................................... 39 ............................................................................................................... 2.9 Sumrnary 41

CHAPTER 3 A Back-Gate Mixer Using CMOS Lateral Bipolar Transistor .-.- ..... A5

........................................................................................................... 3.1 Introduction 45

.................................................................................... 3.2 Technology Consideration 46

....................... 3.3 Structure and Operation of the CMOS Lateral Bipolar Transistor 46

................... .............................*..........**... 3.4 Topology of the Back-Gate Mixer .. -A7

3.5 Device Design ..................................................................................................... ..48

3.5.1 Device Structure ........................................................................................... 48

............................................................................................... 3.5.2 Device Mode1 50

........................................................ 3.5.3 Experirnental Device Characterization 52

3.6 Low Power Mixer Design ................................................................................... 5 5

3.6.1 Schematic the Mixer .................................................................................... 55

3.6.2 Inductor Design .......................................................................................... 3 6

3.6.3 Simulation Results ....................................................................................... 58

..................................................................................................... 3.7 hplementation 58 ............................................................................................ 3.8 Expimentai Results 6û

............................................................................................................... 3.9 Summary 65

APPENDIX A Mixer Intermodui~tioa Aiialysis MM ...~~.W.n.Y.n.-...~..I.n.w.....u...oo .-7o

APPENDIX B Parameters for Lateral BJT Device Simulation ...-..,. -7 6

List of Tables

Page

Table 1.1. Effect of mixer performance on receiver specification .................................... 10

.............................................................................................. Table 1.2. Mixer topologies 11

Table 1.3. Previously reported CMOS mixers characteristics .......................................... 14

Table 1.4. Mixer specificaiions for 1.9 GHz CDMA applications ................................... 15

........................................................................... Table 2.1 : Dual-gate mixer components 30

............................................... Table 2.2. Simulated performance of the dual-gak mixer 31

Table 2.3. Inductor parameters ......................................................................................... 32

.......................................................................... Table 2.4. Mixer performance summary 42

...................................................................... Table 2.5. Comparison with previous work 43

Table 3.1. Ebers-Mol1 mode1 parameters of the lateral BST ............................................. 53

Table 3.2. Component list of the back-gate mixer ............................................................ 57

........................................... Table 3.3. Metal parameters of the 0.25 pm CMOS process 57

Table 3.4. On chip inductor parameters used in the back-gate mixer design ................... 58

...................................... Table 3.5. Substrate parameters of the 0.25 pm CMOS process 58

Table 3.6. Simulated performance of the back-gate mixer ............................................... 59

Table 3.7. Performance summary of the back-gaie mixer ............................................. 66

Table A.1. Faameters used in the mixer intermodulation calculation .............................. 73

. Table B 1 : Parameters for Lateral BST Device Simulation ............................................. 76

Table C . 1: Power Conversion Thle ................................................................................. 77

List of Figures

Page

Fig . 1.1 : (a) Superheterodyne pual-Conversion IF) radio receiver architecture

........................ (b) Homodyne (Direct-Conversion) radio receiver architecture 2

.................................. Fig . 1.2. nlustration of frequency conversion performed by mixer 2

Fig . 1.3. Iilustration of PldB point ................................................................................... 6 Fig . 1.4. Illustration of IIP3 measurement ........................................................................ 7

Fig . 1.5. Iilustration of IIP3 point ..................................................................................... 8

.................................................................................... Fig . 2.1 : SOI MOSFET structure 20

................................................. Fig . 2.2. Topology of the dual-gate mixer 21

Fig . 2.3. MOSFET mode1 ......................................................................................... 22 ......................................................... Fig . 2.4. Nonlinear mode1 of the dual-gate mixer 22

Fig . 2.5. Mixer design flow ............................................................................................ 24

................................................................................................ Fig . 2.6. IF port matciiing 25

Fig . 2.7. Package and bonding wire mode1 ................................................................... 26

Fig . 2.8. LO port matching ............................................................................................. 27

Fig . 2.9. RF port matching .............................................................................................. 28

..................................................................... Fig . 2.10. Schematic of the dual-gate mixer 29

.......................................................................................... Fig . 2.1 1: SOI inductor mode1 31

Fig . 2.12. The mixer layout ........................................................................................ 32 Fig . 2.13. (a) Micrograph of the mixer (b) 24-pin ceramic package ................................ 33 Fig . 2.14; RF port remm test setup ................................................................................... 33

..................................................................... Fig . 2.15. Expnmental RF port retum loss 34

Fig . 2.16. LO port retum loss measunment setup ........................................................ 34 Fig . 2.17. Experimntd LO port cetum loss ..................................................................... 35

Fig . 2.18. IF port r e m loss test setup ............................................................................ 35

................................................................................... Fig . 2.19. Gain masurement setup 36

. Fig . 2.20: Experimentai conversion gain vs RF fiequency .......................................... 3 6

Fig . 2.2 1: Experimental dependence of IF power on RF power ...................................... 37

Fig . 2.22. Input refened third order intercept point (IIP3) test setup ............................... 38

Fig . 2.23. Experhneotal output spectrum for the two tone test ........................... .......... 3 8

. ...................................................................... Fig . 2.24. Experimental iIP3 vs LO power 39

...................................................................................... Fig . 2.25. Noise figure test setup 40

................................................................................ Fig . 2.26. LO-RF isolation test setup 40

Fig . 2.27. Experimental LO-RF / LO-IF isolation vs . LO power ..................................... 41

Fig . 2.28. Experimental RF-IF isolation vs . RF power .................................................... 41

Fig . 3.1. Structure of the lateral and vertical bipolars in a CMOS n-well process ........ 46

Fig . 3.2: (a) Topology of the back-gate mixer and

........................ .................................... (b) its small signal equivalent circuit ,.., 47

Fig . 3.3. Layout of the p-MOSFET ............................................................................... 49

Fig . 3.4. A ce11 structure of the p-MOSFET. M.5 p.m. Wcell=6.25 p.m ..................... 49

........................................................ Fig . 3.5. Doping concentration of the p-MOSFET 50

Fig . 3.6. Composite mode1 of the p-MOSFET with LPNP ........................................... 50

Fig . 3.7: Simulated IsD vs . VSB of tkr composite device . (VGS is v"ed from -1 . lV to

.0.6V in 0.1V steps) ......................................................................................... 51

Fig . 3.8. Simulated Ic vs . VEC for the LPNP at VGs=.0.6V ......................................... 52

................................................................. . Fig . 3.9. Experimental IsD vs VSB and VGs 54

Fig . 3.10. Experimental Ic vs.Vu: and VBE when VGs=.0.6 V ...................................... 54

Fig . 3.11. Experimental P of the LPNP vs . IB and VGs .................................................. 55

.................................................................................... Fig . 3.12. Schematic of the mixer 56

Fig . 3.13. illustration of the CMOS metal layers .......................................................... 56

......................................................................................... Fig . 3.14: Layout of the mixer 59

Fig . 3.15. n-well underneath signal pads ..................... .., ................................................. 60

Fig . 3.16. Microphotograph of the mixer ..................... .., ......................................... 60

Fig . 3.17. Experimental conversion gain vs . RF frequency ............................................ 61

Fig . 3.18. Experimental gain vs . IF frequency ............................................................. 61

Fig . 3.19. Experimental IF power vs . RF power ............................................................ 62

Fig . 3.20. Experimental output spectnim of the two tone test ......................................... 62

. ............................................... Fig . 3.21. Expetimentai gain and IIP3 vs LO power 63

Fig . 3.22. Experimentai RF-IF isolation vs . RF frequency ........................................ 63

Fig . 3.23. Expecîmcntal RF-IF isolation vs . RF p w e t ................................................... 64

. ................................................... Fig . 3.24: Experimentai LO-IF isolation vs LO power 64

Fig . A.1. Equivdent circuit of the dud-gate mixer ....................................................... 70

Fig . A.2. PIM3' as a function of transistor's widths W l and W2 ................................. 74

Fig . A.3. PIM3' as a tùnction of bias voltages ............................................................. 74

Chariter 1: Introduction 11

CHAPTER 1

Introduction

1. Architecture of Wireless Receivers

The two receiver architectures that are considered viable for portable telephony

applications are shown of Fig. 1.1 (a) and (b). In the superheterodyne receiver, the antenna

picks up the radio signal and feeds it to the bandpass filter. The filter rejects undesired out-

of-band signals and feed the desired signal to the LNA. The image-reject filter removes the

signais in the image band. The mixers are used to conven the radio frequency (RF) signal

down to an intermediate frequency (IF) by mixing the RF signal with the local oscillator

(LO) signals as shown in Fig. 1.2. This allows channel selection and gain control at lower

frequencies where high quality factor (Q) filters and variable-gain amplifiers can be

implemented economically. The frequency of the local oscillator is fixed above or below the

RF frequency. The foliowing bandpass filter then filters the out-of-band harmonies. The IF

signal then goes to a second mixer stage which generates the baseband data which is then

demodulated. In the case of the homodyne receiver shown in Fig. 1.1 (b), the IF signal is

sent to an andog to digital converter (ADC), and the data samples are then demodulated

using a digital signal processor.

IV, 19 GHz CMOS Mixers for Wireless Applications University of Toronto

Chapter 1: Introduction 12

1st mixer 1st IF mplifier 2nd mixer 2nd IF amplifier

mixer IF amplifier

Image-reject tüter

Data Out

Bandps Bltcr

Fig. 1.1: (a) Superheterodyne (Dual-Conversion 4 radio receiver architecture (b) Homodyne (üirect-Conversion) radio receiver architecture

1st local oscillator 2nd local oscillator

(a)

Fig. 1.2: illustration of Frequency conversion performed by mixer

IV, 19 GHz CMOS Mixers for Wmless Applicatioos University of Toronto

1.2 Mixer Development

Mixer technology, in use today, was known several hundred years ago when the

trigonometric functions were used to generate mathematical functions. Before the invention

of vacuum tubes, mechanical contact mixers in the form of a rotating disk with multiple

conductocs on the edge were used to sample and downconvert radiotelegraphy signals to the

audio range. The invention of the electronic mixer is generally attributed to Armstrong [ l ,

21. In 1917, Armstrong invented the superheterodynel principle in which he used a vacuum-

tube mixer to shift the received signal to an "intemediate frequency (IF)," where it could be

mplified with good selectivity, high gain, low noise, and finally demodulated. At that time,

mixers were often called "detectors" [3]. Today. the superheterodyne receiver is still the

most popular receiver used in communication systems. It is found in receivers ranging in

sophistication from cheap transistor radios to communication satellites.

Very little theoretical work was done on mixers prior to 1940. During Worid War II,

mixers were snidied intensively when the need for high-quality microwave radar receivers

became urgent.

By 1960, vacuum tubes were replaced by transistors excep for mixer implementation.

In 1968, Gilbert pubiished a paper on a four quadrant analog multiplier which is used as

Gilbert mixer today. The first distortion analysis of a bipolar Gilbert mixer was presented in

1998 [30]. The ficst distortion anaIysis of a track-and-hold sampling mixer was reported in

1999 [3 il.

1, Superheteradyne corne h m hetemdyne in which the RF carrier incoming signal is translatecl in ftequenq, and accupies an eqnal bandwidth centered about a new ftecruency This new center fieciuency, known as the intermediate hcpency O, is ked and is nok dependent on the RF signal center fkequency. If this IF is 1mr than the carrier 6!equency but above the final output aignai frequency, the receiver ia d e d a superbetedyne receiver.

1.3 Performance Parameters of a Mixer

When two electronic signais are mixed under the right conditions, one ends up with a

third, different signal (either the sum, the difference, or some combination of the two

original signais). The performance parameters of downconversion mixers are described in

this section.

1.3.1 Conversion Gain

At radio frequencies, the efficiency of transmission of signal power is of great

importance. For this reason, RF circuits are optimized for power gain instead of voltage or

current gain as commoniy done in most low frequency circuits. The unit of power used to

specify absolute power level is the dBm (or decibels referenced to 1 mW). Power levels in

dBm cm be computed from the equation

The conversion gain (G) of a mixer is defined as the ratio of IF output power Po,, to the

available input RF power Pi,

The tenn conversion is used to refer to the frequency converting action of the mixer. A

downconversion mixer which provides power gain can compensate for the IF filter loss and

reduce the noise contribution from the IF stages. However, this gain must not be t w large,

since a strong signal may sahuate the output of the mixer.

1.3.2 Gain Compression

As a measure of amplitude tinearity, the 1 dB compression point (P1dB) is the point at

which the actual gain is 1 dB below the ideal linear gain.

1V, 1.9 GHz CMOS Mixers for Wueless Applications University of Toronto

Chapm 1: Introduction 15

The conversion gain of a mixer remains unchanged for srnail RF input signals where

the IF output power is proportional to the RF input power. However, when the RF input

signal becomes large, the gain starts to drop and the IF output signal is distorted because of

nonlinearities in the mixer. The higher the PldB compression point, the larger RF signal

that the mixer is able to handle for a specified level of distortion generated. By sweeping the

RF input signai power, the PldB compression point of a mixer can be detewned as shown

in Fig. 1.3.

Both limiting (saturation) of the transistor characteristic, and odd-order nonlinearities

can cause gain compression. In the case where gain compression is caused by limiting, the

gain drops abmptly and the output power stays constant as the input power exceeds the

input PldB. In the case where the gain compression is caused by the odd-order nonlinearities

in the transfer function of the devices used, the gain decrease more gradually as the input

power exceeds the input PlciB. At medium input power levels, gain compression is

dominated by third-order nonlinearity. As the input power increases, highersrder

nonlinearities become significant.

P !dB is an important characteristic of the mixer since it indicates the upper lirnit of the

input power level prior to saturating the mixer and generating nonlinear effects. If the input

power of the desired signal is larger than the input PldB, the desired signal will be distorted

at the output of the mixer. This distortion causes amplitude to phase modulation conversion.

No information is lost if the desired signal is frequency modulated. On the other hand, if the

signal is phase modulated, the unwanted phase shift caused by amplitude to phase

modulation conversion may result in detection errors, which increase bit error rate (BER).

IV, 19 GHz CMOS Mixers for Wmless Applications University of Tomnt0


Pout (mm)

8

8 Ideal Output

I

I Noise Floor I

I

I W Pin ( m m ) PldB

Fig. 1.3: iilustration of PldB point

1.3.3 Third-Order Intermodulation Distortion (IP3)

Due to its nonlinear behavior, a mixer generate the IF signal as well as intermodulation

products at different frequencies. Arnong these intermodulation products, the third order

intermodulation (IM3) can fa11 within the IF signal band and cm cause signal distortion.

The figure of merit (IP3) used to characterize the linearity of a mixer is defined as the point

at which the thid order intermodulation product equais the ideal linear, uncompressed

output.

To measure IP3, equal amplitude RF signals at frequencies fm and fm are applied to

the mixer input while a local oscülator at frequency fW is provided as illusirated in Fig. L .4.

IF signais will be generated at fRFl - fLO and fm - fLo The IM3 wiii be generated at 2fRF1

- fRF2 - fLO and 2fw - fm - fLo By sweeping the RF input signal power, IM3 power PM

and IF output power Pa, can be plotted as a function of Pin as shown in Fig. 1 S. The point

1V. 19 GHz CMOS Mixers for Wirefess Applications - ~ ---

University of Toronto

Chapter 1: introduction 17

where the extrapolations of the mail signal lM3 and IF intercept one another is the third

order intercept point (IP3), and its correspondhg input power is iIP3 (input ceferred

intercept) while the output signal power becomes the OP3 (output referred intercept point).

The relation between iIP3 and OP3 are shown below (in dBm), where G is the conversion

gain

Fig. 1.4: Iilustration of lIP3 measurement

micaiiy, IIP3 is specified in receiver systems whereas OP3 is specified in tcansmitter

systems. The numerical value of the IIP3 is not directly related to that of the PldB because

IP3 measures the small-signal nonlinear condition which is dominated by the third-order

nonlinearity, whereas PldB is a measure of the large-signal nonlinearities which include

contributions fiom al1 odd-order harmonics. Furthemore, IP3 depends on the magnitude of

the third-order nonlinearity only, whiie PldB depends on both the magnitude and phase of

the third-order nonlinearity. If the both iP3 and PldB wece dominated by third-order

nonlinearity, the numerical value of the IIP3 would be 9.64 dEl higher than that of P l a .

- --

lV, 19 GHz CMOS Mixers for ~irel&Applications University of Toronto

Chapter 1 : Introduction 18

Pout (dBrn) A

v I I I Noise Floor

Pin

Fig. 1.5: illustration of IIP3 point

1.3.4 Noise Figure (NF)

Noise factor, in decibel units (dB), is an important figure of merit used to characterize

the performance of the mixer and determines the system sensitivity. Noise factor is defined

as the input signal to noise ratio divided by the output signal to noise ratio.

and noise figure is defined as

NF = lOlog(F) (1-6)

where Si, and Ni, represent the RF signai and noise power levels available at the input of the

mixer, and So and No are IF signal and noise power levels available at the output.

Noise in the RF and image bands mixes with the LO signal and translates to the IF

band. Mixer noise figures can be measured and specified in two ways: double side band

IV, 19 GHz CMOS Mixers for Wmless Applications University of Toronto


@SB) or single side band (SSB). SSB noise figure is 3 dB higher than DSB. if the DSB

measurement method is employed, 3 dB must be added to the measured noise figure to

arrive at the SSB noise figure numkr.

1.3.5 Port Return Loss

The impedance of the RF, LO input and ïF output ports are typicaily matched to 50 Cl

Impedance matching at the RF and IF ports is necessary to avoid signai reflection and

excessive baseband ripple in the filters. Typically, return losses of less than -10 dB or

voltage wave standing ratio (VWSR) of less than 2 are required. The return loss

specification on the LO port can be more relaxed. However, excessive return loss requires

the LO terminal to deliver high power to the mixer thus increasing power consumption in

the overail system.

1.3.6 Port Isolation

Isolation is a measure of how much power is coupled from one port to the next. The

two most useful isolation measurements are LO-to-IF isolation and LO-to-RF isolation. The

f o m r indicates how much LO power le& thmugh the output IF port, and the latter

indicates how much LO power leiiks through the input RF port, LO power appeacing at the

output IF port can be attenuated easily by a lowpass filter since the two frequencies are far

apan, but it is more difficult to suppress at the RF port. LO leakage through the RF port

usually results in a ce-radiation through the antenna if the mixer is used as the first

downconverter in a wireless receiver.

1 . 7 Power Consumption

While optimizing the power consumption of the mixer, care has to be taken to avoid

increasing the power consumption of other building blocks.

IV, 19 GHz CMOS Mixers for Weless Appticatiws University of Toronto


For instance, a mixer which requires high LO power drive increases the power

consurnption of the LO. It may take up to 120 mW of power dissipation in a VCO to supply

O dBm of output power into the 50 i2 LO port of the mixer, while it only consumes 24 mW

to supply -5 dBm output power into the same mixer [4].

1.3.8 Summary

A summary of how mixer parameters affect receiver performance is given in Table 1.1.

Table 1.1 : Effect of mixer performance on receiver specitication

Mixer Pnrameter 1 Affected Receiver Specitication

1 Conversion gain 1 Receiver sensitivity 1

1

Noise figure 1 Receiver sensitivity

Third-order intercept point (P3) Intermodulation distortion, adjacent chonnel selectivity

1.4 Mixer Topologies

LO to RF isolation

RF to IF isolation

Mixers are the primary frequency translation devices in a communication system. In

LO energy propagates toward antenna

Susceptibility to direct F frequency pickup

contrast to fiequency multipliers and frequency dividers, which also change signai

frequency, mixers faithfully preserve the amplitude and phase properties of signals at the

RF input port. Signals can therefore be translated in frequency without affecting their

modulation properties.

Aithough, in theory, any nonlinear device can be used as a mixer, only a few devices

satisfy the practical requirements of mixer operation. Any device used as mixer must have a

strong nonlinearity, low noise, low distortion, and adequate frequency response. There are

several options available to the RF designer. The most common technotogy choices for

current systems are silicon bipolar (Si BJT), GaAs MESFET, and CMOS. All of these

alternatives offer price and performance trade-offs that must be carefuiiy examined.


Chapter 1: Introduction 2 1

Table 1.2: Mixer topologies

SigaJ input ami WQUI mibod 1 CbaraemiJtiu

LowccuMJionlou-adB Pmrimlmion Nndt high LO prnm-IMB N d 3 f i l m i4mrspuiourrupcuim Poorlinauity

Gmllineatity Poœnobfigwc Lowmnmionloaa N d high Lû powa

singie t ~ i ~ d e ZJT ' "

Gallr MESFEï. S i BiCMOS, Si CMOS

GaAa MESB. Si B i i O S Si CMOS

I Neeb 3 f i l m - Nndt high L O p o w ---- - Low convusionloaa - Fniriloloiim - NeebMun

Nndt 3 dB h i g k LO p o w h m single diode

Dificultu, intcgmte in a mhnology beeiurc firtdiodi wiih law m-rcrimace DR m ùMIobk

Dificult to integriue in 8 VL! mhnOto6y

- Vay low mnvmion lasa

ihm singiediodc - Lowmmiongnin - Low noise figure - Lowduta<ion - Poarudmion - Nndtdiplaa and f i l in - Modaaie LO powcr

- Gaod isolation wiihout f i l m - Modenue m d o o gnin - ModcimenoUefigwc - Lowdisidon - LowLOpawer

~ ~

OGaAs MESFEï. Si BiCMOS Si CMOS

Si CMOS

. Hi*plrarmnace ICappk- c a u w r ~ t k n u n b e r o f aParinonPadmcsmcof baluar K ~crrprPMe

-Si BIT. Si BiCMOS. G a h MES=. Si CMOS

IV, 1.9 GHz CMOS Mixers for Wiless Appiications University of Toronto


Selection of a topology is made considering a multitude of sometimes conflicting

system cequirements and inevitable performance trade-offs between six, power

consumption, third-order intercept (IP3), noise figure, available voltage, on-chip versus off-

chip components and final product cost.

In tenns of conversion gain, mixers can be categorized into passive and active mixers.

In addition, there are single-ended, single-baianced and double-balanced configurations. A

cornparison is given in Table 1.2.

Although passive mixers, such as balanced diode mixers, are very linear and can

operate at very high frequency (> lOGHz), they have no conversion gain. On the other hand,

active mixers provide conversion gain to reduce the noise contribution from the IF stages.

A numkr of high frequency filters are required to isolate each port of a single diode or

resistive mixer. Monolithic high frequency filtering is a technology still in the early

development stages, and the out-of-band rejection, lineacity and power consumption

required for the radio receiver application is beyond the current state-of-art in filter

tec hnology.

in addition, a large number of extemal components are required to implement a single

passive mixer of sufficient quaiity for wireless applications. This increases the cost and

limits the reliability and manufacturability of the circuit. Although passive mixers work

without power supply, some still need bias voltages.

The typical RF integrated circuits operating at L-band (1 to 2 GHz) use dicon bipolar

or GaAs technology because of their excelient high frequency performance. These circuits

however tend to occupy a large area and use high power and prevent the implementation of

CMOS digital baseband circuitry on the same chip. The increasing demand for portable

IV, 19 GHz CMOS Mixers for Wmless Applicaîions University of Toronto


wireless communications has motivated efforts to design RFICs to meet the requirements

for lower cost, lower power, higher integration density and higher performance. To meet

these increasingly demanding specifications presents a challenge to RF circuit designers

using silicon technology. Silicon MOSFETs have traditionaily found application at the

lower frequencies (IF below) but as technology is scaled down, CMOS performance is

becoming commensurate with that of GaAs MESFETs and silicon bipolar transistors.

Among the RFIC building blocks, the mixer is a critical component, and one which

poorly understood due to the non-linear nature of the mixing process. This thesis will

investigate the design, optimization, implementntion of CMOS mixers.

1.6 Previous Work on CMOS Mixers

In the last few years, CMOS mixers have attracted considerable attention [l l-291. The

performance of the best previously reported CMOS mixers operating at 1.9 GHz are

sumrnarized in Table 1.3.

In general, these mixers have a low gain, a high power dissipation, a poor noise figure,

a low integration or need high LO power. Most of the architectures are based on the Gilbert

configuration which needs an external balun and is not well suited for integration. In

addition, the relatively high input impedance of the differential pair of transistors at RF

rnakes it difficult to match to the image-rejet filter resulting in additional off-chip matching

components for best performance. One finai disadvantage is that the stack structure in the

Gilbert configuration needs at least a 2.5-3 V power supply.

LV, 19 GHz CMOS Mixers for Wreiess Applications University of Toronto

Table 1.3: Previwsly reporteci CMOS mixers cbsiracteristics

Design

Hsiao ' et al, '98

~il icasia~ et al, '98

~ui i iyan~ et al, '98

svelto2 et al, '99

IN1

et al. '97

su~~ivan' et al, '99

0 . 5 p CMOS

0 . 5 ~ CMOS

0 . 6 p CMOS

0Spm CMOS

O. 2ïpm CMOS

0.8prn CMOS

0.2pm C M W SIMOX

4-qu;idrant multiplier ' doubly balnnced Gilbert

back-gaie

Powcr Matching dissipation and b a d

~ P P ~ Y Vottagc)

on-chip

(3W

neeàs balun

emitter fol-

IF on-chip,

chip nccds balun

off-chip

lower & ext batun

19mW nceds fol-

doubly balanced dual-gate

1.7 Objective of the Thesis

The objective of îhis thesis is tu investigate the analysis, design and optimization of

IV, 19 GHz C M û S Mixers for Wmless Applications University of Toronto

Chapier 1: Introduction 25

monolithic RF downconversion mixers using standard CMOS technology with emphasis on

Iow-voltage low-power operation. The mixer configurations investigated are the dual-gate

mixer and the back-gate mixer. The dual-gate mixer yields gwd port-to-port isolation

without using filters and features ceasonable gain, noise figure and low power consumption.

The back-gate mixer uses a MOSFET as a four tenninal device, and thus results in a design

yielding very low power consumption, good conversion and teasonable linearity. The mixers

are intended as building block in a 1.9 GHz PCS CDMA CMOS single chip receiver, The

expected specifications are listed in Table 1.4.

Table 1.4: Mixer speclftcations for 1.9 GHz CDMA applications

1V. 19 GHz CMOS Mixers for Wiiless Appiicatio~ls University of Tmnto

Chaptec 1: Introduction 26

1.8 Outline of the Thesis

in Chapter 2, a silicon on insulator (SOI) CMOS dual-gate mixer is designed,

fabricated and tested [32]. The third oder intermodulation performance is optimized

foiiowed the guidelines denved in Appendix A.

Chapter 3 presents a back-gate mixer utilizing the inherent lateral bipolar transistors in

CMOS. The lateral bipolar transistor was characterized and an Ebers-MOU mode1 was

generated through ISE device simulations and verified through measurements. The design

of the mixer is presented dong with expimental results.

Conclusions and guidelines for future work are presented in Chapter 4.

IV, 1.9 GHz C ' O S Mixers for Wùeles Applications UnivemfSIty of Tomnto

[l] S. A. Maas, Microwave Mirers, 2nd ed., Artech House, Boston, 1993.

[2] http://www.analog-rf.corn/rnixer.shtml

[3] R. C. Dixon, Radio Receiver Design, Marcel Dekker, New York, 1998.

[4] VCO Data sheet, Mercury United Electronic Inc., 2000

[5] B. L. Smith and M. Carpentier; Microwave Engineering Handbook vol. 2, Chapman & Hall, London; New York, 1993.

[6] J. R. Long, ECE1364 Lecture Notes, University of Toronto.

[7] B. Razavi, RF Microelectronics, Prentice Hall, Upper Sddle River, N.J., 1998.

[8] 1. Kneppo, Microwave Integrated Circuit, Chaprnan & Hall, London, 1994.

[9] S. A. Maas, The RF and Microwave Circuit Design Cookbook, Artech House, Boston, MA, 1998.

[LOI K. L. Fong and R. G. Meyer, "Monolithic RF Active Mixer Design," IEEE Transac- tions and Systems - II: Analog and Digital Signal Processing, Vol. 46, 1999.

[Il] J. Crols and M. Steyaert, "A Fully Integrated 900 MHz CMOS Double Quadrature Downconverter", Int'l Solid State Circuits Confi, pp. 136 137, 1995.

[12] A. Rofougaran, J. Y. C. Chang, M. Rofougaran, and A. A. Abidi, "A I GHz CMOS RF Front-End IC for a Direct-Conversion Wireless Receiver," IEEE J. of Solid-State Cir- cuits, vol. 3 1, pp. 880-889, 1996.

[13] A. N. Karanicolas, "A 2.7V 900-MHz CMOS LNA and Mixer:' IEEE J. of Solid-State Circuits, vol. 3 1, pp. 1939- 1944,1996.

[14] D. H. Shen, C. M. Hwang, B, Lusignan, and B. A. Wooley, "A 900 MHz RF Front-End with Integrated Discrete-Time Filtering," ZEEE J. of Solid-State Circuits, vol. 3 1, pp. 1945-1954, 1996.

[15] A. Rofougaran, G. Chang, J. J. Rad, James Y. C. Chang, M. Rofougaran, P. J. Chang, M. Djafati, 1. Min, E. W. Roth, A. A. Abidi, and H. Samueli, "A Single-Chip 900-MHz Spread-Spectnim Wireless Transceiver in 1-pm CMOS - Part II: Receiver Design," lEEE Journal of Solid-State Circuits, Vol. 33, pp. 535447, 1998.

[16] Q. Huang, P. Orsatti and F. Piazza, %SM Transceiver Front-End Circuits in 0.25-pm CMOS," IEEE Journal of Solid-State Circuits, Vol. 34, pp. 292-303, 1999.

[17] J. Crols and M. Steyaert, "A 1.5GHz Highly Linear CMOS Downconversion Mixer," IEEE J. of Solid State Circuits, vol. 30, pp. 736-742, 1995.

[18] H. Kilicaslan, S. K. Hong, M. Ismail, "A 1.9 GHz CMOS RF dom-conversion mixer," Proceedmgs of Midwesî Symposium on Circuits and Systems, pp. 1 172- 1 174,1998.

1191 S. Y. Hsiao, C. Y. Wu, "A parailel structure for CMOS four-quadrant analog multipliers and its application to a 2-GHz RF downconversion mixer," IEEE-Journal-oflofid- State-Circuits. vo1.33, pp. 859-869, 1998.

IV, 19 GHz CMOS Mixers for WiIess Applications University of Toronto


[20] P. J. Sullivan, B. A. Xavier and W. H. Ku, "A common source input cross coupled quad CMOS mixer," Proceedings of Midwest Symposium on Circuits and Systems, pp. 152- 155,1998.

[21]E. Cijvat, P. Eriksson, N. Tan and H. Tenhunen, "A 1.8 GHz subsampling CMOS downconversion circuit for integrated radio applications,", IEEE International Confer- ence on Electmnics, Circuits and Systems, Vol. 3, pp. 149 -152. 1998.

&2] P. Litmanen, P. Ikdainen and K. Halonen, "A 2.0 GHz Submicron CMOS LNA and a Downconversion Mixer,'' Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, Vol, 4, pp. 357 -359, 1998.

[23] A.R, Shahani, D.K. Shaeffer and T.H. Lee, "A 12-mW Wide Dynamic Range CMOS front-end for a Portable GPS Receiver," lEEE Journal ofSolid-State Circuits, pp. 206 1 -2070, Vol. 32, 1997.

[24]F. Svelto, M. Conta, V. D. Tom, R. Castello, "A low-voltage topology for CMOS RF mixers: IEEE Transactions on Consumer Electronics, Vol. 45, pp. 299-309, 1999.

[25] P. J. Sullivan, B. A. Xavier and W. H. Ku, "Low voltage performance of a microwave CMOS Gilbert cell mixer," IEEE Journal of Solid-Stare Circirits, pp. 1 15 1-1 155, Vol. 32, 1997.

[26] H. Wang, "A 1-V Multigigahertz RF Mixer Core in 0.5-pm CMOS," IEEE Journal of Solid-State Circuits, Vol. 33, pp. 2265-2268, 1998.

[27] S. Y. Hsiao and C. Y Wu, "A Parallel Structure for CMOS Four-Quadrant Analog Mul- tiplier~ and Its Application to a 2-GHz RF Downconversion Mixer," IEEE Journal of Solid-State Circiu'ts, Vol. 33, pp. 859-869,1998.

1281 P. J, Sullivan, B. A. Xavier and W.H. Ku, "Double balanced dual gare CMOS mixer," IEEE Jotimal of Solid-State Circuits, Vol. 34, pp.878-88 1, L999.

[29]M. Harada, T. Tsukahara and J. Yamada, "0.5-IV 2GHz Front-end Circuits in CMOSSIMOX," IEEE International Solid-State Circuits Conference, pp. 378-379, 2000.

[30]K. L. Fong and R. G. Meyer, "High-Frequency Nonlinearity Anaiysis of Common- Emitter and Differentiai-Pair Transconductance Stages." IEEE Jountal of Solid-State Circuits, Vol. 33, pp.548-555,1998.

[3 11 W. Yu, S. Sen and B. H. Leung, "Distortion Anaiysis of MOS Track-and-Hold Sam- pling Mixers Using Time-Varying Volterra Series," IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Pmesshg, Vol. 46, pp. 101-1 13, 1999.

[32] S. Ye and C. A. T. Salama, "A IV, I .9GHz, Low Distortion Dual-Gate CMOS on SOI Mixer," lEEE Intematioml SOI Conference, pp. 102- lO3,2OOO.

Chapter 2: A CMOS on SOI Dual-Gate Mixer 29

CHAPTER 2

A CMOS on SOI Dual-Gate Mixer

The design and implementation details of a dual-gate mixer are described in this

chapter. The mixer is implemented in a 0.5 prn silicon on insulator (SOI) CMOS technology

for operation in the 1.9 GHz band at 1 V power supply. Intermodulation characteristics of

the mixers are analyzed using a Volterra series representation. Guidelines for optimum

sizing and operating points of the transistors are obtained. Layout and testing are also

discussed,

2.1 Technology Consideration

A 0.5 pm silicon on insulator (SOI) CMOS technology was chosen for the design. The

structure of SOI transistors is shown in Fig. 2.1. The SOI wafer consists a film of silicon

1200 A thick on top of an insulating subsüate. Because of the insulating substrate, SOI

offers low substrate parasitics and minimum coupling which result in high performance

active as well as passive elements. The MOSFETs in the process have a maximum

oscillation frequency, Fm, of 50 GHz as compared to 20 GHz Fm, for 0.5 ym bulk

devices. The technology is suitable for the integration of analog as well as digital CMOS

circuits, and is an ideal technology for RF front-ends.

U~versity of Toronto


Fig. 2.1: SOI MOSFET structure

2.2 Dual-Gate Mixers

Silicon MOSFET dual-gate mixers have been widely used in mobile and hand-held

radio transceivers since the 1960s [ I l . They exhibit good noise figures and reasonable

conversion gains and most importantly, they allow the application of the two input signals to

two separate gates thus making separate LO and RF matching possible ihus avoiding

passive couplers and simplifying the design. The inherent isolation between the gates of the

two FETs aiso results in very good LO-to-RF isolation without the use of filters. A double

balanced CMOS duai-gate mixer has ken reported [4]. However, low voltage singleended

dual-gaie CMOS mixers have not been reported thus far. The absence of a theoreticai

distortion analysis makes it difficult to predict and optirnize the intermodulaiion

performance of such a mixer.

2.3 Topology of the Duel-Gate Mixer

The typical topology for a dual-gate CMOS mixer is shown in Fig. 2.2. Two MûSFETs

(FETl and FET2) are connected in a cascode configuration. The LO signal Vto is injected

into the gate of FET2 while the RF signal VRF is injected into FETI. The IF output signal

Vw is accessed from the drain of FET2. Zgl and Zg2 represent for the input matching

networks associated with FET1 and FET2 respectively. Z, is the source impedance

associated with the source of FETI. "IF Matching" is the output matching network, and ZL

IV, 13 GHz CMOS Mixers for WmIess Applications University of Toronto

Chapter 2: A CMOS on SOI Dual-Gate Muer 3 1

is the load usually 50 Q RFC is the RF choke used to prevent the RF signal from flowing

through the power supply Vdd to ground. VG1 and VG2 are bias voltages applied to the

gates of FET 1 and FET;! respectively. The SOI devices have zero threshold voltages and the

supply voltage chosen is 1 V.

Vdd p

Fig. 2.2: Topology of the duai-gate mixer

The mixer is biased so that the upper transistor (FET2) is in the saturation region and

the lower transistor (FETl) is in the triode region near the edge of saturation. The drain to

source resistance (Rdsl) of FETl is varied by the large LO signal applied at the gate of

FET2.

2.4 Analysis of the CMOS Dual-Gate Mixer

2.4.1 Intermodulation

Since the mixer is a three port nonlinear network, it is difficult to optimize the

intermoduIation petformance without theoreticai guidelines. Based on the MOSFET mode1

shown in Fig. 2.3 and the dual-gate equivaient circuit shown in Fig. 2.4, the third order

intermodulation was analyzed (see Appendix A).

LV, 19 GHz CMOS Mixers for Wkeless AppLications üniversity of Toronto


In Fig. 2.3. Cg, is gate-to-source capacitance, vg is the signal voltages across CF, is

drain-to-source resistance, and g, is the transconductance. Based on this model, the dual-

gate equivalent circuit is show in Fig. 2.4. Cgsl is gate-to-source capacitance of FET1, vgl

and vg;! are the signal voltages across Cgs 1 and Cgsa respectively, R h 1 and hS2 are drain-to-

source resistance of FETl and FET2, and gml and gm2 are transconductance of FETl and

FET2 respectively, and id, is the drain to source current of FET1 and FET2. To simplify the

circuit, the IF matching network is replaced with a capacitor C. Using this model,

guidelines for lowering PIM3 were developed (see Appendix A). The guidelines point out

the need for:

minimizing the width of FETl while maintaining reasonable gain,

increasing the LO power,

reducing the source impedance Z, associated with FET 1, and

biasing FET2 for maximum transconductance while keep FET2 in the saturation

region.

Fig. 2.3: MOSFET model

Fig. 2.4: Nonlinear model of the duai-gate mixer

IV, 19 GHz CMOS Mixers for ~ i ~ l e s s Applicaiions University of Toronto

Chapter 2: A CMOS on SOI DualGate Mixer 33

2.4.2 Conversion Gain

An approximate expression for the conversion gain of dual-gate mixers is [ I I

where Rgl and Rd are gate and source related resistances of FET 1, QF and o , ~ are the RF

and IF frequency respectively. Equation 1-7 provides guidelines on how to adjust the

conversion gain. Gain cari be increased by increasing the transconductance of FETl,

lowering the gate to source capacitance of FETl and FET2, and decreasing the gate and

source resistance of FET 1. It dso indicates that gain decreases with increasing ORF and c.01~

2.5 DuahGate Mixer Design

2.5.1 Design Flow

The design steps used in designing the mixer are illustrated in Fig. 2.5. The circuit

simulations were carried out using the HP ADS design software while Iayout was done

using Cadence. Due to the relatively poor accumy of the models provided by the foundry

at RF frequencies, the simulation was only used to initialize the design. It is usualiy not

possible to optimize al1 the performance simultaneously. Setting priorities is necessary.

Usudly conversion gain, IP3 and noise figure are the most important parameters to

consider.

2.6.2 Design Considerations

In the circuit of Fig. 2.2, FET 1 is biased in the lineu region dose to the pinch-off poist,

FET2 is biased so that the device switches on and off evety half LO cycle to create large LO

voltage at the drain of FETl resuiting in efficient W g .

LV, IJ GHz CMOS Mixers for WmIess AppIications üniversity o f Toronto


I t i

DC & S-Rmmncr Siuintioa wl HSPICE w l HP ADS

1

BLing üaip

S-Pnnuncur Sirnulpiion

RFAOflF Mntching Nctwork Design Tuning and Adjuminit

1 Gnio. ln. NF. lsohtion Sirnulpiion 1

Y u

1 Gain, IP3, NF. isolation Sirnulniton 1

Fig. 2.5: Mixer design flow

LV, 19 GHz CMOS Mixers for Wmless Applications University of Toronto


The IF matching network is redizd off chip due to the frequency at which the

matching must be carried out. Fig. 2.6 shows the IF port matching fiow and the termination

of RF and LO ports. Bondwires make a connection from package pins to desired pads on

the chip. Parasitic elements acise due to the package which are essential to take into account

especially in high-frequency design. The pin of the package has a series inductance. The

bonding wire has a series inductance of a value of approximately lnH/mm, The ohmic loss

due to the pin is modeled with a series resistor.

Fig. 2.7 illustrates the mode1 of package and bonding wire. Cpl a d Cp2 are parasitic

capacitance in the package. Cprd is the pad capacitance. Rp and Lp serial resistance and

inductance of the package respectively. Lbond is the bonding wire inductance. The series

capacitor C4 is used to block the dc current. The capacitor C3 together with bonding wire

and package parasitic inductance fonn a notch filter to filter out the high frequency

harmonies. Both the LO and RF ports are terminated with their respective conjugate

impedance when matching the IF port.

v a , IV LF matching ____t i otr-chlp FET2

i Fig. 2.6: IF port rnatching

IV, 1.9 GHz CMOS Mixers for Wireless Applications University of Toronto


Package P

Fig. 2.7: Package and bonding wire mode1

FET 2 acts as an IF amplifier, its input impedance is very high and thus very difficult to

match to 50 Q Fig. 2.8 shows the LQ port matching circuit. In this case, the on-chip

matching network is located between the package lead and the gate of FET2. In order to

include the package parasitics and bonding wire of the LO port, the matching starts from the

input of the LO port, and moves progressively toward the gate of FET2. A conjugate match

is necessary to achieve maximum power transfer to the gate of FET2. The matching also

includes a dc blocking capacitor to prevent any dc current flow from the LO input port. A

shunt inductor L2 together with bonding wire and package parasitics (used as components

of the matching network) serves as a bias path as well.

The RF input impedance Z, of FETl is dominated by the gate impedance, source

impedance and gaie-to-source capacitance. An estimate for is Zi, given by

where 2, and Zgl are source and gate associated impedances of FETl including bonding

wire and package parasitics effect-

Fig. 2.9 shows the RF port matching circuit. The matching technique is similar to that

used for the LO port case. An inductor L3 is inserted into the source of FETl to improve the

IV, i 9 G& CMOS Mixers for wue~ess ~ p p ~ i c a t i ~ ~ s

Cha~ter 2: A CMOS on SOI Dual-Gate Mixer 37 . - - - -- --

matcbing. This will improve the RF input retum los~ with sacrificing on ihe IP3

performance.

032V

matching direction -

Fig. 2.8: LO port rnatching

2.6.3 Complete Design

Transistors' size cm initidly be determined following the guideline proposed in

Section 2.4.1, then adjusted to meet the gain specification. The dc bias for FET2 can be

adjusted to optimize the conversion gain at a given LO level. Decreasing the source

impedance associated with FETl can improve IP3, however, it will result in poorer input

matching for both the LO and RF ports, and thus decrease the gain and increases the noise

figure. RF port input matching affects LO port input rnatching, and vice versa Capacitor C3

suppresses the high frequency harmonics, and also contributes to IF output matching. It

affects both IP3 and the conversion gain. Noise figure is found to be sensitive to the bias

voltages. Iterative tuning usuaiiy can not be avoided in order to meet aU specilications

IV, 19 GHz CMOS Mixers for Wiless Applications University of Tomnto

Chapier 2: A CMOS on SOI Dual-Gate Mixer 38

simultaneously. The final schematic for the mixer is illustrated in Fig. 2-10, and the circuit

parameters are listed in Table 2.1.

RF matching

Fig. 2.9: RF port matching

2.6 Simulation Results

A summary of simulation results is given in Table 2.2. The resutts meet the

specifications outlined in Section 1.7.

IV, 19 G H ~ CMOS Mixers for Wiiless Applications University of Totoato


intrinsic devices

Fig. 2.10: Schematic of the dual-gate mixer

IV, 1.9 Güz CMOS Mixers for Wmless Applications University of T m t o

Chaptet 2: A CMOS on SOI Dual-Gate Muer 40

Table 2.1: Dual-gate mixer components

FETl 1 WIL=216pn10.5pm

Parameter

IV. 19 GHz CMOS Mixers for Wteless Applications Univem-ty of Toronto

Value

Chapter 2: A CMOS on SOI Dual-Gate Muer 4 1

Table 2.2: Simulated performance of the dual-gate mixer

I LO port return Lm

2.7 Layout

IF port mtum 104s

LO-RF uolatim

LO-IF i6olation

RF-@ Wlatian

Supply vol*

Ibmr diamipatina

The mixer was implemented in a triple metal double poly 0.5 pm CMOS on SOI

-2s dB

41 dB

4 4 dB

4 0 dB

1 V

3.7 mW

process. Capacitors were double poly. Inductors used ail three metals layers in shunt to

minirnize series resistance. A five width space was given around each inductor to reduce

coupling [7]. The SOI process provides the spiral inductor parameters based on the

modeling shown in Fig. 2.1 1. The parameters of used inductors are listed in Table 2.3. The

mixer layout is shown in Fig. 2.12

Fig. 2.1 1: SOI inductor mode1

lV, 19 GHz CMOS Mixers for Whless Applications University of Tomto

Chapter 2: A CMOS on SOI Dual-Gate Mixer 42 .- - -

Table 23: Inductor parameters

Fig. 2.12: The mixer layout

The mixer was packaged in ri 24 pin ceramic fiat package (CFP) and soldered onto the

PCB-TF2 PCB provided by CMC. The PCB accepts a 24-pin CFP, routing 12 signal lines to

SMA connectors, 8 Lines directly to ground, and 4 selectable lines io p w e r sources or

ground. The micrograph of the mixer and ihe 24 pin ceramic dat package (CFP-24) used are

shown in Fig. 2.13 (a) and (ô) respectively. The mixer was tested as a downconverter for a

standard heterodyne receiver with an input RF frequency of 1.93 GHz, a LO frequency of

1.72 GHz and an IF frequency of 210 MHz. In the testing, aii measurements were per-

f o d in a 50 Q system.

The gates of the MOSFETs bave low breakdown voltages and are easily damaged by

L 1

L2

L3

- -- -

IV, 19 Güz CMOS Mixers for Wueless Applications

LineGap

4

2

2

L(nW

3.7776

4.0096

0.3324

[mer ,,jarneter

(pm)

145

135

50

R (il) Line

F-2

1.7237

4.6042

0.9184

GHz of-

( P d

4.0868

21.1614

13

35

1.5

15<QaO

1024<15

22

18

10 11.2536 1 5<Q<IO


electrostatic discharge (ESD). A safe procedure is to bcing up the bias voltages gradually

instead of just throwing the switch.

I b

(a) (b) Fig. 2.13: (a) Micrograph of the mixer (b) 24-pin ceramic package

2.8.1 RF Port Return Loss

The test setup is shown in Fig. 2.14. A signai generator capable of generating a

sinusoidal signal was used to apply the -5 dBm LO signal to the mixer at 1.72 GHz. A 50 9

termination was used to represent the 50 $2 IF load. The return loss versus frequency is

displayed on the network analyzer. The measured RF port return loss is - 15.8 dB, as shown

in Fig. 2.15, and is better than the -14 dB specified in Section 1.7.

Fig. 2.14: RF port cetuni test setup

IV, 19 GHz CMOS Mixers for Witeless Applications University of Toronto


Fig. 2.15: Experimental RF port retum loss

2.8.2 LO Port Return Loss

The setup used to measure the LO port retum loss is shown in Fig. 2.16, A LO signal is

applied to its port and the unused RF and IF ports are terminated in 50 Q . The LO generator

supplies an input signal level of -5 dBm. With the mixer disconnected from the directional

coupler, a reference level is obtained. Next, the mixer is connected to the output of the

directional coupler and the LO power refiected back from the mixer is measured. The return

loss is -18 dB, as shown in Fig. 2.17, and is weU above the specified - 14 dB.

1 V Vdd and bies

Fig. 2.16: LO port return loss measurement setup

IV, 1.9 GHz CMOS Mixers for Wreless Applications University of Toronto

Chapter 2: A CMOS on SOC Dual-Gate Mixer 45

g-3 i f ' €-la -l-'+q&;

Fig. 2.17: Experimental LO port return los

2.8.3 IF Port Return Loss

The testing of IF port return loss is similar to that of the RF port, as illustrated in Fig.

2.18. The network analyzer is switched to the IF porc and the RF port is terrninated in 50 CL

A return loss of -17 dB was measured at 210 MHz frequency. The result indicates a good

match meeting the specification.

signal

V Vdd and bias 7

Fig. 2.18: IF port return loss test setup

--

network analyzer

lV, 19 GHz CMOS Mixers for Wireless Apptications University of Toronto


2.8.4 Conversion Gain and PldB

The test setup for measuring the conversion gain is shown in Fig. 2.19. A signai at 1.93

GHz was applied to the RF port. The signai power at the RF port and IF port were measured

using the spectrum anaiyzer. The conversion gain was found by subtracting the IF signai

power from the RF signal pcwer. The measured gain versus RF frequency is shown in Fig.

2.20. PldB was obtained from the output power of D; versus RF power as illustrated in Fig.

2.21. Both conversion gain and PldB meet the specifications.

1 V Vdd and bias

signal generator

spectrum analyzer

Fig. 2.19 Gain meaurement setup

Ph = -20 dBm

-'8.s 1 1.5 2 2.5 3 RF Frequency (Hz) x 109

Fig. 2.20: Experimentai conversion gain vs. RF frequency

1V. 19 GHz CMOS Mixers for Wreless Appücations University of Tomnto


. . . . . . . . . . . . . , . . . . - . , , . . , -

-50 -40 -30 -20 -1 0 O 10 RF power (dBm)

Fig. 2.2 1: Experimental dependence of iF power on RF power

The merisurement of HP3 requins a two tone RF signal and one LO signal. The test

setup is shown in Fig. 2.22. ' h o signai generators used in above sections were used as LO

and one RF signais, and the network anaiyzer was used as the other RF signal. Two -20

dBm RF signals at 1927 MHz and 1929.5 MHz are applied. The resultant output specûum

for îhe two tone test is shown in Fig. 2.23. iïP3 is obtained fiom Fig. 2.23 using equation

IIP3 = Pi, + 0.5P0,, -0.SIM3 = -0.8dBm

The measured JIP3 versus LO power is shown in Fig. 2.24. The resuIt meets the CDMA

specitication.

- - --

IV, 1 9 GHz CMOS Mixers for Wmless Applications University of Toronto

Chapter 2: A CMOS ou SOI Dual-Gaie Mixer 48

1 V Vdd and bias

signal generator R&S SMTiX3 1 power combiner

signal generator

Fig. 2.22: Input referred third order intercept point (IIP3) test setup

-98A0 I

205 21 O 21 5 Frequency (MHz)

Fig. 2.23: Experirnental output specmim for the two tone test

IV, 1.9 GHz CMOS Mixers for Wreless Applications - - - - -

University ofT0~01lt0

Cha~ter 2: A CMOS on SOI Dual-Gate Murer 49

4 -1 O -5 O 5 10

LO Power (dBm)

Fig. 2.24: Experimentai lIP3 vs. LO power

2.8.6 Noise Figure

The setup of noise figure measurement is shown in Fig. 2.25. The measured single-side

band (SSB) noise figure is 9.8 dB.

2.8.7 LO-IF, LOIRIF, RF-IF Isolation

The test setup of LO-RF is shown in Fig. 2.26. it also applies to the LO-IF measurement

by switching the spectrum analyzer and die 50 iL load. The measmd results are shown in

Fig. 2.27. The results at the operating LO levd &O=-5 dBm) meet the specifications.

The test setup for measuring the conversion gain can be used for RF-IF isolation

measurement. The result of measurement is iiiustrated in Fig. 2.28. The RF-IF isolation at - 20 dBm of RF power is -26 dB.

IV, 19 GHz CMOS Miers for Wreless AppLimtions University of Toronto

Chapter 2: A CMOS on SOI Dual-Gaie Mixer 50

n o b figure meter hp 89708

noise source NC 3468

signal ganerator H&S SMT03

Fig. 2.25: Noise figure test setup

Fig. 2.26: LO-RF isolation test senip

- --

IV, 1.9 GHz CMOS Mixers for Wmless Applications University of Toronto

Chapcer 2: A CMOS on SOI Dual-Gate Mixer SL

Fig. 2.28: Experimental RF-IF isolation vs. RF power

-32

-34

5L LL -36 Ï 9-38- - IL

7 40

9 -42,

-44

A 1 V mixer using 0.5 pm CMOS on SOI technology was implemented and tested. The

mixer meets the specifications of a CDMA transceiver operating at 1.9 GHz [9]. The

characteristics of the mixer are summarized in Table 2.4. The discrepancy between

-30.,,,,,, . , - - - t

l t

8

t 8

- 1 1 LO-IF / t t 8 - t 8

-

t t

8

*- - - - l

t # * t * t- - - - **# RF = -20 dBm

lV, 19 GH2 CMOS Muers for Wireless Applications University of Toronto

-2% -1 5 -1 0 -5 O 5 LO power (dBrn)

Fig. 2.27: Experimental LO-RF 1 LO-IF isolation vs. LO power


simulated and experimental results are attributed to the lack of accuraçy of device mode1

provi&d by the foundry at RF frequency.

A cornparison with the best reported previous work is given in Table 2.5. Compared to

the previous design, the present mixer has higher gain, lower noise figure, good IIP3, lower

power consumption, lower LO power required and on-chip input matching and in addition it

is the first dual-gate mixer operating at 1 V power supply,

Table 2.4: Mixer performance summary

Parneter

Tafhnology

Die m a

Supply voltage

Power dhipation

RF fmiueW

1 IF port mhuir l m 1 -25 dB 1 -17, 1 - --

Convenion gain

PldB

IIP3

SSB miae ligure

RF port mtum l m

LO port mhua l m

Siulation h u i t

0.5 )im CMOS on SOI

1.44 mun2

1 V

3.7 mW

1.93 G ü z

IV, 19 GHz CMOS Mixers for Wiiless Applications University of Toronto

Expaiimencel Rsiult

0.5 pm CMOS on SOI

1.44 mm2

1 V

3 mW

1.93 G k

3.6 dB

4.7 dBm

0.17 dBm

NIA

-21 dB

-18 dB

L0-W iiolation

LOF holation

RF-[F inointion

1.8 dB

-9 mm

-0.8 dBm

9.8 dB

-16.8 dB

-18 dB

41 dB

4 d B

4 0 dB

-22 dB

-38 dB

-26 dB

Chapter 2: A CMOS on SOI DuabGate Mixer 53

Table 2.5: Cornparison with previ~us work

Double balanceci dual-gate ** Dual-Gate


Design

Sullivan* et al [4], '99

thi-s deSign**PlP '00

C

Gain (dB)

O

1.8

Rocess

0.8um CMOS

0;- = on S M

PldB ( d W

- 10

3

Power mW

(SUPP~Y)

30 (3V)

UV)

Fceq. (GHz)

1.9

1.9

OPJ

O

- -0.8

SSB NF

(dB)

13.6

9.8

MatChing

off-chip

m-chip hp~t

-f3

Chapter 2: A CMOS on SOI Dual-Gaie Mixer 54

References

[1] S. A. Maas, The R F and Microwave Circuit Design Cookbook, Artech House, Boston, MA, c1998.

[2] A. M. Pavio and R. H. Halladay, "A Distributed Double-Balanced Dual-Gate FET Mixer," IEEE GaAs IC Symposium, pp. 177-180, 1988.

[3] J. Fikart and P. Acimovic, "Single-Ended Mixer with Reduced LO Penetration," IEEE Pac@c Rim Conference on Communications, Computers and Signal Processing, pp. 63-66, 199 1.

[43 P. J. Sullivan, B.A. Xavier and W.H. Ku, "Double bdanced dual gate CMOS mixer," IEEE Journal of Solid-State Circuits, Vol. 34, pp. 878-88 1, 1999.

[5j D. A. Johns and K. Martin, Andog Integrated Circuit Design, John Wiley & Sons Inc., c 1997.

[6] W. Yu, S. Sen and B. H. Leung, "Distortion Analysis of MOS Track-and-Hold Sam- pling Mixers Using Time-Varying Volterra Series," IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Pmcessing, Vol. 46, pp. 101-1 13, 1999.

[7] J. R, Long and M. A. Copeland, "The modeling, characterization, and design of monolithic inductors for silicon RF IC's," lEEE Journal of Solid-State Circuits, Vol. 32, pp. 357-369, 1997.

[8] T. Manku, G. Beck and E. J. Shin, "A Low-Voltage Design Technique for RF Integrated Circuits," IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Processing, Vol. 45, pp. 1408-1413, 1998.

[9] S. Ye and C. A. T. Salama, "A IV, l.SGHz, Low Distortion Dud-Gate CMOS on SOI Mixer," IEEE International SOI Conference, pp. 102-103,2000.

IV, 19 GHz CMOS Mixers for Wmless Applications University of Toronto

Chapter 3: A Back-Gate Mixer Using CMOS Laterai Bipolar Transistor 55

CHAPTER 3

A Back*Gate Mixer Using CMOS Lateral Bipolar Tkansistor

3.1 Introduction

Presently, the dominant technology for commercial RF front ends is advanced bipolar

junction transistor (BJT) [Il. However, the demand for low cost implementation has

resulted in integration of RF building blocks into a digital CMOS monolithic system.

Unfortunately, the performance of the CMOS RF building blocks is limited by the low

transconductance and low cutoff frequency of the MOSFET.

BiCMOS offers a combination of both bipolar and CMOS devices, however BiCMOS

requires additional mask layers and increased process complexity, w hich translate in lower

yield and higher costs as compareci to standard CMOS technologies.

Circuit designers have come to realize that bipolar transistors coexisting on the same

substrate as CMOS could enhance circuit performance because of their high transconduc-

tance. Since no modification of the IC process needs to be made this approach is cheap,

widely applicable and relatively simple to realize. An amplifier using this approach has

been reported [2]. A mixer using a BiCMOS gate-controlled lateral PNP transistor has also

been mported [3], however, it was ümited to reiatively low frequency (400 MHz). This

Chapter describes a 1.9 GEiz mixer implementation using a lateral BJT inherent in a buk

CMOS technology.

IV, 19 GHz CMOS Mixers for Wuelss Applications University of Toronto

Chapter 3: A Back-Gate Mixer Using CMOS Lateral Bipolaf Transistor 56

3.2 Technology Consideration

A 0.25 pm CMOS technology was selected for the design. The technology has five metal

and single poly layer allowing a minimum drawn feature size of 0.25 p. The technology is

suitable for the design of low power analog and full custom digital circuits. It offers p-

MOSFETs with a threshold voltage of -0.6 V and n-MOSFETs with a threshold voltage of

0.45 V.

3.3 Structure and Operation of the CMOS Lateral Bipolar

Transistor

As illustrated in Fig. 3.1, there are two kinds of pnp parasitic bipolar transistors in

CMOS, Iateral and vertical. The source and drain of the p channel MOSFET serve as the

ernitter and the collector of the lated bipolar transistor. The channel region of the p-MOS-

FET serves as the base of the lateral bipolar device. The vertical bipolar transistor is fomed

by the p+ source acting as the emittex, the n-wel acting as the base and the p-substrate act-

ing as the collector. A conventional CMOS technology does not offer a buried layer. The

vertical transistor is not important due to its very low current gain. The objective is to make

use of the lateral parasitic bipolar (LPNP) provided by the MOSFET in the mixer design

discussed in this chapter.

Fig. 3.1: Structure of the laterai and vertical bipolars in a CMOS n-weU process

IV, 19 GHz CMOS Mixers for Wireless Applicatiolls University of Toronto

Chapier 3: A Back-Gaie Mixer Using CMOS Latecd Bipolar Transistor 57

3.4 Topology of the Back-Gate Mixer

The topology for a back-gate mixer is shown in Fig. 3.2 (a). A pMOSFET M 1 with an

inherent LPNP P 1 is usd as a four terminai device. The RF input signai Vw is applied to

the gate of the MOSFET and the LO signal VLO is fed to the substrate or base of the LPNP.

The 11: output signai V,,, is accessed from the drain. VG VB1 and Vdd are the bias and

supply voltages respectively. The n-MOSFET M2 acts as a load and the conversion gain of

the mixer can be adjusted by changing its gate voltage VG2. LS is used to shift the ac voltage

level at the source of M 1 and its function will be explained below.

Vdd

P

Fig. 3.2: (a) Topology of the back-gate mixer and (b) its smail signai equivaient circuit

The srnall signal equivalent circuit of the mixer is shown in Fig. 3.2 (b). Vp, is the signai

voltage across Zg which is the impedance associated with the gate of Ml, g, is the

transconductance of Ml, Zs is the impedance of Ls, is the current gain of Pl and & is the

impedance associated with the base of the LPNP. To simplify the circuit, the n-MOSFET is

replaced by a resistor RL. VS is the voltage at the source of the Ml. In saturation region, îhe

transconductance of Ml can be exptesssd as

IV, 19 GHz CMOS Mixers for Wueiess Applid0lls --


Chapter 3: A Back-Gaie Mixer Using CMOS Lateral Bipolar Transistor 58

w here

where y is the body effect factor, VTo is zero substrate bias tfireshold voltage, + is the sur-

face potential, is the electmn mobility, Cox is the oxi& capcitance of M 1, L is the chan-

ne1 length, and W is the width, bx is the oxide thickness, %,, is the permittivity of Si&.

Equation 3- 1 indicates that g, is a function of Vs and Vth. However, Vs is modulated by

the collector current Pib and the base current ib of the LPNP generated by VLO as show in

Fig. 3.2 (b). Furthemore Vh is a function of VBS or VLO-VS. Therefore, the drain current

of Ml id (i+. g,,,V,) has a rniiring terni VRFVLO varying ai a frsquency fwfLo, which is

the desired IF signal. A first or&r estimate of the conversion gain is given by the expres-

sion:

M l should be biased in the saturation region where the gate voltage can controll the

source to drain current. Pl must be biased in the active region so that a small variation of the

base voltage can result in a iarge variation in the collector current Pib and thus vary Vs

effectively by changing tbe current flowing thcough Ls. Since M2 is used as a resistive load,

it must be biased in the triode region. LO and RF inputs c m not be exchanged because high

base resistance of the LPNP resulîs in high losses at RF frequencies.


Chapter 3: A Buck-Gate Muer Llsing CMOS Lateral Bipoiar Tmisror 59

3.5 Device Design

3.5.1 Device Structure

To analyze and characterize the LPNP bipolar transistor, 2-D ISE' simulation was

performed based on the device layout shown in Fig. 3.3. in order to increase the drive

current capability, the pMOSFET was split into sub-cells surrounded by body contacts.

Each sub-ce11 had a 0.5 pm channel length with five channels in parallel as illustrated in Fig.

3.4. The channel width of each ce11 is and the total aspect ratio W/L is 438um/O.Sum.

The parameters used in ihe simulation are given in Appendix B. The doping concentration

in the structure is show in Fig. 3.5.

b b , 75 Pm -q

Fig. 3.3: Layout of the p-MOSFET

-

1. Integrated Spstems Engineering, Zurich, Switzerland

Fig. 3.5: Doping co~lccntration OS the pMûSFET

3.63 DeviceMode1

The modd parameters for the cornpsite gMOSFET and LPNP dcvice illustraid in

Fig. 3.6 were obtaiaed using the ISE simulatoc The MOSFET m&l is the conventional

BSIM3 mode1 provideci by the faundry. The bipolar mcxiel was based on a simple &CS-

MOU modcl with pammm listed in Table 3.1. Sincc the pMOSFET is in the n-well, thm

is an aâditional jwtion capacitance Cs b a n the a-weU and psubstrate.

Fig. 3.7 shows the simulateci source to drain cumnt ID versus source to bulL voltage

VSB as a function of the gate to source voltage. It indicates that the LPNP conûibutes the

dominant composent of IsD when VsB kiargcr than 0.7 V w b the LPNP is in active

IV, 1.9 GHz CMOS Mixers fa Wuel#l A p p ü a h Uni-ty of Tapot0

Chapter 3: A Back-Gate Mixer Using CMOS Laieral Bipolar Transistor 6 1

region. In the region where VSB is smaller than 0.7 V, TsD is mainly controiied by VGS. The

circled region identified in the diagram is ideal for mixer operation because both VSB (or

VBE) and VGS have significant effect on IsD The model parameters of the LPNP were

extracted in this region, for [email protected] V and VGs=-0.6 V. The main consideration in choos-

ing VGS is power dissipation. Fig. 3.8 shows the forward output characteristic of the LPNP

when VGs=-0.6 V. The value of the extracted parameters are listed in Table 3.1.

Fig. 3.6: Composite model of the p-MOSFET with LPNP

0.1)

WIL = 438 pm / 0.5 Pm 0.w

Bipolar dominated Region

0.m

O os 1

VSB 0 Fig. 3.7: Simulated IsD vs. VSB of the composite device. (VGS is varied h m -1.lV to -

0.6V in 0. IV steps).

IV. 19 GHz CMOS Mixers for Wireless Applications University of Toronto

Chapter 3: A Back-Gate Mixer Using CMOS Lateral Bipolar Transistor 62

Fig. 3.8: Simulated vs. VEC for the LPNP at VGs=-0.6V

3.5.3 Experimental Device Characterieation

Fig. 3.9 illustrates the experimental source ta drain current of the p-MOSFET versus VSB

and VGS. VSB is varied from O V to 1.5 V for various values of VGS ranging from -1.1 V to

-0.6 V. These results show the same trend as the simulated characteristic shown in Fig. 3.7.

The ciifference between the experimental and the simulation results may be attributed to

parasitic resistances not accounted for the model.

The collector current Ic of the LPNP versus VEC and VBE is shown in Fig. 3.10 and

agrees with the simulated result in Fig. 3.8. The current gain B of the LPNP versus base cur-

rent Ig and gate to source voltage VGS is shown in Fig. 3.1 1. B increases capidly at low base

currents making the transistor is suitable for low current design.

IV, 1.9 GHz CMOS Mixers for W'iless Applications University of Totonio


Table 3.1: Ebers-Mol1 moàd parameten of the lateral BJT

VA 1 VAF

Symbol

1s

1 CJE 1 CJE 1 5.3E-14 F 1 1 4% 1 VJE 1 0.8 V 1

Spice Keyworà

IS

1 c ~ c 1 CJC 1 3E-13 F 1

Value

2.23-16 A

@c 1 VJC 1 0.8 V

1 C ~ s 1 CJS 1 2.983-14 F 1 @S 1 VJS 1 0.8 V

1 ZR 1 TR 1 î.îe-11 sec 1

LV, 19 GHz CMOS Muers for Wiiless Applications University OC Totonto

Chapter 3: A Back-Gate Mixer Using CMOS Lateral Biplar Transisior 64

W/L = 438 pm / 0.5 pm

1.5 v~~

Fig. 3.9: Experimental IsD vs. V, and VGS

v,, = -0.5 v

v,, = -0.4 v O - = 5

O0 O .S 1 1.5 2 2.5 3

v, 0 Fig. 3.10: Experimental Tc vs.VEc and VBB when VGs=-0.6 V

IV, 19 GHz CMOS Mixers for WreIess Appücations University of Toronto

Chapter 3: A Back-Gate Mixer Using CMOS Lateral BipoIar Transistor 65

Fig. 3.1 1: Experimental P of the LPNP vs. IB and VGs

3.6 Low Power Mixer Design

3.6.1 Schematic the Mixer

A back-gate mixer using the LPNP discussed pmiously is presented in this section. The

mixer is intended for use in CDMA applications and must meet the specification listed in

Chapter 1.

The schematic of the mixer is shown in Fig. 3.12. Boib RF and LO input matching are on

chip, while the output matching is off chip. Cl, L1 and L2 form the RF matching netwodc.

C2, L3 and L4 form the matching network for the LO signal. C3, C4 and L5 form the JF

matching network, A width of the pM0SFET was picked to be 438 pm to achieve the

requested gain and iIP3. The width of 201 Pm was cbosen €gr the n-MOSFET to achieve

maximum adjustable range for the conversion gain. The component values in the design are

listed in Table 3.2+

IV, 1.9 GHz CMOS Mixers for Wireless Applications University of Toronto

Chapter 3: A Back-Gate Mixer Using CMOS Lateral Bipolat Transistor 66

VG I Vdd ? ?

Fig .3.12: Schematic of the mixer

3.6.2 Inductor Design

The 0.25 pm CMOS process provides five metal layers as shown in Fig. 3.13. The

metal and substrate parameters are listed in Table 3.3 and Table 3.4 respectively. Metals 5

and 4 have Iower losses to the substrate and were used in shunt for the spiral inductors.

Spiral inductors on silicon have ben studied in past few years [Ml. A CAD tool,

ASmC (Analysis and Simulation of inductors and Transfomiers for IC), developed by A.

M. Niknejad at University of Califonia at Berkeley, was empIoyed for inductor LI to L5 and

simulation and design. The simulation results are shown in Table 3.2.

Fig. 3.13: IIlustration of the CMOS metal layers

LV, 19 GHz CMOS Mixers f i Wire1ess Appiicarims


Table 3.2: Component lbt of the back-gate mixer

Table 3.3: Metal parameters of the 0.25 jm CMOS process

L5

L6

V G ~

VBI

v ~ 2

-- - -

Distance to Conductor Layer

100 nH*

9 nH*

0.39 V

0.4 V

0.72 v

IV, 1.9 GHz CMOS Muers for Wiiless Appiicatiuas University of Totonto

* off chip


Table 3.5: On chip inductor parameters used in the back-gate mixer design

Table 3 4 Substrate parameters of the 0 s pm CMOS pmcess

3.6.3 Simulation R e d t s

Thickness (um)

Resistivity (Qcm)

Relative Permeabdi@, E,

With the extracted parameters of the LPNP, simulation was performed using HP-ADS.

A summriry of simulation results are given in Table 3.6. The results meet the specifications

outlined in Section 1.7.

625

10

11.7

3.7 Implementation

The layout of the mixer is illustrated in Fig. 3.14. To reduce the signal loss througb the

substrate, a n-well was put undemath each input and output signal pari as shown in Fig.

3.15. Capacitors u x d were metal-to-metal capacitors. The area of the chip is 0.7~2 m d incIuding bonding pads. Less than 0.5% of the chip area is used for the active devices.

IV, 19 GEz CMOS Muers for Wmless Applications University of Tomato

Chaptet 3: A Back-Gate Mixer Using CMOS Lateral Bipolar Transistor 69

Table 3.6: Simulated performance of the back-gate mixer

-

1.99 GHz

LO-RF ùdition

IF fmuiey I 210 MHs

CF Vdd

Convenion gmh

PtdB

rn

RF pott mturn [ o r

LO port nhim Iom

I ~ W P - I Fig. 3.14: Layout of the mixer

7.6 dB

-11 düm

4 .3 dBm

-16 dFl

-18 dB

IV, 1.9 GHz CMOS Mixers for Wirekss Applications University of Toronto

Chapter 3: A Back-ûate Mixer Using CMOS Laterai Bipolar T mistor 70

PCB Package Chip t t t

Bondwire f .

\

PIN L PADI, 1, n-well ,

psubstrate

Fig. 3.15: n-well undemeath signal pads

A micrograph of the mixer is illustrated in Fig. 3.16. The fabricated chip was packaged in

a 24 pin ceramic flat package (CFP). A PCB was designed for the testing and was fabricated

through AP Circuit Inc. GMLlOOO laminate was chosen for low loss purpose. The testing

procedure is sllnilar to the described in chapter 2. Ali measurements were performed in a 50

Q system with al1 the needed external surface-mounted-device components.

Fig. 3.16: Microphotograph of the mixer

The measured conversion gain versus RF fiequency is shown in Fig. 3.17. The input

LO power, PLo and RF power Ph are -6 dBm and -20 dBm respectively. The IF f iuency

fw is h e d at 2 10MHz. A gain of 6.5 dB was obtained at 1.93 GHz. Fig. 3.18 illushates the

conversion gain of the mixer versus IF frequency. Fig. 3.19 illustrates the gain versus RF

input power. The LO ûequency is h e d at 1720 MHz. PldB is detennined to be -17.5 dBm.

Both conversion gain and PldB meet the specilications. Fig. 3.20 illustrates the measured

IV, 1.9 GH2 CMOS Mixers for Wuclcss Applications University of Toronto

Chaptcr 3: A Back-Gate Mixer Using CMOS Lateral Bipolar Transistor 7 1

output spectnm of two tom test when a No-tone RF input at fRFI=1930MHz and

fm=1938MHz was applied. And IIP3 is measured to be -3.5 dBm and higher than the

specification.

-20 t fw=210 MHz

Fig. 3.17: Experhental conversion gain vs. RF tiepuency

- -so 1 0 0 l i a 2 2ia & 4 w 4b 500 IF Frequency (GHz)

Fig. 3.18: Experimentd gain vs. IF freciuency

IV, 1.9 GHz CMOS Mixers for Wiless Applicatiaas University of Toronto

Chapter 3: A Back-Gaie Mixer Usina CMOS Lateral Bipolar Transistor 72

PL@ dBm fLO = 1720 MHz f, -210 M H z

-4& -50 -45 -40 -35 -30 -25 -20 RF Power (dBm)

Fig. 3.19: Experimental gain vs. RF power

Fig. 3.20: Experimental output spectnun of the two tone test

iV, 1.9 GHz CMOS Mixers for Wirclcss Applications University of Tomnto

Chapter 3: A Back-Gate Mùa Using CMOS Caieral Bipolar Transistor 73

10

*mLL----- --- . -1 5 -10 -5 O 5

LO Power (dBm)

Fig. 3.2 1: Experimental gain and flP3 vs. LO power

Fig. 3.21 illustrates the gain and IIP3 vernis LO pwer. High gain can be obtained

when LO power is in the range of -IO d h to -4 dBm. Optimum iIP3 can be achieved at a

LO power around -4 &m. RF-IF isolation versus RF fkquency and RF power are sbuwn in

Fig. 3.22 and Fig. 3.23 respectively. The RF-IF isolation at -20 dBm of RF power is -26.5

dB. LO-iF isolation is -36.5 dB at 4 dBm of LO power as show in Fig. 3.24. Boîh RF-IF

and LO-IF isolation meet the specifications. LO-RF isolation is -10 dB and meets the

specification. The reason is ihat the LO signal goes to the RF port Wugh the substrate

coupling. Meamrd noise figure was 9.7 dB and meets the specification.

1.1 2 2.2 2 4 28 2 8 RF Frsqusncy (GHz)

Fig. 322: Experimental RF-iF isolation vs. RF fieswncy

IV, 1.9 GHz CMOS Mixers for Wmless Applications University of Toronto

Chapier 3: A BackGate Murer Using CMOS LateraI Bipolar Transistor 74

Fig. 3.23: Experimentai RF-IF isolation vs. RF power

Fig. 3.24: Experimental LO-iF isolation vs. LO power

IV, 1.9 GHz CMOS Mixers for WUC~CSB Applicatiolls University of Toronto

Chaptcr 3: A Back-Gate Mixer Using CMOS Lateral Bipolar Transistor 75

A RF mixer using the lateral bipoiar transistor inherent in CMOS has been desigaed and

fabricated in a standard 0.25 p n CMOS process. At 1.93 GHz, the mixer has a 6.5 dB gain,

a 9.7 dB noise figure and -3.5 dBm üP3. The circuit draws 1.3 mW h m a 1 V supply. The

mixer meets the specifications of a CDMA transceiver operating at 1.9 GHz. Table 3.7 sum-

marized the mixer performance. The differences between simulateci and experimental

results are attriiuted to the lack of accuracy of the extracted LPNP model and the model of

MOSFETs provided by the foundry.

The work has demonstrated that a MOSFET and the inherent lateral bipolar transistor

cm be used to design a mixer with gwd high frequency performance cbaracteristics. Such a

mixer is a likely candidate for low power portable CDMA wireless applications. The design

compares very favorably with previous work meationed in Chapter 1, while using a simple

architecture, requiring few compomnts, eliminating interstage coupling, offering variable

gain conml by adjusting the gate bias of the n-MOSFET and reducing the supply voltage

while still maintaining reasonable performance.

IV, 1.9 GHz CMOS Miers for Wirelcss Applications University of Totonto

Chapter 3: A Back-Gate Mixer Usinn CMOS L a t d Bipolar Trmistor 76

Table 3.7: PerfQrmance summary of the back-gate miser -- - -

Parameter

Technology

Die area

Supply voltage

Power dissipation

RF frequency

ïF frequency

Convernion gain

Simulation Result

0.25 pm CMOS

SSB noiae figute

( RF-IF isolation 1 3 0 dB 1 -26.5 dB 1

Experimmtal Result

0.25 pm CM09

1.4 mm?

1V

1.2 mW

1.93 GHz

210 MHz

7.6 dB

- -- - -- . - - - . . . - . . .

IF port mtum loea

LO-RF isolation

LO-IF ieolation

IV, 1.9 GHz CMOS Mixers for Wiilcss Applications University o f Toronto

1.4 m d

1V

1.3 mW

1.93 GHz

210 MHz

6.5 dB

d a 9.7 dB

-20 dB

-11 dB

-34 dB

-18 dB

-10 dB

-36.5 dB

Chapur 3: A Back-Gate Mixer Using CMOS Lateral Bipolar T-stor 77

References

[l] Q. Huang, P. Orsatti and F. Piazza, "GSM Transceiver Front-End Circuits in 0.25-um CMOS," iEEE Journal of Solid-State Circuits, Vol. 34, No. 3, pp 292-303, 1999.

[2] T. W. Pan and A. A. Abidi, "A 50dB Variable Gain Amplifier Using Parasitic Bipolar Transistors in CMOS," IEEE Journal of Solid-State Cinuirs, Vol. 24, No. 4, pp 951- 961,1989.

[3] 2. Yan, M. J. Deen and D. S. Malbi, 'Qate-ControUed Lateral PNP BJT Characteris- tics, Modeling and Circuit Applications," IEEE Tmmactions on Elecmn Devices, Vol. 44, pp. 118-128,1997,

[4] J. R. Long and M. A. CopeIand, 'The Modeling, Characterization, and Design of Monolithic inductors for Silicon RF IC's," IEEE Journal of Solid-Sîate Circuits, V01.32, pp. 357-369, 1997.

[SI A. Valkodai and T. Manku, "Modeling and designing silicon thin-film inductors and transfomers using HSPICE for RFIC applications," htegration, the YLSljoumal, Vol 24, pp. 159-171,1997.

[6] H. Ronkainen, H. Kattelus and E. Tarvainen, 'SC compatible planar inductors on d i - con," IEE Proc. Circuits Devices Sysrem, Vol 144, pp. 29-35, 1997.

IV, 1-9 GHz CMOS Miers for W'iless Appücations University of Tomnto

Chapcer 4: Conclusions 78

Conclusions

This work was motivated by ihe demand for low-ver , low-çost, high fiequency ICs

for applications in wireless receivers. The thesis has targeted one of the most challengiag

parts of the receiver, the RF mixer and is aimed at designing low power 1.9 GHz CMOS

mixers for CDMA applications. Beiag a key cornpunent in the receiver, mixer dominates

the overaii performance. However, the ctiaileage in analyzing such highly nonlinear

networks makes it difficult to optimïze mixer design. Two monolithic RF rnixen were

designed and chatacterized in this thesis. Both of these mixers aot only reduce the power

consumption but also the LO power requirement.

The dual-gaie mixer, implemented in a 0.5 pn CMOS on SOI process, achieves a

power gain of 1.8 dB at 1.9 GHz, a noise figure of 9.8 dB, and an input referred intercept

point of -0.8 &m. The mixer requires a -5 dBm LO power and consumes 3 mA from a 1 V

power supply. The chip area is 1.44 mm2. Guidelines based on theoretical anaiysis and

airning at improviag the linearity of the mixer were proposed for the k t tirne.

The back-gate mixer, implemented in a 0.25 pm CMOS process, utilizes the uihetent

lateral biplar transistor in CMOS to achieve g a i performance at low v e r . The lateral

bipolar transistor was chacterized and an EbemMoU mode1 generated through ISE device

simulations and verified thruugh measMemetlu. The mixer achieves a power gain of 6.5 dB,

a noise figure of 9.7 dB, an input thirddrdet in- point of -3.5 dBm. It requks -6 dEm

IV, 1 9 GHz CMOS Mixers for Whless Applications University of Taronto

Chapter 4: Conclusions 79

LO and consumes 1.3 mA h m a 1 V power supply. The mixer is the k t mixer using the

composite device and operating at 1.9 GHz RF and 210 MHz iF tiequency.

Future work should focus on adyzing and reducing the noise figure in the dual-gate

mixer. The back-gate mixer using the laterai bipolar transistor also needs work to optimize

its performance. The simulation mode1 of the laterai bipolar transistor should be revised to

improve the accuracy on RF mode1 for the composite device developed.

IV, 19 GHz CMOS Mixers for Wilcss Applications University oCTomto

Appcndii A: Mixer Intemodulation Analysis 80

APPENDIX A

Mixer Intemodulation Analysis

The mixer model used in the analysis is shown in Fig. A. 1. Although al1 elements in the

circuit model contribute to the mixing process, the nonlinearity in id, is the most significant

one [LI and as such will be the only one considered in the analysis.

Fig. A. 1: Equivalent circuit of the dual-gate mixer

Applying Kirchhoff s Voltage Law to VI node resuits in

where the individuai components are identified in the figure.

Appendut A: Mier intemodulation Analysis 8 1

At the Vdsl node, the current id, can be expressed as

and

where VI and Vdsl are voltages at node VI and V b l respectivel~, gml and i h a are the

transconductance of FETl and FET2 respcctively and given by

j = 1,2 for FETl and FET2 respectively.

where is the threshold voltage of the transistors, y,, is the electmn mobility, Cox is the

oxide capacitance, L is the channel length, and W is the width, t,, is the oxide thickness, E,,

is the permittivity of SiO2

The gate to source capacitances are given by [2]

The non-linearity in id, can be descn'bed by

Appcndbt A: Muer Intermodulation Analysis 82

where a, 0 are Volterra series coefficients.

Obtaining VI tiom Equation A-1 substitutiag it into Equation A-2, and solving Equations

A-2 and A-3 for ids, and substituthg in Equation A-9 results in the Volterra series coeffi-

cients:

The thîrd order intermodulaiion product, 1M3' generated by two RF signals (q and a l ) at

frequency (2al-%) can be calculated by using the Volterra series coefficient a3(wl, q, q]

and letting *ali q =-q, it is uwlly assumed that the difference between aiand q i s

small and that they have the same amplitude. Then the input referred PIM3' is given by (31

The guidelines obtained h m Equation A-14 for l o w e ~ g PM' are:

r miniminng the width of FETl while mainiainiag reasonable gain,

increasing the LO power,

8 reducing the source impedance 2, associatecl with FET 1, and

Appendi A: Mixer Intermodulation Analysis 83

biasing FET2 for maximum transconductance while keep FET2 in the saturation

region.

In order to get intuitive results of Equation A-14, the parameters of the 0.5 p SOI

CMOS process were substituted into Equation A-14. These parameters are listed in Table

A.1. Fig. A.2 shows the dependence of PM3* on the channel widths of FETl (W 1) and

FET2 (W2) respectively. PM3' decreases as Wl decreases while it decreases sligbtly as W2

decreases. To minimize PM3-, W1 should be reduced. However, the conversion gain will

d e r when W1 is below 200 Pm. Therefore, there is a tradesff between gain and PIFr139.

Fig. A.3 shows PM3v as a fhction of the gate bias voltages VGl and vGI applied to FETl

and FET2. VGI has relatively no effect on PW3'. The peak region of PM3. corresponds to

the minimum transconductance of FETZ. Therefore, to minimize PIM3', FET2 should be

biased for maximum îransconductance. Tbe guidelines also applies to PM3 because PM3

and PIM3' are comlated1.

Table A. 1: Parameten used in the miser intermodulation calculation

1. This bas been verifid by both eimuiation and measuremente.

Appendii A: M i Intermodulation Analysis 84

Fig. A.2: PM' as a h c t i o n of tnuisistor's widths W1 and W2

(channel length=O.S pm, Vw=-20dBmr VLo=-SdBm, VGl=0.33V, VW=O.22V, Vdd=iV)

Fig. A.3: PM- as a function of bias voltages Wl=2ûûpm, Wateoopm, channel legthPO.6~ V p - W B m , Vw6dBm, Vdd=lV)

Maple V was used for syrnboiic computation.

A~ucndix A: Mixer Intermodulation Analvsis 85

Reference

[l] J. Fikart and P. Acimovic, "Single-ended Mixer with Reduced LO Penetration," IEEE Pacgc Rim Confrence on Communications, Computers and Signal Pmcessing, pp 64- 66, 1991.

[2] D. A. Johns and K. Martin, "Analog integrated Circuit Design," John Wiley & Sons Inc, 1997.

[3] W. Yu S. Sen and B. H. Leung, "Distortion Analysis of MOS Track-and-Hold Sam- pihg Mixers Using Tirne-Varying Volterra Series," IEEE Transactions on Cimits and Systems - II: Analog and Digital Signal Pmcessing, Vol, 46, pp. 10 1-1 13, 1999.

Appcndix 8: Paramciers for Latcral BJï lkvicc Simulation 86

APPENDIX B

Parameters for Lateral BJT Device Simulation

Table B. 1: Parameters for Lateral BJT Device Simulation

LDD region n-well paubetrate

Gauseian

Gaueeian

Roflle type II Gausman Gauseian

diffusion Laterel facîor

Species Bomn Bomn Active

Conœntra- tion

Arsenic Active Con-

Phospho- nie Active Concentra-

tion

Bomn Active Con- centration œntration

Peak concentration

Junetion concan- tration

Junr 11 0.15 pn

deptà

Active Conœntra-

tion

6 x l d O d

3 ~ 1 0 ' ~ cmJ

1 V, 19 GH2 CMOS M i for Wucless Applications University of Tmnto

Appendix C: Power Convmion hble 87

APPENDIX C

Power Conversion Table

Table C. 1 : Power Conversion Table

1 V, 19 GHz CMOS Mûers for Wuclas Applications University of Tomnto

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