ACCESS IC LAB
Graduate Institute of Electronics Engineering, NTU
101-1 Under-Graduate ProjectTechniques in VLSI design
Speaker: Yu-Min LinAdvisor: Prof. An-Yeu Wu
Date: 2012/10/23
Some slides come from Prof. Chien’s course — DSP in VLSI Design
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OutlineTechniques in VLSI design
Iteration BoundPipelining & ParallelRetimingUnfolding / Folding
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Critical PathThe path with the longest computation time
among all paths that contain zero delays
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Loop BoundLoop — A directed path that begins and ends
at the same node
Loop Bound — The lower bound on the loop computation timeLoop Bound T = t / wt — loop computation timew — # of delays in the loop
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Iteration BoundCritical Loop —
The loop with the maximum loop boundIteration Bound —
Loop bound of the critical loop
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Iteration Bound
Iteration bound is the lower bound on the sample/clock period of the DSP program regardless of the amount of computing resources available
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Pipelining & ParallelPipelining and parallel are the most important
design techniques in VLSI DSP systems
Pipelining — Different function units working in parallel
Parallel — Duplicated function units working in parallel
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Pipelining & Parallel
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PipeliningHow to do pipelining?
Put pipelining registers across an feed-forward cutset
Drawbacks of Pipelining — Increasing latencyIncreasing the number of registers
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Parallel
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Parallel
Drawbacks of Pipelining — Large hardware cost
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RetimingRetiming —
A transformation technique used to change the locations of delay elements in circuit without affecting the input/output characteristics
Applications of retiming — Reducing the clock periodReducing the number of registers
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Retiming
Pipelining is a special case of retiming
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RetimingReducing the clock period —
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RetimingReducing the number of registers —
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UnfoldingUnfolding is similar to parallel processing
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UnfoldingSample/Clock period reduction —
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Folding
