Abstract— A 10b 150MS/s 0.4mm2 pipeline ADC is implemented in a 45nm CMOS process. The input SHA, employing four charge-redistributed capacitors, converts single-ended or differential input signals of 1.2Vpp to differential outputs of 0.8Vpp for a low supply voltage of 1.1V. The process-insensitive high-gain amplifiers in the SHA and MDACs are based on gain-boosting, pseudo-differential output pair, and continuous-time common-mode feedback circuits to overcome various performance limitations that are observed in deep nanometer CMOS technologies. The MDAC2 and MDAC3 share a single high-gain amplifier to reduce the input memory effect, chip area, and power dissipation. The measured DNL and INL are within 1.06 and 1.29LSB, respectively. At 150MS/s, the prototype ADC shows a maximum SNDR of 51.8dB and a maximum SFDR of 63.7dB with a 1.2Vpp sinusoidal input and consumes 47.3mW.
I. INTRODUCTION With the recent development of digital signal processing,
high-resolution high-speed video systems such as HDTV have been increasingly on demand [1]. The analog front-end of the HDTV system essentially requires high-performance A/D converters (ADCs) with an 8 to 10 effective number of bits and a high sampling rate over 150MS/s. Particularly, the related core circuits for the system have been developed by using deep nanometer CMOS technologies for low power consumption and small area. However, conventional deep nanometer CMOS technologies cause a lot of circuit limitations, making it difficult to design high-performance amplifiers [2]. Specifically, the amplifiers suffer from a low output impedance of transistors and a reduced signal swing range from scaled supply voltages. Thereby, it is not easy to simultaneously obtain high gain, high swing, and wide bandwidth of the amplifiers for high-performance ADCs. The proposed ADC employs various circuit design schemes to overcome the limitations of nanometer technologies.
II. OVERALL ADC ARCHITECTURE The proposed 10b 150MS/s 45nm four-step pipeline ADC
of Fig. 1 optimizes area and power dissipation at target
specifications. Each of the first three stages decides 3 bits while the last stage decides 4 bits. The nonlinear errors between stages are corrected in the digital logic to obtain the final 10 bits. The input sample-and-hold amplifier (SHA), employing four charge-redistributed capacitors, reduces single-ended or differential input signals of 1.2Vpp to differential signals of 0.8Vpp considering a low supply voltage of 1.1V [3]. The process-insensitive amplifiers in the SHA and the multiplying D/A converters (MDACs) adopt various circuit design techniques, such as gain-boosting, cascode current mirror, and continuous-time common-mode feedback (CMFB) circuits, to solve the limitations of deep nanometer CMOS technologies. The shared high-gain amplifier for the MDAC2 and MDAC3 minimizes input memory effect and reduces area and power dissipation [4].
Fig. 1. Proposed 10b 150MS/s 45nm CMOS ADC.
III. PROPOSED PROCESS-INSENSITIVE AMPLIFIER The input SHA and the MDACs of the proposed ADC
basically require a high-gain amplifier to maintain target linearity without any distortion. In addition, the wide input bandwidth and high phase margin are also required for a high- speed operation exceeding 150MS/s. However, the reduced output impedance due to a short channel-length effect in deep nanometer CMOS technologies makes it extremely
Fig. 2. High-performance op-amp based on gain-boosting and continuous-time CMFB circuits in the MDAC1.
challenging to design a high-gain amplifier. A three-stage amplifier has been proposed to achieve the required high gain; however, the multi-stage amplifier needs a complex frequency-compensation technique to remove zeros in the right-half plane, affecting the stability of the overall system. As a result, the circuits become complicated; moreover, the area and power consumption of the amplifier are correspondingly increased [5].
The proposed ADC employs a two-stage amplifier with a
gain-boosting technique to achieve a high DC gain of 81.5dB, as shown in the MDAC1 amplifier of Fig. 2. The first stage of M1 to M13 is based on a folded-cascode topology with a gain-boosting circuit for the required high gain, while a pseudo-differential common-source topology of M14 to M17 is selected for the second stage to meet a wide signal-swing range of 0.8Vpp at a low supply voltage of 1.1V. The gain-boosting amplifiers, GBP and GBN, are also based on a folded-cascode architecture. As an example, the amplifier, GBN, in the NMOS cascode output is illustrated in Fig. 3. The bias voltages for the gain-boosting amplifiers are shared with the main amplifier of the MDAC1. The SHA employs the Miller compensation, which is more convenient to satisfy the required bandwidth and phase margin for 150MS/s operation with a zero-nulling resistor. In contrast, the MDACs prefer the cascode compensation for better signal settling behavior, achieving a higher phase margin than the Miller compensation with the same power consumption [6].
On the other hand, device mismatches caused by the
fabrication procedure generate an input offset voltage, a nonzero common-mode-to-differential-mode gain, and other undesired distortions in the amplifier [7]. Specifically, the device mismatch problems are getting worse in deep nanometer CMOS technologies because of the reduced output impedance due to the short channel-length effect [8]. Therefore, the MOS transistors for the amplifier need to be composed of multiple unit devices for high matching and tracking accuracy, as shown in Fig. 3. The performance
degradation due to the channel-length modulation effect is prevented considerably with the cascode bias circuits of M1 to M4, as shown in Fig. 3.
Fig. 3. Gain-boosting amplifier at the NMOS cascade output.
A CMFB circuit is usually implemented in switched-
capacitor circuits and shows low power consumption and high linearity, while large size capacitors are required to reduce a clock feed-through effect. The resultant large output loading capacitance can limit the bandwidth of the amplifier significantly [9]-[10]. A continuous-time CMFB circuit of M18 to M24, as shown in Fig. 2, requires half the number of capacitors than the dynamic CMFB circuit, which is very helpful for low power and small chip area of the proposed ADC. The continuous-time CMFB circuit needs to have a bandwidth and phase margin corresponding to the differential signal path in the main amplifier of the SHA and MDACs for stable dynamic operation. As shown in Fig. 2, since the main amplifier of M1 to M13 and the CMFB circuit of M18 to M24 share the identical path from the first-stage output to the second-stage output [11], two poles of the main and CMFB amplifiers are placed at the similar locations. However, the open-loop gain of the CMFB circuit should be designed to be a quarter of that of the MDAC1 amplifier, considering that the feedback factors of the MDAC1 amplifier and the CMFB circuit are 1/4 and 1, respectively. The gain adjustment can be easily realized by properly sizing the MOS transistor ratio
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between the M10-M13 pair for the main amplifier and the M11-M12 pair for the CMFB circuit.
The MDAC2 and MDAC3 share a single high-gain
amplifier to reduce power consumption and chip area. Recently, the amplifier sharing technique with two separate differential pairs has been employed to remove the input memory effect caused by having no extra reset the input summing nodes of an amplifier [5]. However, it suffers from the performance degradation due to the internal input switching operating of the amplifier. Thus, the proposed MDAC2 and MDAC3 are consisted of a single high-gain amplifier with single differential input pairs and two selection switches, as shown in Fig. 4. The memory effect is minimized by a sufficient high-gain amplifier. The two selection switches size are increased for the required signal settling within no influence offset voltage by clock feed-through.
Fig. 4. Op-amp sharing technique in MDAC2 and MDAC3.
IV. MEASUREMENT RESULTS The proposed 10b 150MS/s ADC is implemented in a
45nm CMOS process using vertical-parallel plate capacitors. The die photo of the prototype ADC in Fig. 5 shows an active die area of 0.40mm2. The on-chip MOS decoupling capacitors of 300pF in the idle space of the ADC reduce the signal interference between functional blocks, EMI, power supply noise, and high-speed transient glitches.
Fig. 5. Die chip photo of the prototype ADC.
The ADC consumes 47.3mW at 150MS/s with a 3.3V supply only for the analog input switches and with a 1.1V supply for the remaining overall circuits. The measured maximum differential non-linearity (DNL) and integral non-linearity (INL) are within 0.80LSB and 1.71LSB, respectively, as shown in Fig. 6.
Fig. 6. Measured DNL and INL of the ADC.
The signal-to-noise-and-distortion ratio (SNDR) and
spurious-free dynamic range (SFDR) are measured to be 51.8dB and 63.7dB at 150MS/s, respectively, with a sinusoidal differential input of 1.2Vpp and 4MHz, as shown in Fig. 7. Digital output data captured at a quarter rate of the full conversion speed of 150MS/s by the on-chip decimator.
Fig. 7. Measured FFT spectrum of the prototype ADC.
Fig. 8 shows the measured dynamic performance of the
ADC as a function of input frequency. As input frequencies increase up to 80MHz at 150MS/s, the measured SNDR and SFDR with a differential input are maintained over 50dB and 62dB. The SNDR and SFDR of Fig. 9 are measured with different sampling frequencies up to 200MS/s at a 4MHz input signal. The SNDR and SFDR with a differential input are maintained over 51dB and 63dB, respectively, up to 150MS/s. The measured performance of the prototype ADC is summarized in Table 1.
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Fig. 8. Measured SNDR and SFDR versus input frequency.
Fig. 9. Measured SNDR and SFDR versus sampling frequency.
Table 1. Performance summary of the prototype ADC.
V. CONCLUSIONS The proposed 10b 150MS/s prototype ADC is
implemented in a 45nm CMOS pipeline ADC based on process-insensitive high-gain amplifiers for high-definition video applications. The two-stage amplifiers in the SHA and MDACs employ various circuit techniques such as gain-
boosting, pseudo-differential common-source pair, high matching accuracy with multiple unit devices, cascode current mirrors, continuous-time CMFB, and amplifier sharing to overcome many limitations observed in conventional nanometer CMOS technologies. The prototype ADC with an active die area of 0.40mm2 shows a maximum SNDR and SFDR of 51.8dB and 63.7dB, respectively, and a power consumption of 47.3mW at 150MS/s.
ACKNOWLEDGMENT This work was supported by the IDEC of KAIST,
Samsung Electronics, the Ministry of Knowledge, Economy, Korea, under the University ITRC program supervised by the National IT Industry Promotion Agency (NIPA-2012-H0301-12-1007), and the Basic Science Research Program through the National Research Foundation funded by the Ministry of Education, Science and Technology (2012-000-2297).
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