10T SRAM MEMORY CELL FOR LEAKAGE REDUCTION

AND LOW POWER OPERATIONS

SHAIK YASMEEN SULTANA , M.Tech

Dr. BHOOPAL RAO GANGADARI, Associate Professor

DEPARTMENT OF ECE(VLSI)

NALLA MALLA REDDY ENGINEERING COLLEGE, HYDERABAD

ABSTRACT:

This paper focuses on 10T SRAM Memory Cell for

leakage reduction and low power operations. 4T read

port with RBL decouples at single end in10T static

access memory for reducing power and leakage.

Based on the stored data bit RBL discharges. at

o.5vdd cells supply voltage RBL is precharged.

During operations at read line complementary data

node QB , virtual rail of power interfaces to RBL

through pass transistor gate.RBL Leakage decreases

at virtual rail having control dynamically. For read -

1 ,at vdd RBL increases and for read-0 ,it discharges

at vss.virtual power rail is connected to true supply

level at read operation. At hold and write mode same

RBL recharges with virtual power.In 45nm cmos

technology, 10t sram cell is proposed with 2.35

times the size of 6T.It has 50% of reduction in

dissipation of read power than 6transistor cell. RBL

leakage also decreases and read static noise margin

increases 2.7 times the 6T .Current ratio during ON

and OFF mode has great improvements. Proposed

design results in low power ,low area ,low size and

low current- voltage characteristics at 27oc kept at

low leakage value.6.33um( approxi)power is

observed at current of 0.1ma with 3.81ns delay..

keywords: 10T,6T,low power, precharge,read bit line

(RBL),single ended SE,SRAM,virtual rail.

I.INTRODUCTION:

POWER dissimenation has attained a highest priority

design limitations to success the implementation, and

system, architecture and circuit level techniques at

low power are found [1]- [4]. SRAMs part on a

system-on-chip (SoC) is everincreasing in digital

macro is most important and lowering the power

dissemination of SRAM will raise the SoC reliability

and also increase the yield along with total power

dissimenation. Infact 6T SRAM cell is limitless

application with some restrictions. 6T SRAM has

both varying write and read conditions at read static

noise margin (RSNM) loss. In recent nanometer

technologies SRAM design has factors like write

stability, read stability, leakage currents, variability,

power dissimenation, reduction of cell supply, power

dissipation and ratio of ION to IOFF at bitline

(BL)[5]-[6]. obtaining specific yield becoming hard

due to growing process variations including write and

read support circuits acquired at the amount of

power dissimenation ,area or speed to raise the

write/read stability and the number of cells in a one

column at novel designs and techniques [7].

Active power dissimenation reduces due to depletion

of the supply voltage is simple technique. Due to

RSNM degradation power supply of 6T SRAM can’t

be decreased. Many SRAM cell have been proposed

that raise RSNM including single ended (SE) 8T ,9T

,10Tand differential 7T ,8T 9T, 10T[8]-[18]. Also, to

enlarge the write margin, and reduce the leakage

power dissimenation differentiated to operating the

memory array at a higher supply voltage or bitcell

transistor upsizing at efficient method for many

SRAM support techniques .A 10T cell use virtual

negative rail at read port to acuire decreasing BL

leakage, while Kanda et al. used grounded wordline

voltage for 2 orders in leakage currents to reduce

magnitude and row-by-row dynamic control of cell

supply voltage [19]-[23]. In 65nm technology

10TSRAM design was analysed and low switching

power obtained[30].In this paper, we present

10TSRAM design having reduction of leakage values

and operations done under low power .To implement

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Volume VIII, Issue II, February/2019

ISSN NO:2236-6124

Page No:195

proposed plan, designing of 4T read port is done.

Based on the condition of stored bit read port

constantly charges and discharges RBL. RBL leakage

is reduced when read port power challenges under

dynamic control considerably.

II. RELATED WORKS OF SRAM DESIGNS:

SRAM cell should fastly work under write ,read and

hold mode .Single bit of information is deposited by

using cross coupled inverters positive feedback in

sram cell. Write and read operations are provided

mechanism by Access transistors. supply voltage

precharge is distributed to BL and BLB pairs for

acessing. write driver discharges precharged BLs to

operate write mode.

Fig.16TSRAM design

Fig. 1 6T SRAM cells, single columnM of cell is

retrieved in read mode with data Qa=0 and M −1

cells in hold mode. Leakage units are classified andM

−1 cells accumulate data Qu= 1 for unnecessary

leakage . accessed cells AL and NL has Iread flows

from BL to the VSS and BL voltage is lowered. BL

leakage is indicated by BL unaccessed cell .BL

leakage has IuLeak0 as main part and IuLeak1 is

ignored. for unaccessed cell VDS of ARs is large

and AL is small (0 to VBL). differential BL voltage

issue is lowered by leakage portion. outmost BL

leakage may lower BLB voltage sufficient to

assemble invalid read when single column has more

cells .consequently, Iread should be higher than (M

−1)×IuLeak0, where M is the number of cells in a

single column.

During read operation, the read current way has Qa=0

storage and voltage rise for 6T cell internal

node.transistor sizing has rising voltage V

dependency. For efficient read operation, β ratio is

defined as (((W/L)N)/((W/L)A)) should be bigger

than 1 (typically 2 to 3) [5]. The exposure of an

SRAM cells internal nodes is expressed into metrics

WNM/write trip point (WTP) ,RSNM, and HSNM

during write, hold and read mode respectively.

differential BL voltage (VBL) decreases and requires

the raise in WL pulse duration. A larger read pulse

may cause dynamic uncertainty and raises the power

dissemination[25].similarly , for efficient write

operation,6T access transistors should be tough

enough to acquise the pull-up pMOS transistors.

Thus, γ ratio is defined as (((W/L)P)/((W/L)A))

should be lower than 1.infact, a tough pMOS is

useful for read operation to lower V and a delicate

pull-down nMOS is useful for write operation

.therefore, proper sizing is required for specific

conditions and application. The existing 6T SRAM

has two BL s are BL and BLB. BL is decreased for

each read operation. We shall design 6T SRAM by

BL with an activity factor of 1. Therefore, the

dynamic read power dissemination of 6T is given as

Pd6T = N ×CBL ×VDD× VBL × f (1)

where N is the number of cells connected in a

wordline (word size), CBL is the overall switching

BL capacitance, VDD is the supply voltage precharge

, and f is the frequency of operation. A minimum

VBL of 100 mV is necessary for proper sensing

taking into leakage, the process parameter

fluctuations and noise as CBL does not decrease in

view of engineering . Leakage power dissemination

is largely data dependent. During the hold 6T SRAM

subthreshold leakage current can be estimated as

( 2)

where M × N is the size of the SRAM array, vt is the

thermal voltage (≈26 mV at 27 °C), , Vth is the

threshold voltage of working transistor, η is the

technology-dependent subthreshold and I0 is the

technology-dependent coefficient and is the current

leakage at VGS = Vth of lowest sized transistor,[26].

In Fig. 1, unaccessed cell AR is OFF at VGS = 0 V

whereas VDS = VDD, which release high leakage.

Actually 6TSRAM contain varying write and read

needs[5] and transistor sizing is not possible

independently. read current tranmits down internal

node of cell [27] when 6T receives RSNM situation

[27], and it moreover reduces with VDD estimations

[28]. According to baseline model , 6T contain total a

high power dissemination, and BL leakages. dynamic

power dissemination is decreased by using low power

operations like charge sharing and vertical BL[29],

[30] [31] and the leakages by using virtual rails [22],

[23]

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.

Fig. 2 SRAM designs showing read ports at

(a)6T(b)8T(c)9T(d)9T(e)10T

In Fig. 2(a) 6T SRAM cell read port is shown which

features the internal node Q in the read current way.

Many varying bit cells and techniques are proposed

in the literature for improving SRAM cell stability,

leakage current reductions and acquiring low power

operation distinguished with the existed 6T design.

in Fig. 2(b) shows 2T read port is joined in 8T

SRAM cell separately and it solves the situation of

read stability. higher RSNM is obtained due to

isolation of read current way and its internal nodes

and 8T read port sizing is possible independently

without disturbing the write operation.

In 6T SRAM read operation, one BL is at the VDD

whereas another decreases by VBL unit. 8T SRAM

has only one BL (RBL) and lowers at the VDD level

based on the bit read. the sensing of SE BL is done

using different circuits such as domino sensing based

on full VDD swing ON the local-BL; psuedo-

differential based on reference signal; and ac coupled

sensing based on capacitors [32]. Utilizing a

reference-based sense amplifier , only a low voltage

difference is needed. In 6T case , BL always serves

as a reference, but in 8T case , reference is set at

VDD− VBL. Therefore, for read-1, RBL

remains at VDD and Vref −VRBL =− VBL is

sensed. For a read-0, RBL should lowers to produce

+ VBL of the sensing margin, which meant RBL

should decrease by y2× VBL, such that

Vref−VRBL = VDD− VBL−(VDD−2×

VBL)= + VBL.

for proposed cell sensing, Vref is kept at VDD/2

during every read operation . for every read

operation VBL sensing is needed and RBL of the

LP10T may decrease or increase from VDD/2

basedon the data read.

according to large differential voltage needs 8T

contain 0.5 activity factor and same dynamic power

disseminations of 6T SRAM . inorder to distribute

same performance differential voltage is developed

in similar time (Tread). RBL leakages are highly

exhibited due to provision of great Iread at 8T read

port sizing.

Fig. 2(c) shows SE 9T SRAM using 3T read port. In

this the M2 stacks between M1 and M3 to decrease

leakage at RBL[11]. It has same dynamic power

dissemination and Write performance as 8T. speed

degrades distinguishly with 6T and 8T cell because

of 3T read path.

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Fig. 2(d)shows, Another creative design of 9T SRAM

cell utilizing 3T read port[10]. leakage current is

provided to the RBL into M3 to reduce the BL

leakage and RBL remains higher position. It

decreases at the leakage currents. sensing margin is

improved and better performance is achieved

because of 2T (M1-M2) read current way .even

though dynamic power is same as 6T and total static

power is raised up .

Fig. 2(e) shows A 10T cell proposed joins a 4T read

port for an SE read[12]. The cell was modeled for

subthreshold operation to provide ultralow leakage.

RBL leakage instantly decreases at the rate of

performance and area.

III. PROPOSED TECHNIQUE OF 10T SRAM

CELL

The proposed 10T SRAM cell with RBL is shown in

Fig. 3. In this 4T read port joined to 6T cell to

separate internal nodes for read operation. Read port

comprises of an INV P1-N1 operated by node QB,

with transmission gate (TG) P2-N2. during the read

function, output (Z) of the INV connects RBL into

TG controlled by control signals. both VVDD and

VVSS, are controlled dynamically to boost read port.

These control signals run horizontally with true rail

gains at read operation. both virtual rails have the

same RBL precharge level to reduce RBL leakage. In

our proposed 45nm technology ,we precharge and

discharge cell at vdd/2 to RBL.For every read cycle

RBL has small voltage value at vdd/2.TG activates to

connect RBL to node Z and R goes low and high

during read operation.P1connects to Vdd and N1is

off at Qb=0.fromP1-TG read current runs from vdd to

RBL.At RBL level voltage increases to vdd.At read

mode P1 is OFF and N1 connected to Vss for read

0..From N1-TG read current flows from RBL to

Gnd.For efficient working read signals are boosted to

achieve high current flow.

For read 0,power dissemination is given by

P0 =α0 ×CBL ×VDD 2 × VBL× f (3)

For read1 ,power dissemination is given by

P1 = α1 ×CBL ×(VDD− VDD/2)× VBL × f

= α1 ×CBL ×VDD 2 × VBL × f (4)

Probability equality for both read 0 and read1 power

dissemination is given by

Pd10T = N ×CBL ×VDD 2 × VBL× f. (5)

Leakage reduces due to virtual rails nonread remains

at voltage level vdd/2 equally. The power

dissemination due to virtual rails VVSS is given by

Pvvss =1×Cvvss×((VDD)/2)×((VDD)/2)× f. (6)

total power penalty for both virtual rails are

Pv =CBL ×VDD×1 /16 × f (7)

MOS characteristics at 27oc are observed for 10T

SRAM and simulated.

Based on the design all current ,voltage,delay and

gain are obtained for low power and low leakage

values. Layouts and transistor are fixed based on

45nm technology basis.

Fig.3.Proposed 10TSRAM design in 45nm

technology

In proposed 45nm technology, Wmin of 80 nm and

Lmin of 40 nm are used. Poly–poly spacing is 90 nm

and polycontacts is 110nm with increased sizes of

contacts and vias are designed.

Fig.4.Layout of 10TSRAM design in 45nm

technology

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COMPARISON TABLE

PARAMRTE

R

6T 10T-

90nm

10T-

45nm

Power 0.201

mw(201uw

)

11.264

uw

6.33uw

Delay 6ns 4.894ns 3.817ns

Current 0.234ma 0.987m

a

0.172m

a

voltage 1.17v 1.14v 0.4v

temperature 27oc 27oc 27oc

IV. RESULTS

Output simulations of 10TSRAM

Fig.5.Transient waveform of 10TSRAM at low

power

Fig.6.Voltage vs Time analysis

Fig.7.Voltage and Current analysis

Fig.8.voltage vs voltage(gain) analysis

Fig.9.delay analysis

MOS characteristics simulations at 27 oc temperature

Fig.10.Id vs Vd

Fig..11.Id vs Vg

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Fig.12.logId vs Vg

Fig.13.Threshold voltage

Fig.14.Capacitance

V. CONCLUSION

In this paper we designed 10T SRAM in 45nm

technology .precharging and discharging operations

are done at RBL for both read0 and read1 with

supply voltage of vdd/2.performance figure

(mV/μW)is 1.78times of 6T is obtained in 45nm

technology at 0.4v. . Proposed design results in low

power ,low area ,low size and low current- voltage

characteristics at 27oc kept at low leakage

value.6.33um( approxi)power is observed at current

of 0.1ma with 3.81ns delay.

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Authors profile:

Shaik Yasmeen Sultana

was born in Hyderabad,India in 1996.

She received the Bachelor of Technology

(B.Tech)degree in Electronics and Communication

Engineering from Teegala Krishna Reddy

Engineering College, Meerpet, Hyderabad, India in

2017. she is currently pursuing the Master of

Technology(M.Tech) degree in Vlsi System Design

in ECE from Nalla Malla Reddy Engineering

College, Ghatkesar, Medchal-Malkajgiri dist., India.

Her current research interests include 10T SRAM

memory cell for leakage reduction and low power

operations design for vlsi system design applications.

Dr. Bhoopal Rao Gangadari

received the Bachelor of Technology (B.Tech.) in

Electronics and Communication Engineering, from

M.T.E.C, Affiliated to J.N.T.U Hyderabad in May

2004., Master of Technology (M.Tech.) (VLSI

System Design) in Electronics and Communication

Engineering from National Institute of Technology

Tiruchirrapalli , Tiruchirrapalli, May 2010 and

Doctor of Philosophy (Ph.D.)(VLSI) in Electronics

and Electrical Engineering from Indian Institute of

Technology Guwahati, Guwahati. . He is an associate

professor in Nalla Malla Reddy Engineering College

in ECE Department.He is having 5years academic

experience and 6 years of research experience. He

has published 9 research papers in reputed

international journals/conferences .His area of

interest includes Cryptography Algorithms, Cyber

Security, Low Power Digital VLSI Architectures and

Analog Circuits. His current research interests

include10T SRAM memory cell for leakage

reduction and low power operations design for vlsi

system design applications.

International Journal of Research

Volume VIII, Issue II, February/2019

ISSN NO:2236-6124

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