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Memorijski sistem
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Control
Datapath
Memory
Processor
Input
Output
Since 1946 all computers have had 5 components
The Big Picture
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Tipovi memorija
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Hijerarhijska organizacija memorije
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Levels in Memory Hierarchy
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Microprocessor performance improved 55% per year
since 1987, and 35% per year until 1986Memory technology improvements aim primarily
at increasing DRAM capacity not DRAM speed
Processor-DRAM Gap
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Relative processor/memory speed
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Relative processor/memory speed
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MOS memories
RAM's ROM's
DRAMSRAM ROM
FLASHEEPROMEPROM
VOLATILE
Power off: contents lost
NON VOLATILE
Power off : contents kept
Volatile vs non Volatile Types ofMemories
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Percentage of Usage
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Typical Applications of DRAM
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Trends in
DRAM main
memory.19901980 2000 2010
Numberofme
morychips
Calendar year
1
10
100
1000
LargePCs
Work-
stations
Servers
Super-computers
1MB
4MB
16MB
64MB
256MB
1GB
4GB
16GB
64GB
256GB
1TB
Computer class
Memory size
SmallPCs
DRAM Evolution
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MRAM can replace many ofthers types of memory including
SRAM, DRAM, ROM, EEPROM, Flash EEPROM, andferoelectric RAM (FRAM) . Prediction are crystalline
structures that users grow on silicon.
Magnetic RAM as Universal Memory
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Veliki kraj u odnosu na mali kraj
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Konverzija BE u LE
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Prezentacija u BE i LE
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Tipovi poluprovodnikih memorija
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Struktura memorijskog ipa
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Address
translation
Rowdecoding
& read out
Columndecoding
& selection
Tagcomparison
& validation
Pipelined and Interleaved Memory
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Interleaved memory is more flexible than wide-access memory in
that it can handle multiple independent accesses at once.
Add-ress
Addresses thatare 0 mod 4
Addresses thatare 2 mod 4
Addresses thatare 1 mod 4
Addresses thatare 3 mod 4
Return
dataData
in
Dataout
Dispatch(based on
2 LSBs ofaddress)
Bus cycle
Memory cycle
0
1
2
3
0
1
2
3
Module accessed
Time
Memory Interleaving
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Tri naina organizacije 96-bitne memorije
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Povezivanje memorije kod 32-bitnihprocesora
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Memorijska adresa i memorijska mapa
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Primer 1: Povezivanja memorije kod 32-bitnog procesora
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Primer 1: Memorijska mapa
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Primer 1: Realizacija dekodera adresa
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Primer 2: Memorijska mapa i dekoder kada su M1 i M2veliine 1 MB
P i 3 S l k ij MS bi
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Primer 3: Selekcija na osnovu MS bita
P lik j ij kih
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Preslikavanje memorijskih prostora
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Tipian adresni dekoder
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Realizacija jedne adresne eme
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Realizacija dekodiranja adresa korienjem komparatora
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Realizacija dekodera adresa korienjem PROM-a
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Struktura PLD-a
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ROM model sa programibilnim OR poljem
P L d l fik i OR lj
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PAL model sa fiksnim OR poljem
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PAL model sa programibilnim AND i OR poljima
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Izgled makroelije
I l d FPGA k l
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Izgled FPGA kola
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Izgled CPLD elije
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Tipian nain povezivanja memorije
Tajming memorije
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Tajming memorije
T j i ikl i ij
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Tajming ciklusa upisa u memoriju
T j i ikl it j i ij
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Tajming ciklusa itanja iz memorije
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Struktura dinamike memorije
Dinamika memorija lo ika ema
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Dinamika memorija logika ema
P i j DRAM
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Povezivanje DRAM-ova
P i j di ikih ij
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Povezivanje dinamikih memorija
Tajming kod dinamikih memorija
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Tajming kod dinamikih memorija
P i j di ikih ij
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Povezivanje dinamikih memorija
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Virtuelna fizika adresa
Poloaj kea u memorijskoj hijerarhiji
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Poloaj kea u memorijskoj hijerarhiji
Memorijski moduli
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Memorijski moduli
Memorijski moduli
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M mor js mo u
Dual port memorija
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Dual-port memorija
Struktura krunog bafera
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Struktura krunog bafera
P i i d k b f
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Princip rada krunog bafera
A ij ti n m m ij
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Asocijativna memorija
Asocijativna memorija
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Asocijativna memorija
Memorija u sistemu
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Memorija u sistemu
M ij i t i b j
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Memorija u sistemu sa veim brojemprocesora
Ke memorija
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Princip rada kea se zasniva na lokalnosti- koja moe biti:
CPU
adrese
podaci
ke
kontroler
keglavna
memorija
podaci
adrese
podaci
Ke kontrolerposreduje izmedju CPU-a i memorijskogsistema koga ine ke i glavna memorija.
vremenska lokalnost
prostorna lokalnost
Ke memorija
The Need for a Cache
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Cache memories act as intermediaries between the superfast
processor and the much slower main memory.
Level-2cache
Mainmemory
CPU CPUregisters
Level-1cache
Level-2cache
Mainmemory
CPU CPUregisters
Level-1cache
(a) Level 2 between level 1 and main (b) Level 2 connected tobackside bus
One level of cache with hit rateh
Ceff = hCfast+ (1h)(Cslow+ Cfast) = Cfast+ (1h)Cslow
The Need for a Cache
Performance of a Two-Level Cache
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Example
A system with L1 and L2 caches has a CPI of 1.2 with no cache miss.
There are 1.1 memory accesses on average per instruction.
What is the effective CPI with cache misses factored in?
What are the effective hit rate and miss penalty overall if L1 and L2
caches are modeled as a single cache?
Level Local hit rate Miss penaltyL1 95 % 8 cyclesL2 80 % 60 cycles
Level-2cache
Mainmemory
CPU CPUregisters
Level-1cache
8cycles
60cycles
95%4%
1%
Solution
Ceff = Cfast+ (1h1)[Cmedium+ (1h2)Cslow]
Because Cfastis included in the CPI of 1.2, we must account for the rest
CPI = 1.2 + 1.1(10.95)[8 + (10.8)60] = 1.2 + 1.10.0520 = 2.3
Overall: hit rate 99% (95% + 80% of 5%), miss penalty 60 cycles
Performance of a Two Level CacheSystem
Cache Memory Design Parameters
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Cache size(in bytes or words). A larger cache can hold more of the
programs useful data but is more costly and likely to be slower.Blockor cache-line size(unit of data transfer between cache and main).
With a larger cache line, more data is brought in cache with each miss.
This can improve the hit rate but also may bring low-utility data in.
Placement policy. Determining where an incoming cache line is stored.
More flexible policies imply higher hardware cost and may or may not
have performance benefits (due to more complex data location).
Replacement policy. Determining which of several existing cache blocks
(into which a new cache line can be mapped) should be overwritten.
Typical policies: choosing a random or the least recently used block.Write policy. Determining if updates to cache words are immediately
forwarded to main (write-through) or modified blocks are copied back to
main if and when they must be replaced (write-backor copy-back).
Cache Memory Design Parameters
Temporal- and spatial-locality of
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p p yreference
When exhibiting spatial locality, a program accesses neighboring
memory locations.
When displaying temporal localityof reference a program repeatedly
accesses the same memory location during a short time period.
Both forms of locality occur in the following Pascal code segment:
Temporal locality- the CPU accesses i at three points in a short time
period.Spatial locality- assuming that Pascal stores the elements of A into
consecutive memory locations6, each loop iteration accesses adjacent
memory locations.
What Makes a Cache Work?
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Assuming no conflict in address
mapping, the cache will hold a
small program loop in its entirety,
leading to fast execution.
9-instructionprogram loop
Address mapping(many-to-one)
Cache
memory
Main
memory
Cache line/block(unit of transfer
between main andcache memories)
Temporal locality
Spatial locality
What Makes a Cache Work?
Temporal and Spatial Localities
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Addresses
Time
From Peter Dennings CACMpaper,
July 2005 (Vol. 48, No. 7, pp. 19-24)
Temporal:
Accesses to the
same address
are typically
clustered in time
Spatial:
When a location
is accessed,
nearby locations
tend to be
accessed also
Working set
Temporal and Spatial Localities
Harvard arhitektura
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procesor
ke za
instrukcije
ke za
podatke
glavna memorija
pribavljanje
podataka
pribavljanje
instrukcija
Harvard arhitektura
L1 i L2 ke
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L1-ke
mikroprocesor
L2-ke
glavna
memorija
1
2
L1-ke
mikroprocesorglavna
memorija
L2-ke
12
backsidemagistralafrontsidemagistralafrontsidemagistrala
L1 i L2 ke
Poloaj kea u sistemu
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mikroprocesor ke
most
(bridge)glavna
memorija
procesorska / memorijska magistrala
sistemska / Ulazno-Izlazna magistrala
mikroprocesor
keglavna
memorija
most
magistrala procesora
memorijska magistrala
sistemska / Ulazno-Izlazna magistrala
Poloaj kea u sistemu
Poloaj kea u sistemu PC-a
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grafiki
kontroler
Host/ PCI
most
glavna
memorija
(DRAM)
CD-ROM
kontrolerPCI / ISA
most
proirenja
tastatura ,
mi
AGPSCSI-
Host
adapter
LAN-
kontroler
mikroprocesor
(host) saL1-keom
L2-ke(SRAM)
IDE
IDE
USB
USB
.
PCI
kartica:
ISA
kartica: audioflopi-disk
kontroler .
ISA-Bus
PCI-Bus
magistrala procesora (host magistrala)
Poloaj kea u sistemu PC a
Razlika u vremenima pristupa
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Razlika u vremenima pristupa
Gradivni delovi ke memorije
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Gradivni delovi ke memorije
Princip rada ke memorije
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Princip rada ke memorije
Ke memorija primer organizacije
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Ke memorija primer organizacije
Ke memorija primer realizacije u dva nivoa
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Ke memorija primer realizacije u dva nivoa
Asocijativna ke memorija
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031
Tag
Tag 0
Tag 1
Tag 2
Tag 2047
28
k0
k1
k2
k2047
...
linija 0
linija 2
linija 1
linija 2047
V D
V D
V D
V D
MUX / DEMUX
2
2
32
32 323232
selekcija bajta
selekcija rei
selekt
selekcija bajta uokviru rei
ka / sa magistrale
podataka
ke
pogodak
tagpogodatak
adresa
valid
pogodak
Asocijativna ke memorija
Asocijativna ke memorijasa FIFO politikom zamene
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Asocijativna ke memorija sa FIFO politikom zamene
Direktno preslikana ke memorija
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Direktno preslikana ke memorija
031
Tag
Tag 0
Tag 1
Tag 2
Tag 2047
linija 0
linija 2
linija 1
linija 2047
V D
V D
V D
V D
MUX / DEMUX
2
2
32
32 323232
selekcija bajta
selekcija rei
selekt
selekcija bajta uokviru rei
ka / sa magistralepodataka
kepogodak
tagpogodatak
adresa
validpogodak
Indeks
=
linija 0
linija 2
linija 1
linija 2047
11
17
17 1
1
1
dekod
eradresa
Primer direktno preslikane ke memorije
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rimer direktno preslikane ke memorije
Preslikavanje adresa kod direktno preslikane kemem rije
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memorije
Direct-Mapped Cache
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Direct-mapped cache holding 32 words within eight 4-word lines. Each line is
associated with a tag and a valid bit.
3-bit line index in cache
2-bit word offset in line Mainmemory
locations
0-34-7
8-11
36-3932-35
40-43
68-71
64-67
72-75
100-10396-99
104-107
TagWord
address
Valid bits
Tags Read tag andspecified word
Com-pare
1,Tag
Data out
Cache m iss1 if equal
pp
Skupno-asocijativna ke memorija
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031
Tag
Tag 0
Tag 1
Tag 2
Tag 1023
linija 0
linija 2
linija 1
linija1023
V D
V D
V D
V D
2
2
32
32
selekcija bajta
selekcija rei
selekcija bajta u
okviru rei
ka / sa magistrale
podataka
ke
pogodak
tag
pogodatak
adresa
valid
pogodak
Indeks
=
linija 0
linija 2
linija 1
linija 1023
1018
1
1
1
linija 0V D
Tag 0linija 0
= 118
18
MUX /DEMUX
32 32 32
MUX /DEMUXen
en
32ke
pogodak
1
Primer dvostruko skupno-asocijativne ke memorije
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p j j
Set-Associative Cache
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Two-way set-associative cache holding 32 words of data within
4-word lines and 2-line sets.
Mainmemory
locations
0-3
16-19
32-35
48-51
64-67
80-83
96-99
112-115
Valid bits
Tags
1
0
2-bit set index in cache
2-bit word offset in line
Tag Wordaddress
Option 0 Option 1
Read tag and specifiedword from each option
Com-pare
1,Tag Com-pare
Dataout
Cachemiss1 if equal
Poloaj kea u sistemu
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j
Poloaj kea u sistemu prod.
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j p
Virtuelni i realni ke
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Interni i eksterni ke
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K d U/I d i
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Ke u odnosu na U/I podsistem
Procenat promaaja u funkciji od obima kea
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p j j
Procenat promaaja u funkciji od obima kea
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Procenat promaaja u funkciji od obima kea
Politike zamene kod kea
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o t zam n o a
Virtual verus Physical memory
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The Need for Virtual Memory
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Program segments in main memory and on disk.
Program anddata on severaldisk tracks
System
Stack
Active piecesof program anddata in memory
Unusedspace
Memory Hierarchy: The Big Picture
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Data movement in a memory hierarchy.
Pages
Lines
Words
Registers
Main memory
Cache
Virtualmemory
(transferredexplicitly
via load/store)(transferred
automaticallyupon cache miss)
(transferred
automaticallyupon page fault)
Address Translation in Virtual Memory
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Virtual-to-physical address translation parameters.
Virtual
address
Physicaladdress
Physical page number
Virtual page number Offset in page
Offset in page
Address translation
Pbits
Pbits
VPbits
MPbits
Example Determine the parameters for 32-bit virtual addresses, 4 KBpages, and 128 MB byte-addressable main memory.
Solution:Physical addresses are 27 b, byte offset in page is 12 b;
thus, virtual (physical) page numbers are 3212 = 20 b (15 b)
Page Tables and Address Translation
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The role of page table in the virtual-to-physical address
translation process.
Page table
Main memory
Validbits
Page tableregister
Virtualpage
number
Otherflags
Protection and Sharing in Virtual Memory
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Virtual memory as a facilitator of sharing and memory
protection.
Page table forprocess 1
Main m emoryPermission bits
PointerFlags
Page table forprocess 2
To disk memory
Only read accessesallow ed
Read & w riteaccesses allowed
The Latency Penalty of Virtual Memory
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Page table
Main memory
Validbits
Page tableregister
Virtualpage
number
Otherflags
Virtual address
Memoryaccess 1
Physical address
Memory
access 2
Translation Lookaside Buffer
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Virtual-to-physical address translation by a TLB and how the
resulting physical address is used to access the cache memory.
Virtualpage number
Byteoffset
Byte offsetin wordPhysicaladdress tagCache index
Validbits
TLB tags
Tags matchand entryis valid
Physicalpage number Physical
address
Virtual
address
T
ranslation
Otherflags
Address Translation via TLB
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Example
An address translation process converts a 32-bit virtual address to a
32-bit physical address. Memory is byte-addressable with 4 KB pages.A 16-entry, direct-mapped TLB is used. Specify the components of the
virtual and physical addresses and the width of the various TLB fields.
Solution Virtualpage number
Byteoffset
Byte offsetin word
Physicaladdress tag
Cache index
Validbits
TLB tags
Tags matchand entryis valid
Physicalpage number Physical
address
Virtual
address
Translation
Otherflags
12
12
20
20
Virtual
Page number
416
TLB
index
Tag
TLB word width =
16-bit tag +
20-bit phys page # +
1 valid bit +
Other flags
37 bits16-entryTLB
Virtual- or Physical-Address Cache?
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Options for where virtual-to-physical address translation
occurs.
TLB Main memoryVirtual-addresscache
TLB Main memoryPhysical-address
cache
TLB
Main memoryHybrid-address
cache
Page Replacement Policies
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A scheme for the approximate implementation of LRU .
0
1
0
0
1
1
0
1
0
1
0
1
0
0
0
1
(a) Before replacement (b) After replacement
Least-recently used policy: effective, but hard to implement
Approximate versions of LRU are more easily implemented
Clock policy: diagram below shows the reason for name
Use bit is set to 1 whenever a page is accessed
Improving Virtual Memory Performance
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Memory hierarchy parameters and their effects on performance
Parameter variation Potential advantages Possible disadvantages
Larger main or cache
size
Fewer capacity misses Longer access time
Longer pages or lines Fewer compulsory misses(prefetching effect)
Greater miss penalty
Greater associativity
(for cache only)
Fewer conflict misses Longer access time
More sophisticated
replacement policy
Fewer conflict misses Longer decision time, more
hardware
Write-through policy
(for cache only)
No write-back time penalty,
easier write-miss handling
Wasted memory bandwidth,
longer access time
Summary of Memory Hierarchy
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Data mo ement in a memor hierarch
Pages
Lines
Words
Registers
Main memory
Cache
Virtualmemory
(transferredexplicitly
via load/store)
(transferred
automaticallyupon cache miss)
(transferredautomatically
upon page fault)
Cache memory:
provides illusion of
very high speed
Virtual memory:
provides illusion of
very large size
Main memory:
reasonable cost,
but slow & small
Localitymakes
the
illusions
work