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© 2011 Xilinx, Inc. All Rights ReservedThis material exempt per Department of ommerce license exception T!"
Xilinx Tool Flow
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© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only
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Objectives
After completing this module, you will be able to:% List the steps of the Xilinx design process
% Implement and simulate an FPGA design by using default softwareoptions
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© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only
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Outline
% Overview
% ISE Foundation
% Summary
% Lab ! Xilinx "ool Flow #emo
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© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only
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Translate
Map
Place & Route
Xilinx Design Flow
Plan & udget !"# RT#$imulation
$ynthesi%e
to create netlist
unctional
$imulation
Attain Timing'losure Timing$imulation
(mplement
'reate 'ode)$chematic
*enerate(T ile
'onfigure
P*A
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© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only
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Design Entry
% Plan and budget% $hiche%er method you use& you will need a tool to generate an
E#IF or 'G( netlist to bring into the Xilinx implementation tools – Popular synthesis tools include! Synplify& Precision& FPGA (ompiler II& and XS"
% "ools a%ailable to assist in design entry – Architecture $i)ard& (*+E Generator, system& and State(A# tools
% Simulate the design to ensure that it wor-s as expected.
Plan & udget 'reate 'ode)$chematic !"# RT#$imulation
$ynthesi%e
to create netlist
unctional
$imulation+ + +
(reate designs in /#L or Schematic
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© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only
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Synthesis
% After coding up your /#L code& you will need atool to generate a netlist 0'G( or E#IF1 – Xilinx Synthesis "ool 0XS"1 included
–
Support for Popular "hird Party Synthesis tools! Synplify andSynplify Pro from Synplicity& and Precision from 2entor
Graphics
Generate a netlist file
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m!lementation
% (onsists of three phases – Translate: 2erge multiple design files
into a single netlist
– Map: Group logical symbols from the
netlist 0gates1 into physical components
0slices and I*3s1
– Place & Route: Place components onto
the chip& connect the components& and
extract timing data into reports
% Access Xilinx reports and tools ateach phase – "iming Analy)er& Floorplanner& FPGA
Editor& XPower
"ranslate
2ap
Place 4 +oute
(mplement" " "
"""
'etlist Generated
From Synthesis
"""
Process a netlist file
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#on$iguration
% *nce a design is implemented& you must create a file that theFPGA can understand – "his file is called a bitstream! a 3I" file 05bit extension1
% "he 3I" file can be downloaded –
#irectly into the FPGA• 6se a download cable such as Platform 6S3
– "o external memory de%ice such as a Xilinx Platform Flash P+*2
• 2ust first be con%erted into a P+*2 file
"esting and 7erification
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Online So$tware %anualsSee #e%elopment System +eference Guide for Flow #iagrams
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Timing #losure
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Outline
% *%er%iew
% ($ oundation
% Summary
% Lab ! Xilinx "ool Flow#emo
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SE &roject 'avigator
% Enter #esigns
% Access to synthesis tools – Including third8party
synthesis tools
% Implement your design with a simple double8clic- – Fine8tune with easy8to8
access software options
% #ownload – Generate a bitstream
– (onfigure FPGA using
i2PA("
Xilinx ISE Foundation is built around the Xilinx #esign Flow
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Entering DesignsSource $i)ard a%ailable to assist with design entry
% Select source type – #esign Entry 2ethods
• Schematic• /#L source 07/#L and
7erilog1
– #esign Entry "ools• Architecture $i)ard• 32292E296(F Files• (ore Generator• (hipScope• Embedded Processor
• System Generator – Simulation "est 3ench
• 7/#L• 7erilog
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Synthesi(ing Designs
#ouble8clic- to
Synthesi)e
Generate a netlist file using XS" 0Xilinx Synthesis "echnology1
/ighlight /#L
Sources
:
% Synthesis Processes andAnalysis – Access report – 7iew Schematics 0+"L or
"echnology1 – (hec- Syntax – Generate Post8Synthesis
Simulation 2odel
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Tool #lo$ 1(
m!lementing Designs
% Implement a design – "ranslate
• Access reports• Post8"ranslate Simulation 2odel
– 2ap•
Access reports• Post82ap Static "iming• 2anually place components• Post82ap Simulation 2odel
– Place 4 +oute• Access reports•
Analy)e timing9Floorplan 0PlanAhead1• 2anually place 4 route components• And more
Process netlist generated from synthesis
/ighlight /#L
Sources
#ouble8clic- to
Implement
:
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The Design Summary
Dis!lays Design Data
% ;uic- 7iew of+eports&
(onstraints
% Pro
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Simulating Designs7erify the design with the ISE Simulator
Select simulation
/ighlight test
bench
=
#ouble8clic- to
simulate
>
% Add a test bench – 7/#L& 7erilog& or Xilinx wa%eform file
% Perform a 3eha%ioral Simulation – 6se 6'ISI296ni2acro library when FPGA
primiti%es are instantiated in the design – 6se Xilinx(oreLib library when IP cores are
instantiated in the design
% Perform a timing simulation – 6se Xilinx SI2P+I2 library when FPGA
primiti%es are instantiated in the design
% Smart2odels – Simulation library for both functional and
timing simulation of Xilinx /ard8IP such asPP(& P(Ie& G"& "E2A( are used in thedesign
Select simulation type:
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© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only
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#on$iguring F&)As
% (onfigure FPGAs from computer – 6se i2PA(" to download bitstream from
computer to FPGA %ia Xilinx download cable
0ie5 Platform 6S31
% (onfigure FPGAs from External 2emory – Xilinx Platform Flash
• 6se i2PA(" to generate P+*2 file and
download to P+*2 using Xilinx download cable
– Generic Parallel P+*2
• 6se i2PA(" to generate P+*2 file 8 nosupport for programming
– (ompact Flash 0Xilinx System A(E re?uired1
• 6se i2PA(" to generate SysA(E file 8 no
support for programming
#ouble8clic- to
generate 5bit
:
/ighlight source file
Generate P+*2 files and download to de%ices using i2PA("
#ouble8clic- to in%o-e
i2PA(" programming tools
=
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© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only
Tool #lo$ 1
Outline
% *%er%iew
% ISE
% $ummary
% Lab ! Xilinx "ool Flow
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© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only
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*eview +uestions
% $hat are the phases of the Xilinx design flow@% $hat are the components of implementation& and what
happens at each step@
% $hat are two methods of programming an FPGA@
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© 2011 Xilinx, Inc. All Rights Reserved For Academic Use Only
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Answers
% $hat are the phases of the Xilinx design flow@ – Plan and budget& create code or schematic& +"L simulation& synthesi)e&
functional simulation& implement& timing closure& timing simulation& and 3I" file
creation
% $hat are the components of implementation& and what happens ateach step@ – "ranslate! merges multiple design files into one netlist
– 2ap! groups logical symbols into physical components
– Place 4 +oute! places components onto the chip and connects them
% $hat are two methods of programming an FPGA@ – #irectly from (omputer
– From external memory de%ice
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Summary
% Implementation means more than Place 4 +oute% Xilinx pro%ides a simple pushbutton tool to guide you
through the Xilinx design process
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© 2011 Xili I All Ri h R d
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Outline
% *%er%iew
% ISE
% Summary
% #ab -: .ilin/ Tool low